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Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_screen.c')
-rw-r--r--src/mesa/drivers/dri/i965/brw_screen.c54
1 files changed, 27 insertions, 27 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_screen.c b/src/mesa/drivers/dri/i965/brw_screen.c
index 0f2b3f11309..83abe5c4ef7 100644
--- a/src/mesa/drivers/dri/i965/brw_screen.c
+++ b/src/mesa/drivers/dri/i965/brw_screen.c
@@ -396,7 +396,7 @@ modifier_is_supported(const struct gen_device_info *devinfo,
if (supported_modifiers[i].modifier != modifier)
continue;
- return supported_modifiers[i].since_gen <= devinfo->gen;
+ return supported_modifiers[i].since_gen <= devinfo->ver;
}
return false;
@@ -1919,7 +1919,7 @@ brw_detect_swizzling(struct brw_screen *screen)
* reserved, and the CPU's memory controller performs all address
* swizzling modifications."
*/
- if (screen->devinfo.gen >= 8)
+ if (screen->devinfo.ver >= 8)
return false;
uint32_t tiling = I915_TILING_X;
@@ -2085,10 +2085,10 @@ brw_detect_pipelined_so(struct brw_screen *screen)
const struct gen_device_info *devinfo = &screen->devinfo;
/* Supposedly, Broadwell just works. */
- if (devinfo->gen >= 8)
+ if (devinfo->ver >= 8)
return true;
- if (devinfo->gen <= 6)
+ if (devinfo->ver <= 6)
return false;
/* See the big explanation about command parser versions below */
@@ -2117,13 +2117,13 @@ brw_supported_msaa_modes(const struct brw_screen *screen)
static const int gen6_modes[] = {4, 0, -1};
static const int gen4_modes[] = {0, -1};
- if (screen->devinfo.gen >= 9) {
+ if (screen->devinfo.ver >= 9) {
return gen9_modes;
- } else if (screen->devinfo.gen >= 8) {
+ } else if (screen->devinfo.ver >= 8) {
return gen8_modes;
- } else if (screen->devinfo.gen >= 7) {
+ } else if (screen->devinfo.ver >= 7) {
return gen7_modes;
- } else if (screen->devinfo.gen == 6) {
+ } else if (screen->devinfo.ver == 6) {
return gen6_modes;
} else {
return gen4_modes;
@@ -2257,12 +2257,12 @@ brw_screen_make_configs(__DRIscreen *dri_screen)
stencil_bits[0] = 0;
if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) {
- if (devinfo->gen >= 8) {
+ if (devinfo->ver >= 8) {
depth_bits[num_depth_stencil_bits] = 16;
stencil_bits[num_depth_stencil_bits] = 0;
num_depth_stencil_bits++;
}
- if (devinfo->gen >= 6) {
+ if (devinfo->ver >= 6) {
depth_bits[num_depth_stencil_bits] = 24;
stencil_bits[num_depth_stencil_bits] = 8;
num_depth_stencil_bits++;
@@ -2294,10 +2294,10 @@ brw_screen_make_configs(__DRIscreen *dri_screen)
continue;
if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) {
- if (devinfo->gen >= 8) {
+ if (devinfo->ver >= 8) {
depth_bits[0] = 16;
stencil_bits[0] = 0;
- } else if (devinfo->gen >= 6) {
+ } else if (devinfo->ver >= 6) {
depth_bits[0] = 24;
stencil_bits[0] = 8;
} else {
@@ -2331,7 +2331,7 @@ brw_screen_make_configs(__DRIscreen *dri_screen)
* them.
*/
for (unsigned i = 0; i < num_formats; i++) {
- if (devinfo->gen < 6)
+ if (devinfo->ver < 6)
break;
if (!brw_allowed_format(dri_screen, formats[i]))
@@ -2345,7 +2345,7 @@ brw_screen_make_configs(__DRIscreen *dri_screen)
depth_bits[0] = 0;
stencil_bits[0] = 0;
- if (formats[i] == MESA_FORMAT_B5G6R5_UNORM && devinfo->gen >= 8) {
+ if (formats[i] == MESA_FORMAT_B5G6R5_UNORM && devinfo->ver >= 8) {
depth_bits[1] = 16;
stencil_bits[1] = 0;
} else {
@@ -2353,19 +2353,19 @@ brw_screen_make_configs(__DRIscreen *dri_screen)
stencil_bits[1] = 8;
}
- if (devinfo->gen >= 9) {
+ if (devinfo->ver >= 9) {
static const uint8_t multisample_samples_gen9[] = {2, 4, 8, 16};
multisample_samples = multisample_samples_gen9;
num_msaa_modes = ARRAY_SIZE(multisample_samples_gen9);
- } else if (devinfo->gen == 8) {
+ } else if (devinfo->ver == 8) {
static const uint8_t multisample_samples_gen8[] = {2, 4, 8};
multisample_samples = multisample_samples_gen8;
num_msaa_modes = ARRAY_SIZE(multisample_samples_gen8);
- } else if (devinfo->gen == 7) {
+ } else if (devinfo->ver == 7) {
static const uint8_t multisample_samples_gen7[] = {4, 8};
multisample_samples = multisample_samples_gen7;
num_msaa_modes = ARRAY_SIZE(multisample_samples_gen7);
- } else if (devinfo->gen == 6) {
+ } else if (devinfo->ver == 6) {
static const uint8_t multisample_samples_gen6[] = {4};
multisample_samples = multisample_samples_gen6;
num_msaa_modes = ARRAY_SIZE(multisample_samples_gen6);
@@ -2395,9 +2395,9 @@ static void
set_max_gl_versions(struct brw_screen *screen)
{
__DRIscreen *dri_screen = screen->driScrnPriv;
- const bool has_astc = screen->devinfo.gen >= 9;
+ const bool has_astc = screen->devinfo.ver >= 9;
- switch (screen->devinfo.gen) {
+ switch (screen->devinfo.ver) {
case 11:
case 10:
case 9:
@@ -2546,7 +2546,7 @@ __DRIconfig **brw_init_screen(__DRIscreen *dri_screen)
screen->deviceID = devinfo->chipset_id;
screen->no_hw = devinfo->no_hw;
- if (devinfo->gen >= 12) {
+ if (devinfo->ver >= 12) {
fprintf(stderr, "gen12 and newer are not supported on i965\n");
return NULL;
}
@@ -2556,7 +2556,7 @@ __DRIconfig **brw_init_screen(__DRIscreen *dri_screen)
brw_process_intel_debug_variable();
- if ((INTEL_DEBUG & DEBUG_SHADER_TIME) && devinfo->gen < 7) {
+ if ((INTEL_DEBUG & DEBUG_SHADER_TIME) && devinfo->ver < 7) {
fprintf(stderr,
"shader_time debugging requires gen7 (Ivybridge) or better.\n");
intel_debug &= ~DEBUG_SHADER_TIME;
@@ -2727,7 +2727,7 @@ __DRIconfig **brw_init_screen(__DRIscreen *dri_screen)
screen->kernel_features |= KERNEL_ALLOWS_SOL_OFFSET_WRITES;
}
- if (devinfo->gen >= 8 || screen->cmd_parser_version >= 2)
+ if (devinfo->ver >= 8 || screen->cmd_parser_version >= 2)
screen->kernel_features |= KERNEL_ALLOWS_PREDICATE_WRITES;
/* Haswell requires command parser version 4 in order to have L3
@@ -2742,13 +2742,13 @@ __DRIconfig **brw_init_screen(__DRIscreen *dri_screen)
* MI_MATH GPR registers, and version 7 in order to use
* MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
*/
- if (devinfo->gen >= 8 ||
+ if (devinfo->ver >= 8 ||
(devinfo->is_haswell && screen->cmd_parser_version >= 7)) {
screen->kernel_features |= KERNEL_ALLOWS_MI_MATH_AND_LRR;
}
/* Gen7 needs at least command parser version 5 to support compute */
- if (devinfo->gen >= 8 || screen->cmd_parser_version >= 5)
+ if (devinfo->ver >= 8 || screen->cmd_parser_version >= 5)
screen->kernel_features |= KERNEL_ALLOWS_COMPUTE_DISPATCH;
if (brw_get_boolean(screen, I915_PARAM_HAS_CONTEXT_ISOLATION))
@@ -2775,7 +2775,7 @@ __DRIconfig **brw_init_screen(__DRIscreen *dri_screen)
*
* Don't even try on pre-Gen6, since we don't attempt to use contexts there.
*/
- if (devinfo->gen >= 6) {
+ if (devinfo->ver >= 6) {
struct drm_i915_reset_stats stats;
memset(&stats, 0, sizeof(stats));
@@ -2796,7 +2796,7 @@ __DRIconfig **brw_init_screen(__DRIscreen *dri_screen)
* offset to an absolute address is only safe if the kernel isolates other
* contexts from our changes.
*/
- screen->compiler->constant_buffer_0_is_relative = devinfo->gen < 8 ||
+ screen->compiler->constant_buffer_0_is_relative = devinfo->ver < 8 ||
!(screen->kernel_features & KERNEL_ALLOWS_CONTEXT_ISOLATION);
screen->compiler->glsl_compiler_options[MESA_SHADER_VERTEX].PositionAlwaysInvariant = driQueryOptionb(&screen->optionCache, "vs_position_always_invariant");
generated by cgit v1.2.3 (git 2.39.1) at 2024-06-17 07:31:22 +0000