diff options
| author | Glenn Kennard <glenn.kennard@gmail.com> | 2014-07-23 10:48:17 +0200 |
|---|---|---|
| committer | Andreas Boll <andreas.boll.dev@gmail.com> | 2014-07-31 11:51:04 +0200 |
| commit | a48b615006942f92243fd7783f5ef9cf396be1d0 (patch) | |
| tree | c475606137c8ac2c0e95c4bf37b34fcf9fbd0111 /src | |
| parent | 1da4bb5b97a4b9458fad6f5e7dd4ec29f522f934 (diff) | |
r600g: Implement GL_ARB_texture_query_lod
Requires Evergreen or later
v2 (Andreas): Update relnotes/10.3
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v1)
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/r600/r600_pipe.c | 2 | ||||
| -rw-r--r-- | src/gallium/drivers/r600/r600_shader.c | 13 |
2 files changed, 13 insertions, 2 deletions
diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c index f243159982e..39edbcf4585 100644 --- a/src/gallium/drivers/r600/r600_pipe.c +++ b/src/gallium/drivers/r600/r600_pipe.c @@ -304,6 +304,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_CUBE_MAP_ARRAY: case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT: case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS: + case PIPE_CAP_TEXTURE_QUERY_LOD: return family >= CHIP_CEDAR ? 1 : 0; /* Unsupported features. */ @@ -314,7 +315,6 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_VERTEX_COLOR_CLAMPED: case PIPE_CAP_USER_VERTEX_BUFFERS: case PIPE_CAP_TEXTURE_GATHER_SM5: - case PIPE_CAP_TEXTURE_QUERY_LOD: case PIPE_CAP_SAMPLE_SHADING: case PIPE_CAP_TEXTURE_GATHER_OFFSETS: case PIPE_CAP_DRAW_INDIRECT: diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c index 9f4c3019aa8..0d9cb26784e 100644 --- a/src/gallium/drivers/r600/r600_shader.c +++ b/src/gallium/drivers/r600/r600_shader.c @@ -5104,13 +5104,21 @@ static int tgsi_tex(struct r600_shader_ctx *ctx) tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; + tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; + } + else if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ) { + tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; + tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; + tex.dst_sel_z = 7; + tex.dst_sel_w = 7; } else { tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; + tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; } - tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; + if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ) { tex.src_sel_x = 4; @@ -6666,6 +6674,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = { {TGSI_OPCODE_IMUL_HI, 0, ALU_OP0_NOP, tgsi_unsupported}, {TGSI_OPCODE_UMUL_HI, 0, ALU_OP0_NOP, tgsi_unsupported}, {TGSI_OPCODE_TG4, 0, FETCH_OP_GATHER4, tgsi_unsupported}, + {TGSI_OPCODE_LODQ, 0, FETCH_OP_GET_LOD, tgsi_unsupported}, {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported}, }; @@ -6860,6 +6869,7 @@ static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = { {TGSI_OPCODE_IMUL_HI, 0, ALU_OP0_NOP, tgsi_unsupported}, {TGSI_OPCODE_UMUL_HI, 0, ALU_OP0_NOP, tgsi_unsupported}, {TGSI_OPCODE_TG4, 0, FETCH_OP_GATHER4, tgsi_tex}, + {TGSI_OPCODE_LODQ, 0, FETCH_OP_GET_LOD, tgsi_tex}, {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported}, }; @@ -7055,5 +7065,6 @@ static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = { {TGSI_OPCODE_IMUL_HI, 0, ALU_OP0_NOP, tgsi_unsupported}, {TGSI_OPCODE_UMUL_HI, 0, ALU_OP0_NOP, tgsi_unsupported}, {TGSI_OPCODE_TG4, 0, FETCH_OP_GATHER4, tgsi_tex}, + {TGSI_OPCODE_LODQ, 0, FETCH_OP_GET_LOD, tgsi_tex}, {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported}, }; |