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authorJerome Glisse <jglisse@redhat.com>2012-10-11 10:40:30 -0400
committerJerome Glisse <jglisse@redhat.com>2012-12-20 18:23:51 -0500
commit6532eb17baff6e61b427f29e076883f8941ae664 (patch)
tree8a2fbc76f6037381017d81148996a4db6598254a /src/gallium/drivers/r600/r600d.h
parent24b1206ab2dcd506aaac3ef656aebc8bc20cd27a (diff)
r600g: add htile support v16
htile is used for HiZ and HiS support and fast Z/S clears. This commit just adds the htile setup and Fast Z clear. We don't take full advantage of HiS with that patch. v2 really use fast clear, still random issue with some tiles need to try more flush combination, fix depth/stencil texture decompression v3 fix random issue on r6xx/r7xx v4 rebase on top of lastest mesa, disable CB export when clearing htile surface to avoid wasting bandwidth v5 resummarize htile surface when uploading z value. Fix z/stencil decompression, the custom blitter with custom dsa is no longer needed. v6 Reorganize render control/override update mecanism, fixing more issues in the process. v7 Add nop after depth surface base update to work around some htile flushing issue. For htile to 8x8 on r6xx/r7xx as other combination have issue. Do not enable hyperz when flushing/uncompressing depth buffer. v8 Fix htile surface, preload and prefetch setup. Only set preload and prefetch on htile surface clear like fglrx. Record depth clear value per level. Support several level for the htile surface. First depth clear can't be a fast clear. v9 Fix comments, properly account new register in emit function, disable fast zclear if clearing different layer of texture array to different value v10 Disable hyperz for texture array making test simpler. Force db_misc_state update when no depth buffer is bound. Remove unused variable, rename depth_clearstencil to depth_clear. Don't allocate htile surface for flushed depth. Something broken the cliprect change, this need to be investigated. v11 Rebase on top of newer mesa v12 Rebase on top of newer mesa v13 Rebase on top of newer mesa, htile surface need to be initialized to zero, somehow special casing first clear to not use fast clear and thus initialize the htile surface with proper value does not work in all case. v14 Use resource not texture for htile buffer make the htile buffer size computation easier and simpler. Disable preload on evergreen as its still troublesome in some case v15 Cleanup some comment and remove some left over v16 Define name for bit 20 of CP_COHER_CNTL Signed-off-by: Pierre-Eric Pelloux-Prayer <pelloux@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Diffstat (limited to 'src/gallium/drivers/r600/r600d.h')
-rw-r--r--src/gallium/drivers/r600/r600d.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h
index 78fa6b689ec..69bfd7a2f87 100644
--- a/src/gallium/drivers/r600/r600d.h
+++ b/src/gallium/drivers/r600/r600d.h
@@ -530,6 +530,7 @@
#define S_028010_ZRANGE_PRECISION(x) (((x) & 0x1) << 31)
#define G_028010_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1)
#define C_028010_ZRANGE_PRECISION 0x7FFFFFFF
+#define R_028014_DB_HTILE_DATA_BASE 0x00028014
#define R_028414_CB_BLEND_RED 0x028414
#define S_028414_BLEND_RED(x) (((x) & 0xFFFFFFFF) << 0)
#define G_028414_BLEND_RED(x) (((x) >> 0) & 0xFFFFFFFF)
@@ -3360,6 +3361,10 @@
#define S_0085F0_CB11_DEST_BASE_ENA(x) (((x) & 0x1) << 18)
#define G_0085F0_CB11_DEST_BASE_ENA(x) (((x) >> 18) & 0x1)
/* evergreen only end */
+/* evergreen and r7xx only */
+#define S_0085F0_FULL_CACHE_ENA(x) (((x) & 0x1) << 20)
+#define G_0085F0_FULL_CACHE_ENA(x) (((x) >> 20) & 0x1)
+/* evergreen and r7xx only end */
#define S_0085F0_TC_ACTION_ENA(x) (((x) & 0x1) << 23)
#define G_0085F0_TC_ACTION_ENA(x) (((x) >> 23) & 0x1)
#define C_0085F0_TC_ACTION_ENA 0xFF7FFFFF