diff options
| author | Marek Olšák <marek.olsak@amd.com> | 2022-05-12 02:50:17 -0400 |
|---|---|---|
| committer | Marek Olšák <marek.olsak@amd.com> | 2022-05-13 14:56:22 -0400 |
| commit | 39800f0fa3104c56736d5beb70a7920a33be48de (patch) | |
| tree | 8c658b5a75bc52b5fe0a66c09d4f326438cf4508 /src/gallium/drivers/r600/r600_texture.c | |
| parent | 6dcf7f651f421c0f46ebf9c4c5904f452ea14eb1 (diff) | |
amd: change chip_class naming to "enum amd_gfx_level gfx_level"
This aligns the naming with PAL.
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pellou-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16469>
Diffstat (limited to 'src/gallium/drivers/r600/r600_texture.c')
| -rw-r--r-- | src/gallium/drivers/r600/r600_texture.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c index 2be8c90ebda..930e9b6dd9f 100644 --- a/src/gallium/drivers/r600/r600_texture.c +++ b/src/gallium/drivers/r600/r600_texture.c @@ -213,7 +213,7 @@ static int r600_init_surface(struct r600_common_screen *rscreen, is_depth = util_format_has_depth(desc); is_stencil = util_format_has_stencil(desc); - if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth && + if (rscreen->gfx_level >= EVERGREEN && !is_flushed_depth && ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) { bpe = 4; /* stencil is allocated separately on evergreen */ } else { @@ -365,7 +365,7 @@ static void r600_reallocate_texture_inplace(struct r600_common_context *rctx, templ.bind |= new_bind_flag; /* r600g doesn't react to dirty_tex_descriptor_counter */ - if (rctx->chip_class < GFX6) + if (rctx->gfx_level < GFX6) return; if (rtex->resource.b.is_shared) @@ -630,7 +630,7 @@ void r600_texture_get_fmask_info(struct r600_common_screen *rscreen, /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption. * This can be fixed by writing a separate FMASK allocator specifically * for R600-R700 asics. */ - if (rscreen->chip_class <= R700) { + if (rscreen->gfx_level <= R700) { bpe *= 2; } @@ -756,12 +756,12 @@ static void r600_texture_get_htile_size(struct r600_common_screen *rscreen, rtex->surface.meta_size = 0; - if (rscreen->chip_class <= EVERGREEN && + if (rscreen->gfx_level <= EVERGREEN && rscreen->info.drm_minor < 26) return; /* HW bug on R6xx. */ - if (rscreen->chip_class == R600 && + if (rscreen->gfx_level == R600 && (rtex->resource.b.b.width0 > 7680 || rtex->resource.b.b.height0 > 7680)) return; @@ -933,7 +933,7 @@ r600_texture_create_object(struct pipe_screen *screen, if (rtex->is_depth) { if (base->flags & (R600_RESOURCE_FLAG_TRANSFER | R600_RESOURCE_FLAG_FLUSHED_DEPTH) || - rscreen->chip_class >= EVERGREEN) { + rscreen->gfx_level >= EVERGREEN) { rtex->can_sample_z = !rtex->surface.u.legacy.depth_adjusted; rtex->can_sample_s = !rtex->surface.u.legacy.stencil_adjusted; } else { @@ -1043,7 +1043,7 @@ r600_choose_tiling(struct r600_common_screen *rscreen, return RADEON_SURF_MODE_LINEAR_ALIGNED; /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */ - if (rscreen->chip_class >= R600 && rscreen->chip_class <= CAYMAN && + if (rscreen->gfx_level >= R600 && rscreen->gfx_level <= CAYMAN && (templ->bind & PIPE_BIND_COMPUTE_RESOURCE) && (templ->target == PIPE_TEXTURE_2D || templ->target == PIPE_TEXTURE_3D)) @@ -1253,7 +1253,7 @@ static bool r600_can_invalidate_texture(struct r600_common_screen *rscreen, const struct pipe_box *box) { /* r600g doesn't react to dirty_tex_descriptor_counter */ - return rscreen->chip_class >= GFX6 && + return rscreen->gfx_level >= GFX6 && !rtex->resource.b.is_shared && !(transfer_usage & PIPE_MAP_READ) && rtex->resource.b.b.last_level == 0 && |