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| author | Bryan Cain <bryancain3@gmail.com> | 2011-09-10 12:31:54 -0500 |
|---|---|---|
| committer | Bryan Cain <bryancain3@gmail.com> | 2011-09-10 12:46:41 -0500 |
| commit | 324ac982d8e7c2693035342de2d24baff3042911 (patch) | |
| tree | 2292218438c582665e41c1c64db654607589956b /src/gallium/docs | |
| parent | 9222c497f9e73ae19b1b4dab1d9c9b4aa797b11d (diff) | |
gallium: add TGSI opcodes UARL and UCMP
They are needed by glsl_to_tgsi for an efficient implementation using native
integers.
Reviewed-by: Brian Paul <brianp@vmware.com>
Diffstat (limited to 'src/gallium/docs')
| -rw-r--r-- | src/gallium/docs/source/tgsi.rst | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/src/gallium/docs/source/tgsi.rst b/src/gallium/docs/source/tgsi.rst index 5cf08752e75..d7f50b1a6e8 100644 --- a/src/gallium/docs/source/tgsi.rst +++ b/src/gallium/docs/source/tgsi.rst @@ -1013,6 +1013,25 @@ XXX so let's discuss it, yeah? dst.w = src0.w \oplus src1.w +.. opcode:: UCMP - Integer Conditional Move + +.. math:: + + dst.x = src0.x ? src1.x : src2.x + + dst.y = src0.y ? src1.y : src2.y + + dst.z = src0.z ? src1.z : src2.z + + dst.w = src0.w ? src1.w : src2.w + + +.. opcode:: UARL - Integer Address Register Load + + Moves the contents of the source register, assumed to be an integer, into the + destination register, which is assumed to be an address (ADDR) register. + + .. opcode:: SAD - Sum Of Absolute Differences .. math:: |