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authorMarek Olšák <marek.olsak@amd.com>2013-08-11 02:15:12 +0200
committerMarek Olšák <marek.olsak@amd.com>2013-08-27 23:18:54 +0200
commitadb93e3bda13ed539f383787c09f948d0f27fbcb (patch)
tree146b838c9a9533cc8f0f1ef55778865afeffde00
parentaa3905423e398e1ba36502ae91339d1303acf77f (diff)
r300g: enable MSAA on r300-r400, be careful about using color compression
MSAA was tested by one user on RS690 and it works for him with color compression (CMASK) disabled. Our theory is that his chipset lacks CMASK RAM. Since we don't have hardware documentation about which chipsets actually have CMASK RAM, I had to take a guess based on the presence of HiZ. Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--src/gallium/drivers/r300/r300_chipset.c8
-rw-r--r--src/gallium/drivers/r300/r300_chipset.h2
-rw-r--r--src/gallium/drivers/r300/r300_screen.c5
-rw-r--r--src/gallium/drivers/r300/r300_texture_desc.c4
4 files changed, 14 insertions, 5 deletions
diff --git a/src/gallium/drivers/r300/r300_chipset.c b/src/gallium/drivers/r300/r300_chipset.c
index 30e085ac517..c1f5e3cee1f 100644
--- a/src/gallium/drivers/r300/r300_chipset.c
+++ b/src/gallium/drivers/r300/r300_chipset.c
@@ -84,6 +84,7 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps)
84 caps->num_vert_fpus = 0; 84 caps->num_vert_fpus = 0;
85 caps->hiz_ram = 0; 85 caps->hiz_ram = 0;
86 caps->zmask_ram = 0; 86 caps->zmask_ram = 0;
87 caps->has_cmask = FALSE;
87 88
88 89
89 switch (caps->family) { 90 switch (caps->family) {
@@ -91,6 +92,7 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps)
91 case CHIP_R350: 92 case CHIP_R350:
92 caps->high_second_pipe = TRUE; 93 caps->high_second_pipe = TRUE;
93 caps->num_vert_fpus = 4; 94 caps->num_vert_fpus = 4;
95 caps->has_cmask = TRUE; /* guessed because there is also HiZ */
94 caps->hiz_ram = R300_HIZ_LIMIT; 96 caps->hiz_ram = R300_HIZ_LIMIT;
95 caps->zmask_ram = PIPE_ZMASK_SIZE; 97 caps->zmask_ram = PIPE_ZMASK_SIZE;
96 break; 98 break;
@@ -105,6 +107,7 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps)
105 case CHIP_RV380: 107 case CHIP_RV380:
106 caps->high_second_pipe = TRUE; 108 caps->high_second_pipe = TRUE;
107 caps->num_vert_fpus = 2; 109 caps->num_vert_fpus = 2;
110 caps->has_cmask = TRUE; /* guessed because there is also HiZ */
108 caps->hiz_ram = R300_HIZ_LIMIT; 111 caps->hiz_ram = R300_HIZ_LIMIT;
109 caps->zmask_ram = RV3xx_ZMASK_SIZE; 112 caps->zmask_ram = RV3xx_ZMASK_SIZE;
110 break; 113 break;
@@ -127,24 +130,28 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps)
127 case CHIP_R481: 130 case CHIP_R481:
128 case CHIP_RV410: 131 case CHIP_RV410:
129 caps->num_vert_fpus = 6; 132 caps->num_vert_fpus = 6;
133 caps->has_cmask = TRUE; /* guessed because there is also HiZ */
130 caps->hiz_ram = R300_HIZ_LIMIT; 134 caps->hiz_ram = R300_HIZ_LIMIT;
131 caps->zmask_ram = PIPE_ZMASK_SIZE; 135 caps->zmask_ram = PIPE_ZMASK_SIZE;
132 break; 136 break;
133 137
134 case CHIP_R520: 138 case CHIP_R520:
135 caps->num_vert_fpus = 8; 139 caps->num_vert_fpus = 8;
140 caps->has_cmask = TRUE;
136 caps->hiz_ram = R300_HIZ_LIMIT; 141 caps->hiz_ram = R300_HIZ_LIMIT;
137 caps->zmask_ram = PIPE_ZMASK_SIZE; 142 caps->zmask_ram = PIPE_ZMASK_SIZE;
138 break; 143 break;
139 144
140 case CHIP_RV515: 145 case CHIP_RV515:
141 caps->num_vert_fpus = 2; 146 caps->num_vert_fpus = 2;
147 caps->has_cmask = TRUE;
142 caps->hiz_ram = R300_HIZ_LIMIT; 148 caps->hiz_ram = R300_HIZ_LIMIT;
143 caps->zmask_ram = PIPE_ZMASK_SIZE; 149 caps->zmask_ram = PIPE_ZMASK_SIZE;
144 break; 150 break;
145 151
146 case CHIP_RV530: 152 case CHIP_RV530:
147 caps->num_vert_fpus = 5; 153 caps->num_vert_fpus = 5;
154 caps->has_cmask = TRUE;
148 caps->hiz_ram = RV530_HIZ_LIMIT; 155 caps->hiz_ram = RV530_HIZ_LIMIT;
149 caps->zmask_ram = PIPE_ZMASK_SIZE; 156 caps->zmask_ram = PIPE_ZMASK_SIZE;
150 break; 157 break;
@@ -153,6 +160,7 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps)
153 case CHIP_RV560: 160 case CHIP_RV560:
154 case CHIP_RV570: 161 case CHIP_RV570:
155 caps->num_vert_fpus = 8; 162 caps->num_vert_fpus = 8;
163 caps->has_cmask = TRUE;
156 caps->hiz_ram = RV530_HIZ_LIMIT; 164 caps->hiz_ram = RV530_HIZ_LIMIT;
157 caps->zmask_ram = PIPE_ZMASK_SIZE; 165 caps->zmask_ram = PIPE_ZMASK_SIZE;
158 break; 166 break;
diff --git a/src/gallium/drivers/r300/r300_chipset.h b/src/gallium/drivers/r300/r300_chipset.h
index f8b5d4e3d3e..8e9deb6057c 100644
--- a/src/gallium/drivers/r300/r300_chipset.h
+++ b/src/gallium/drivers/r300/r300_chipset.h
@@ -55,6 +55,8 @@ struct r300_capabilities {
55 int hiz_ram; 55 int hiz_ram;
56 /* Some chipsets have zmask ram per pipe some don't. */ 56 /* Some chipsets have zmask ram per pipe some don't. */
57 int zmask_ram; 57 int zmask_ram;
58 /* CMASK is for MSAA colorbuffer compression and fast clear. */
59 boolean has_cmask;
58 /* Compression mode for ZMASK. */ 60 /* Compression mode for ZMASK. */
59 enum r300_zmask_compression z_compress; 61 enum r300_zmask_compression z_compress;
60 /* Whether or not this is RV350 or newer, including all r400 and r500 62 /* Whether or not this is RV350 or newer, including all r400 and r500
diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c
index 5a388970c9b..063bc0922a1 100644
--- a/src/gallium/drivers/r300/r300_screen.c
+++ b/src/gallium/drivers/r300/r300_screen.c
@@ -444,11 +444,6 @@ static boolean r300_is_format_supported(struct pipe_screen* screen,
444 if (!drm_2_8_0) { 444 if (!drm_2_8_0) {
445 return FALSE; 445 return FALSE;
446 } 446 }
447 /* Only support R500, because I didn't test older chipsets,
448 * but MSAA should work there too. */
449 if (!is_r500 && !debug_get_bool_option("RADEON_MSAA", FALSE)) {
450 return FALSE;
451 }
452 /* No texturing and scanout. */ 447 /* No texturing and scanout. */
453 if (usage & (PIPE_BIND_SAMPLER_VIEW | 448 if (usage & (PIPE_BIND_SAMPLER_VIEW |
454 PIPE_BIND_DISPLAY_TARGET | 449 PIPE_BIND_DISPLAY_TARGET |
diff --git a/src/gallium/drivers/r300/r300_texture_desc.c b/src/gallium/drivers/r300/r300_texture_desc.c
index 8d96b5684ad..8fa98c5804e 100644
--- a/src/gallium/drivers/r300/r300_texture_desc.c
+++ b/src/gallium/drivers/r300/r300_texture_desc.c
@@ -417,6 +417,10 @@ static void r300_setup_cmask_properties(struct r300_screen *screen,
417 static unsigned cmask_align_y[4] = {16, 16, 16, 32}; 417 static unsigned cmask_align_y[4] = {16, 16, 16, 32};
418 unsigned pipes, stride, cmask_num_dw, cmask_max_size; 418 unsigned pipes, stride, cmask_num_dw, cmask_max_size;
419 419
420 if (!screen->caps.has_cmask) {
421 return;
422 }
423
420 /* We need an AA colorbuffer, no mipmaps. */ 424 /* We need an AA colorbuffer, no mipmaps. */
421 if (tex->b.b.nr_samples <= 1 || 425 if (tex->b.b.nr_samples <= 1 ||
422 tex->b.b.last_level > 0 || 426 tex->b.b.last_level > 0 ||