r600g: Support emitting scratch ops

Signed-off-by: Glenn Kennard <glenn.kennard@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

4 files changed, 77 insertions, 1 deletions

diff --git a/src/gallium/drivers/r600/eg_asm.c b/src/gallium/drivers/r600/eg_asm.c
index c03a9d84da4..acf3fd37416 100644
--- a/src/gallium/drivers/r600/eg_asm.c
+++ b/src/gallium/drivers/r600/eg_asm.c
@@ -112,7 +112,8 @@ int eg_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf)
 			                S_SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE(cf->vpm) |
 					S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) |
 					S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf->output.comp_mask) |
-					S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf->output.array_size);
+					S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf->output.array_size) |
+					S_SQ_CF_ALLOC_EXPORT_WORD1_MARK(cf->output.mark);
 			if (bc->chip_class == EVERGREEN) /* no EOP on cayman */
 				bc->bytecode[id] |= S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->end_of_program);
 			id++;
diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c
index ec2d34e9504..5b74be1748a 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -1510,6 +1510,8 @@ int cm_bytecode_add_cf_end(struct r600_bytecode *bc)
 /* common to all 3 families */
 static int r600_bytecode_vtx_build(struct r600_bytecode *bc, struct r600_bytecode_vtx *vtx, unsigned id)
 {
+	if (r600_isa_fetch(vtx->op)->flags & FF_MEM)
+		return r700_bytecode_fetch_mem_build(bc, vtx, id);
 	bc->bytecode[id] = S_SQ_VTX_WORD0_VTX_INST(r600_isa_fetch_opcode(bc->isa->hw_class, vtx->op)) |
 			S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
 			S_SQ_VTX_WORD0_FETCH_TYPE(vtx->fetch_type) |
@@ -2190,6 +2192,10 @@ void r600_bytecode_disasm(struct r600_bytecode *bc)
 					fprintf(stderr, "NO_BARRIER ");
 				if (cf->end_of_program)
 					fprintf(stderr, "EOP ");
+
+				if (cf->output.mark)
+					fprintf(stderr, "MARK ");
+
 				fprintf(stderr, "\n");
 			} else {
 				fprintf(stderr, "%04d %08X %08X  %s ", id, bc->bytecode[id],
@@ -2323,6 +2329,8 @@ void r600_bytecode_disasm(struct r600_bytecode *bc)
 
 			o += fprintf(stderr, ", R%d.", vtx->src_gpr);
 			o += print_swizzle(vtx->src_sel_x);
+			if (r600_isa_fetch(vtx->op)->flags & FF_MEM)
+				o += print_swizzle(vtx->src_sel_y);
 
 			if (vtx->offset)
 				fprintf(stderr, " +%db", vtx->offset);
@@ -2339,6 +2347,19 @@ void r600_bytecode_disasm(struct r600_bytecode *bc)
 			if (bc->chip_class >= EVERGREEN && vtx->buffer_index_mode)
 				fprintf(stderr, "SQ_%s ", index_mode[vtx->buffer_index_mode]);
 
+			if (r600_isa_fetch(vtx->op)->flags & FF_MEM) {
+				if (vtx->uncached)
+					fprintf(stderr, "UNCACHED ");
+				if (vtx->indexed)
+					fprintf(stderr, "INDEXED:%d ", vtx->indexed);
+
+				fprintf(stderr, "ELEM_SIZE:%d ", vtx->elem_size);
+				if (vtx->burst_count)
+					fprintf(stderr, "BURST_COUNT:%d ", vtx->burst_count);
+				fprintf(stderr, "ARRAY_BASE:%d ", vtx->array_base);
+				fprintf(stderr, "ARRAY_SIZE:%d ", vtx->array_size);
+			}
+
 			fprintf(stderr, "UCF:%d ", vtx->use_const_fields);
 			fprintf(stderr, "FMT(DTA:%d ", vtx->data_format);
 			fprintf(stderr, "NUM:%d ", vtx->num_format_all);
diff --git a/src/gallium/drivers/r600/r600_asm.h b/src/gallium/drivers/r600/r600_asm.h
index d7cb64f0b7d..b8abdf014d7 100644
--- a/src/gallium/drivers/r600/r600_asm.h
+++ b/src/gallium/drivers/r600/r600_asm.h
@@ -116,6 +116,17 @@ struct r600_bytecode_vtx {
 	unsigned			offset;
 	unsigned			endian;
 	unsigned			buffer_index_mode;
+
+	// READ_SCRATCH fields
+	unsigned			uncached;
+	unsigned			indexed;
+	unsigned			src_sel_y;
+	unsigned			src_rel;
+	unsigned			elem_size;
+	unsigned			array_size;
+	unsigned			array_base;
+	unsigned			burst_count;
+	unsigned			dst_rel;
 };
 
 struct r600_bytecode_gds {
@@ -155,6 +166,7 @@ struct r600_bytecode_output {
 	unsigned			swizzle_w;
 	unsigned			burst_count;
 	unsigned			index_gpr;
+	unsigned			mark; /* used by MEM_SCRATCH */
 };
 
 struct r600_bytecode_rat {
@@ -313,6 +325,9 @@ int r700_bytecode_alu_build(struct r600_bytecode *bc,
 		struct r600_bytecode_alu *alu, unsigned id);
 void r700_bytecode_alu_read(struct r600_bytecode *bc,
 		struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1);
+int r700_bytecode_fetch_mem_build(struct r600_bytecode *bc,
+		struct r600_bytecode_vtx *mem, unsigned id);
+
 void r600_bytecode_export_read(struct r600_bytecode *bc,
 		struct r600_bytecode_output *output, uint32_t word0, uint32_t word1);
 void eg_bytecode_export_read(struct r600_bytecode *bc,
diff --git a/src/gallium/drivers/r600/r700_asm.c b/src/gallium/drivers/r600/r700_asm.c
index 395059cfeaa..adf5445a2f5 100644
--- a/src/gallium/drivers/r600/r700_asm.c
+++ b/src/gallium/drivers/r600/r700_asm.c
@@ -124,3 +124,42 @@ void r700_bytecode_alu_read(struct r600_bytecode *bc,
 			G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(word1);
 	}
 }
+
+int r700_bytecode_fetch_mem_build(struct r600_bytecode *bc, struct r600_bytecode_vtx *mem, unsigned id)
+{
+	unsigned opcode = r600_isa_fetch_opcode(bc->isa->hw_class, mem->op) >> 8;
+
+	bc->bytecode[id++] = S_SQ_MEM_RD_WORD0_MEM_INST(2) |
+		S_SQ_MEM_RD_WORD0_ELEM_SIZE(mem->elem_size) |
+		S_SQ_MEM_RD_WORD0_FETCH_WHOLE_QUAD(0) |
+		S_SQ_MEM_RD_WORD0_MEM_OP(opcode) |
+		S_SQ_MEM_RD_WORD0_UNCACHED(mem->uncached) |
+		S_SQ_MEM_RD_WORD0_INDEXED(mem->indexed) |
+		S_SQ_MEM_RD_WORD0_SRC_SEL_Y(mem->src_sel_y) |
+		S_SQ_MEM_RD_WORD0_SRC_GPR(mem->src_gpr) |
+		S_SQ_MEM_RD_WORD0_SRC_REL(mem->src_rel) |
+		S_SQ_MEM_RD_WORD0_SRC_SEL_X(mem->src_sel_x) |
+		S_SQ_MEM_RD_WORD0_BURST_COUNT(mem->burst_count) |
+		S_SQ_MEM_RD_WORD0_LDS_REQ(0) |
+		S_SQ_MEM_RD_WORD0_COALESCED_READ(0);
+
+	bc->bytecode[id++] = S_SQ_MEM_RD_WORD1_DST_GPR(mem->dst_gpr) |
+		S_SQ_MEM_RD_WORD1_DST_REL(mem->dst_rel) |
+		S_SQ_MEM_RD_WORD1_DST_SEL_X(mem->dst_sel_x) |
+		S_SQ_MEM_RD_WORD1_DST_SEL_Y(mem->dst_sel_y) |
+		S_SQ_MEM_RD_WORD1_DST_SEL_W(mem->dst_sel_w) |
+		S_SQ_MEM_RD_WORD1_DST_SEL_Z(mem->dst_sel_z) |
+		S_SQ_MEM_RD_WORD1_DATA_FORMAT(mem->data_format) |
+		S_SQ_MEM_RD_WORD1_NUM_FORMAT_ALL(mem->num_format_all) |
+		S_SQ_MEM_RD_WORD1_FORMAT_COMP_ALL(mem->format_comp_all) |
+		S_SQ_MEM_RD_WORD1_SRF_MODE_ALL(mem->srf_mode_all);
+
+	bc->bytecode[id++] = S_SQ_MEM_RD_WORD2_ARRAY_BASE(mem->array_base) |
+		S_SQ_MEM_RD_WORD2_ENDIAN_SWAP(0) |
+		S_SQ_MEM_RD_WORD2_ARRAY_SIZE(mem->array_size);
+
+
+	bc->bytecode[id++] = 0; /* MEM ops are 4 word aligned */
+
+	return 0;
+}