summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorBen Skeggs <bskeggs@redhat.com>2012-02-16 22:08:41 +1000
committerBen Skeggs <bskeggs@redhat.com>2012-04-14 02:56:30 +1000
commit66c7dc5688bcd5ff9c596f4c410aee574ea2428a (patch)
treebf81b2190f93b4b1a9a7a8d2c41c7b6569810f59
parentf3d8bd3f7b9f5c6387cd5e629a82db9ad9a1e652 (diff)
nvfx: completely remove this driver (GeForce FX/6/7)
This driver hasn't been maintained properly for a very long time, and for many very good reasons. It's horrible. A new driver supporting these chipsets will appear with the commits that port vieux/nv50/nvc0 to libdrm_nouveau-2.0. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat
-rw-r--r--configure.ac2
-rw-r--r--src/gallium/drivers/nouveau/nouveau_video.c50
-rw-r--r--src/gallium/drivers/nouveau/nouveau_winsys.h3
-rw-r--r--src/gallium/drivers/nvfx/Android.mk37
-rw-r--r--src/gallium/drivers/nvfx/Makefile16
-rw-r--r--src/gallium/drivers/nvfx/Makefile.sources22
-rw-r--r--src/gallium/drivers/nvfx/SConscript14
-rw-r--r--src/gallium/drivers/nvfx/nv01_2d.xml.h1343
-rw-r--r--src/gallium/drivers/nvfx/nv04_2d.c1393
-rw-r--r--src/gallium/drivers/nvfx/nv04_2d.h107
-rw-r--r--src/gallium/drivers/nvfx/nv04_2d_loops.h70
-rw-r--r--src/gallium/drivers/nvfx/nv30-40_3d.xml.h2022
-rw-r--r--src/gallium/drivers/nvfx/nv30_fragtex.c117
-rw-r--r--src/gallium/drivers/nvfx/nv30_vertprog.h176
-rw-r--r--src/gallium/drivers/nvfx/nv40_fragtex.c104
-rw-r--r--src/gallium/drivers/nvfx/nv40_vertprog.h178
-rw-r--r--src/gallium/drivers/nvfx/nvfx_buffer.c98
-rw-r--r--src/gallium/drivers/nvfx/nvfx_clear.c14
-rw-r--r--src/gallium/drivers/nvfx/nvfx_context.c124
-rw-r--r--src/gallium/drivers/nvfx/nvfx_context.h375
-rw-r--r--src/gallium/drivers/nvfx/nvfx_draw.c191
-rw-r--r--src/gallium/drivers/nvfx/nvfx_fragprog.c1624
-rw-r--r--src/gallium/drivers/nvfx/nvfx_fragtex.c355
-rw-r--r--src/gallium/drivers/nvfx/nvfx_miptree.c214
-rw-r--r--src/gallium/drivers/nvfx/nvfx_push.c431
-rw-r--r--src/gallium/drivers/nvfx/nvfx_query.c147
-rw-r--r--src/gallium/drivers/nvfx/nvfx_resource.c66
-rw-r--r--src/gallium/drivers/nvfx/nvfx_resource.h194
-rw-r--r--src/gallium/drivers/nvfx/nvfx_screen.c665
-rw-r--r--src/gallium/drivers/nvfx/nvfx_screen.h65
-rw-r--r--src/gallium/drivers/nvfx/nvfx_shader.h526
-rw-r--r--src/gallium/drivers/nvfx/nvfx_state.c389
-rw-r--r--src/gallium/drivers/nvfx/nvfx_state.h115
-rw-r--r--src/gallium/drivers/nvfx/nvfx_state_emit.c439
-rw-r--r--src/gallium/drivers/nvfx/nvfx_state_fb.c290
-rw-r--r--src/gallium/drivers/nvfx/nvfx_surface.c413
-rw-r--r--src/gallium/drivers/nvfx/nvfx_surface.h0
-rw-r--r--src/gallium/drivers/nvfx/nvfx_tex.h175
-rw-r--r--src/gallium/drivers/nvfx/nvfx_transfer.c221
-rw-r--r--src/gallium/drivers/nvfx/nvfx_transfer.h24
-rw-r--r--src/gallium/drivers/nvfx/nvfx_vbo.c637
-rw-r--r--src/gallium/drivers/nvfx/nvfx_vertprog.c1453
-rw-r--r--src/gallium/targets/dri-nouveau/Makefile1
-rw-r--r--src/gallium/targets/vdpau-nouveau/Makefile1
-rw-r--r--src/gallium/targets/xorg-nouveau/Makefile1
-rw-r--r--src/gallium/targets/xvmc-nouveau/Makefile1
-rw-r--r--src/gallium/winsys/nouveau/drm/nouveau_drm_winsys.c4
47 files changed, 6 insertions, 14901 deletions
diff --git a/configure.ac b/configure.ac
index 8259253d401..1e4d9ae5587 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1917,7 +1917,7 @@ if test "x$with_gallium_drivers" != x; then
1917 ;; 1917 ;;
1918 xnouveau) 1918 xnouveau)
1919 PKG_CHECK_MODULES([NOUVEAU], [libdrm_nouveau >= $LIBDRM_NOUVEAU_REQUIRED]) 1919 PKG_CHECK_MODULES([NOUVEAU], [libdrm_nouveau >= $LIBDRM_NOUVEAU_REQUIRED])
1920 GALLIUM_DRIVERS_DIRS="$GALLIUM_DRIVERS_DIRS nouveau nvfx nv50 nvc0" 1920 GALLIUM_DRIVERS_DIRS="$GALLIUM_DRIVERS_DIRS nouveau nv50 nvc0"
1921 gallium_check_st "nouveau/drm" "dri-nouveau" "xorg-nouveau" "" "xvmc-nouveau" "vdpau-nouveau" 1921 gallium_check_st "nouveau/drm" "dri-nouveau" "xorg-nouveau" "" "xvmc-nouveau" "vdpau-nouveau"
1922 ;; 1922 ;;
1923 xswrast) 1923 xswrast)
diff --git a/src/gallium/drivers/nouveau/nouveau_video.c b/src/gallium/drivers/nouveau/nouveau_video.c
index 06fbde46cc0..42bc102b1cf 100644
--- a/src/gallium/drivers/nouveau/nouveau_video.c
+++ b/src/gallium/drivers/nouveau/nouveau_video.c
@@ -27,8 +27,6 @@
27#include "nouveau_context.h" 27#include "nouveau_context.h"
28#include "nouveau_video.h" 28#include "nouveau_video.h"
29 29
30#include "nvfx/nvfx_context.h"
31#include "nvfx/nvfx_resource.h"
32#include "nouveau/nouveau_bo.h" 30#include "nouveau/nouveau_bo.h"
33#include "nouveau/nouveau_buffer.h" 31#include "nouveau/nouveau_buffer.h"
34#include "util/u_video.h" 32#include "util/u_video.h"
@@ -37,15 +35,6 @@
37#include "nouveau/nouveau_device.h" 35#include "nouveau/nouveau_device.h"
38#include "nouveau_winsys.h" 36#include "nouveau_winsys.h"
39 37
40static bool
41nouveau_video_is_nvfx(struct nouveau_decoder *dec) {
42 if (dec->screen->device->chipset < 0x50)
43 return true;
44 if (dec->screen->device->chipset >= 0x60 && dec->screen->device->chipset < 0x70)
45 return true;
46 return false;
47}
48
49static int 38static int
50nouveau_vpe_init(struct nouveau_decoder *dec) { 39nouveau_vpe_init(struct nouveau_decoder *dec) {
51 int ret; 40 int ret;
@@ -396,7 +385,8 @@ nouveau_decoder_surface_index(struct nouveau_decoder *dec,
396{ 385{
397 struct nouveau_video_buffer *buf = (struct nouveau_video_buffer *)buffer; 386 struct nouveau_video_buffer *buf = (struct nouveau_video_buffer *)buffer;
398 struct nouveau_channel *chan = dec->screen->channel; 387 struct nouveau_channel *chan = dec->screen->channel;
399 struct nouveau_bo *bo_y, *bo_c; 388 struct nouveau_bo *bo_y = ((struct nv04_resource *)buf->resources[0])->bo;
389 struct nouveau_bo *bo_c = ((struct nv04_resource *)buf->resources[1])->bo;
400 unsigned i; 390 unsigned i;
401 391
402 if (!buf) 392 if (!buf)
@@ -409,13 +399,6 @@ nouveau_decoder_surface_index(struct nouveau_decoder *dec,
409 dec->surfaces[i] = buf; 399 dec->surfaces[i] = buf;
410 dec->num_surfaces++; 400 dec->num_surfaces++;
411 401
412 if (nouveau_video_is_nvfx(dec)) {
413 bo_y = ((struct nvfx_resource *)buf->resources[0])->bo;
414 bo_c = ((struct nvfx_resource *)buf->resources[1])->bo;
415 } else {
416 bo_y = ((struct nv04_resource *)buf->resources[0])->bo;
417 bo_c = ((struct nv04_resource *)buf->resources[1])->bo;
418 }
419 MARK_RING(chan, 3, 2); 402 MARK_RING(chan, 3, 2);
420 BEGIN_RING(chan, dec->mpeg, NV31_MPEG_IMAGE_Y_OFFSET(i), 2); 403 BEGIN_RING(chan, dec->mpeg, NV31_MPEG_IMAGE_Y_OFFSET(i), 2);
421 OUT_RELOCl(chan, bo_y, 0, NOUVEAU_BO_RDWR); 404 OUT_RELOCl(chan, bo_y, 0, NOUVEAU_BO_RDWR);
@@ -857,35 +840,6 @@ nouveau_screen_init_vdec(struct nouveau_screen *screen)
857} 840}
858 841
859static struct pipe_video_decoder * 842static struct pipe_video_decoder *
860nvfx_context_create_decoder(struct pipe_context *context,
861 enum pipe_video_profile profile,
862 enum pipe_video_entrypoint entrypoint,
863 enum pipe_video_chroma_format chroma_format,
864 unsigned width, unsigned height,
865 unsigned max_references, bool expect_chunked_decode)
866{
867 struct nouveau_screen *screen = &nvfx_context(context)->screen->base;
868 return nouveau_create_decoder(context, screen, profile, entrypoint,
869 chroma_format, width, height,
870 max_references, expect_chunked_decode);
871}
872
873static struct pipe_video_buffer *
874nvfx_context_video_buffer_create(struct pipe_context *pipe,
875 const struct pipe_video_buffer *templat)
876{
877 struct nouveau_screen *screen = &nvfx_context(pipe)->screen->base;
878 return nouveau_video_buffer_create(pipe, screen, templat);
879}
880
881void
882nvfx_context_init_vdec(struct nvfx_context *nv)
883{
884 nv->pipe.create_video_decoder = nvfx_context_create_decoder;
885 nv->pipe.create_video_buffer = nvfx_context_video_buffer_create;
886}
887
888static struct pipe_video_decoder *
889nouveau_context_create_decoder(struct pipe_context *context, 843nouveau_context_create_decoder(struct pipe_context *context,
890 enum pipe_video_profile profile, 844 enum pipe_video_profile profile,
891 enum pipe_video_entrypoint entrypoint, 845 enum pipe_video_entrypoint entrypoint,
diff --git a/src/gallium/drivers/nouveau/nouveau_winsys.h b/src/gallium/drivers/nouveau/nouveau_winsys.h
index 3423451748a..5c634771aff 100644
--- a/src/gallium/drivers/nouveau/nouveau_winsys.h
+++ b/src/gallium/drivers/nouveau/nouveau_winsys.h
@@ -42,9 +42,6 @@ nouveau_screen_transfer_flags(unsigned pipe)
42} 42}
43 43
44extern struct pipe_screen * 44extern struct pipe_screen *
45nvfx_screen_create(struct nouveau_device *);
46
47extern struct pipe_screen *
48nv50_screen_create(struct nouveau_device *); 45nv50_screen_create(struct nouveau_device *);
49 46
50extern struct pipe_screen * 47extern struct pipe_screen *
diff --git a/src/gallium/drivers/nvfx/Android.mk b/src/gallium/drivers/nvfx/Android.mk
deleted file mode 100644
index 219b044d448..00000000000
--- a/src/gallium/drivers/nvfx/Android.mk
+++ /dev/null
@@ -1,37 +0,0 @@
1# Mesa 3-D graphics library
2#
3# Copyright (C) 2011 Chia-I Wu <olvaffe@gmail.com>
4# Copyright (C) 2011 LunarG Inc.
5#
6# Permission is hereby granted, free of charge, to any person obtaining a
7# copy of this software and associated documentation files (the "Software"),
8# to deal in the Software without restriction, including without limitation
9# the rights to use, copy, modify, merge, publish, distribute, sublicense,
10# and/or sell copies of the Software, and to permit persons to whom the
11# Software is furnished to do so, subject to the following conditions:
12#
13# The above copyright notice and this permission notice shall be included
14# in all copies or substantial portions of the Software.
15#
16# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22# DEALINGS IN THE SOFTWARE.
23
24LOCAL_PATH := $(call my-dir)
25
26# get C_SOURCES
27include $(LOCAL_PATH)/Makefile.sources
28
29include $(CLEAR_VARS)
30
31LOCAL_SRC_FILES := $(C_SOURCES)
32LOCAL_C_INCLUDES := $(DRM_TOP)
33
34LOCAL_MODULE := libmesa_pipe_nvfx
35
36include $(GALLIUM_COMMON_MK)
37include $(BUILD_STATIC_LIBRARY)
diff --git a/src/gallium/drivers/nvfx/Makefile b/src/gallium/drivers/nvfx/Makefile
deleted file mode 100644
index 9b6ed1cad6a..00000000000
--- a/src/gallium/drivers/nvfx/Makefile
+++ /dev/null
@@ -1,16 +0,0 @@
1TOP = ../../../..
2include $(TOP)/configs/current
3
4LIBNAME = nvfx
5
6# get C_SOURCES
7include Makefile.sources
8
9LIBRARY_INCLUDES = \
10 $(LIBDRM_CFLAGS) \
11 -I$(TOP)/src/gallium/drivers/nouveau/include
12
13include ../../Makefile.template
14
15# FIXME: Remove when this driver is converted to automake.
16all: default
diff --git a/src/gallium/drivers/nvfx/Makefile.sources b/src/gallium/drivers/nvfx/Makefile.sources
deleted file mode 100644
index 31611f76e08..00000000000
--- a/src/gallium/drivers/nvfx/Makefile.sources
+++ /dev/null
@@ -1,22 +0,0 @@
1C_SOURCES := \
2 nv04_2d.c \
3 nvfx_buffer.c \
4 nvfx_context.c \
5 nvfx_clear.c \
6 nvfx_draw.c \
7 nvfx_fragprog.c \
8 nvfx_fragtex.c \
9 nv30_fragtex.c \
10 nv40_fragtex.c \
11 nvfx_miptree.c \
12 nvfx_push.c \
13 nvfx_query.c \
14 nvfx_resource.c \
15 nvfx_screen.c \
16 nvfx_state.c \
17 nvfx_state_emit.c \
18 nvfx_state_fb.c \
19 nvfx_surface.c \
20 nvfx_transfer.c \
21 nvfx_vbo.c \
22 nvfx_vertprog.c
diff --git a/src/gallium/drivers/nvfx/SConscript b/src/gallium/drivers/nvfx/SConscript
deleted file mode 100644
index 2daf16d1e54..00000000000
--- a/src/gallium/drivers/nvfx/SConscript
+++ /dev/null
@@ -1,14 +0,0 @@
1Import('*')
2
3env = env.Clone()
4
5env.PrependUnique(delete_existing=1, CPPPATH = [
6 '#/src/gallium/drivers',
7])
8
9nvfx = env.ConvenienceLibrary(
10 target = 'nvfx',
11 source = env.ParseSourceList('Makefile.sources', 'C_SOURCES')
12 )
13
14Export('nvfx')
diff --git a/src/gallium/drivers/nvfx/nv01_2d.xml.h b/src/gallium/drivers/nvfx/nv01_2d.xml.h
deleted file mode 100644
index b963eb7edce..00000000000
--- a/src/gallium/drivers/nvfx/nv01_2d.xml.h
+++ /dev/null
@@ -1,1343 +0,0 @@
1#ifndef NV01_2D_XML
2#define NV01_2D_XML
3
4/* Autogenerated file, DO NOT EDIT manually!
5
6This file was generated by the rules-ng-ng headergen tool in this git repository:
7http://0x04.net/cgit/index.cgi/rules-ng-ng
8git clone git://0x04.net/rules-ng-ng
9
10The rules-ng-ng source files this header was generated from are:
11- nv01_2d.xml ( 33462 bytes, from 2010-08-05 19:38:53)
12- copyright.xml ( 6503 bytes, from 2010-04-10 23:15:50)
13- nv_defs.xml ( 4437 bytes, from 2010-08-05 19:38:53)
14- nv_object.xml ( 10424 bytes, from 2010-08-05 19:38:53)
15- nvchipsets.xml ( 2824 bytes, from 2010-08-05 19:38:53)
16
17Copyright (C) 2006-2010 by the following authors:
18- Artur Huillet <arthur.huillet@free.fr> (ahuillet)
19- Ben Skeggs (darktama, darktama_)
20- B. R. <koala_br@users.sourceforge.net> (koala_br)
21- Carlos Martin <carlosmn@users.sf.net> (carlosmn)
22- Christoph Bumiller <e0425955@student.tuwien.ac.at> (calim, chrisbmr)
23- Dawid Gajownik <gajownik@users.sf.net> (gajownik)
24- Dmitry Baryshkov
25- Dmitry Eremin-Solenikov <lumag@users.sf.net> (lumag)
26- EdB <edb_@users.sf.net> (edb_)
27- Erik Waling <erikwailing@users.sf.net> (erikwaling)
28- Francisco Jerez <currojerez@riseup.net> (curro, curro_, currojerez)
29- imirkin <imirkin@users.sf.net> (imirkin)
30- jb17bsome <jb17bsome@bellsouth.net> (jb17bsome)
31- Jeremy Kolb <kjeremy@users.sf.net> (kjeremy)
32- Laurent Carlier <lordheavym@gmail.com> (lordheavy)
33- Luca Barbieri <luca@luca-barbieri.com> (lb, lb1)
34- Maarten Maathuis <madman2003@gmail.com> (stillunknown)
35- Marcin Kościelnicki <koriakin@0x04.net> (mwk, koriakin)
36- Mark Carey <mark.carey@gmail.com> (careym)
37- Matthieu Castet <matthieu.castet@parrot.com> (mat-c)
38- nvidiaman <nvidiaman@users.sf.net> (nvidiaman)
39- Patrice Mandin <mandin.patrice@orange.fr> (pmandin, pmdata)
40- Pekka Paalanen <pq@iki.fi> (pq, ppaalanen)
41- Peter Popov <ironpeter@users.sf.net> (ironpeter)
42- Richard Hughes <hughsient@users.sf.net> (hughsient)
43- Rudi Cilibrasi <cilibrar@users.sf.net> (cilibrar)
44- Serge Martin
45- Simon Raffeiner
46- Stephane Loeuillet <leroutier@users.sf.net> (leroutier)
47- Stephane Marchesin <stephane.marchesin@gmail.com> (marcheu)
48- sturmflut <sturmflut@users.sf.net> (sturmflut)
49- Sylvain Munaut <tnt@246tNt.com>
50- Victor Stinner <victor.stinner@haypocalc.com> (haypo)
51- Wladmir van der Laan <laanwj@gmail.com> (miathan6)
52- Younes Manton <younes.m@gmail.com> (ymanton)
53
54Permission is hereby granted, free of charge, to any person obtaining
55a copy of this software and associated documentation files (the
56"Software"), to deal in the Software without restriction, including
57without limitation the rights to use, copy, modify, merge, publish,
58distribute, sublicense, and/or sell copies of the Software, and to
59permit persons to whom the Software is furnished to do so, subject to
60the following conditions:
61
62The above copyright notice and this permission notice (including the
63next paragraph) shall be included in all copies or substantial
64portions of the Software.
65
66THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
67EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
68MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
69IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
70LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
71OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
72WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
73*/
74
75
76
77#define NV01_CONTEXT_BETA1_DMA_NOTIFY 0x00000180
78
79#define NV01_CONTEXT_BETA1_BETA_1D31 0x00000300
80
81
82#define NV04_BETA_SOLID_DMA_NOTIFY 0x00000180
83
84#define NV04_BETA_SOLID_BETA_FACTOR 0x00000300
85
86
87#define NV01_CONTEXT_COLOR_KEY_DMA_NOTIFY 0x00000180
88
89#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT 0x00000300
90#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_A16R5G6B5 0x00000001
91#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_X16A1R5G5B5 0x00000002
92#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_A8R8G8B8 0x00000003
93
94#define NV01_CONTEXT_COLOR_KEY_COLOR 0x00000304
95
96
97#define NV01_CONTEXT_PATTERN_DMA_NOTIFY 0x00000180
98
99#define NV01_CONTEXT_PATTERN_COLOR_FORMAT 0x00000300
100
101#define NV01_CONTEXT_PATTERN_MONOCHROME_FORMAT 0x00000304
102
103#define NV01_CONTEXT_PATTERN_SHAPE 0x00000308
104
105#define NV01_CONTEXT_PATTERN_COLOR(i0) (0x00000310 + 0x4*(i0))
106#define NV01_CONTEXT_PATTERN_COLOR__ESIZE 0x00000004
107#define NV01_CONTEXT_PATTERN_COLOR__LEN 0x00000002
108
109#define NV01_CONTEXT_PATTERN_PATTERN(i0) (0x00000318 + 0x4*(i0))
110#define NV01_CONTEXT_PATTERN_PATTERN__ESIZE 0x00000004
111#define NV01_CONTEXT_PATTERN_PATTERN__LEN 0x00000002
112
113
114#define NV01_CONTEXT_CLIP_RECTANGLE_DMA_NOTIFY 0x00000180
115
116#define NV01_CONTEXT_CLIP_RECTANGLE_POINT 0x00000300
117#define NV01_CONTEXT_CLIP_RECTANGLE_POINT_X__MASK 0x0000ffff
118#define NV01_CONTEXT_CLIP_RECTANGLE_POINT_X__SHIFT 0
119#define NV01_CONTEXT_CLIP_RECTANGLE_POINT_Y__MASK 0xffff0000
120#define NV01_CONTEXT_CLIP_RECTANGLE_POINT_Y__SHIFT 16
121
122#define NV01_CONTEXT_CLIP_RECTANGLE_SIZE 0x00000304
123#define NV01_CONTEXT_CLIP_RECTANGLE_SIZE_W__MASK 0x0000ffff
124#define NV01_CONTEXT_CLIP_RECTANGLE_SIZE_W__SHIFT 0
125#define NV01_CONTEXT_CLIP_RECTANGLE_SIZE_H__MASK 0xffff0000
126#define NV01_CONTEXT_CLIP_RECTANGLE_SIZE_H__SHIFT 16
127
128
129#define NV04_CONTEXT_SURFACES_2D_DMA_NOTIFY 0x00000180
130
131#define NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE 0x00000184
132
133#define NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_DESTIN 0x00000188
134
135
136#define NV50_CONTEXT_SURFACES_2D_SRC_LINEAR 0x00000200
137
138#define NV50_CONTEXT_SURFACES_2D_SRC_TILE_MODE 0x00000204
139
140#define NV50_CONTEXT_SURFACES_2D_SRC_WIDTH 0x00000208
141
142#define NV50_CONTEXT_SURFACES_2D_SRC_HEIGHT 0x0000020c
143
144#define NV50_CONTEXT_SURFACES_2D_UNK0210 0x00000210
145
146#define NV50_CONTEXT_SURFACES_2D_UNK0214 0x00000214
147
148#define NV50_CONTEXT_SURFACES_2D_DST_LINEAR 0x00000218
149
150#define NV50_CONTEXT_SURFACES_2D_DST_TILE_MODE 0x0000021c
151
152#define NV50_CONTEXT_SURFACES_2D_DST_WIDTH 0x00000220
153
154#define NV50_CONTEXT_SURFACES_2D_DST_HEIGHT 0x00000224
155
156#define NV50_CONTEXT_SURFACES_2D_UNK0228 0x00000228
157
158#define NV50_CONTEXT_SURFACES_2D_UNK022C 0x0000022c
159
160#define NV50_CONTEXT_SURFACES_2D_OFFSET_SOURCE_HIGH 0x00000230
161
162#define NV50_CONTEXT_SURFACES_2D_OFFSET_DESTIN_HIGH 0x00000234
163
164#define NV04_CONTEXT_SURFACES_2D_FORMAT 0x00000300
165#define NV04_CONTEXT_SURFACES_2D_FORMAT_Y8 0x00000001
166#define NV04_CONTEXT_SURFACES_2D_FORMAT_X1R5G5B5_Z1R5G5B5 0x00000002
167#define NV04_CONTEXT_SURFACES_2D_FORMAT_X1R5G5B5_X1R5G5B5 0x00000003
168#define NV04_CONTEXT_SURFACES_2D_FORMAT_R5G6B5 0x00000004
169#define NV04_CONTEXT_SURFACES_2D_FORMAT_Y16 0x00000005
170#define NV04_CONTEXT_SURFACES_2D_FORMAT_X8R8G8B8_Z8R8G8B8 0x00000006
171#define NV04_CONTEXT_SURFACES_2D_FORMAT_X8R8G8B8_X8R8G8B8 0x00000007
172#define NV04_CONTEXT_SURFACES_2D_FORMAT_X1A7R8G8B8_Z1A7R8G8B8 0x00000008
173#define NV04_CONTEXT_SURFACES_2D_FORMAT_X1A7R8G8B8_X1A7R8G8B8 0x00000009
174#define NV04_CONTEXT_SURFACES_2D_FORMAT_A8R8G8B8 0x0000000a
175#define NV04_CONTEXT_SURFACES_2D_FORMAT_Y32 0x0000000b
176
177#define NV04_CONTEXT_SURFACES_2D_PITCH 0x00000304
178#define NV04_CONTEXT_SURFACES_2D_PITCH_SOURCE__MASK 0x0000ffff
179#define NV04_CONTEXT_SURFACES_2D_PITCH_SOURCE__SHIFT 0
180#define NV04_CONTEXT_SURFACES_2D_PITCH_DESTIN__MASK 0xffff0000
181#define NV04_CONTEXT_SURFACES_2D_PITCH_DESTIN__SHIFT 16
182
183#define NV04_CONTEXT_SURFACES_2D_OFFSET_SOURCE 0x00000308
184
185#define NV04_CONTEXT_SURFACES_2D_OFFSET_DESTIN 0x0000030c
186
187
188#define NV04_SWIZZLED_SURFACE_DMA_NOTIFY 0x00000180
189
190#define NV04_SWIZZLED_SURFACE_DMA_IMAGE 0x00000184
191
192#define NV04_SWIZZLED_SURFACE_FORMAT 0x00000300
193#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR__MASK 0x000000ff
194#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR__SHIFT 0
195#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_Y8 0x00000001
196#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X1R5G5B5_Z1R5G5B5 0x00000002
197#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X1R5G5B5_X1R5G5B5 0x00000003
198#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_R5G6B5 0x00000004
199#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_Y16 0x00000005
200#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X8R8G8B8_Z8R8G8B8 0x00000006
201#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X8R8G8B8_X8R8G8B8 0x00000007
202#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X1A7R8G8B8_Z1A7R8G8B8 0x00000008
203#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X1A7R8G8B8_X1A7R8G8B8 0x00000009
204#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_A8R8G8B8 0x0000000a
205#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_Y32 0x0000000b
206#define NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U__MASK 0x00ff0000
207#define NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U__SHIFT 16
208#define NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V__MASK 0xff000000
209#define NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V__SHIFT 24
210
211#define NV04_SWIZZLED_SURFACE_OFFSET 0x00000304
212
213
214#define NV03_CONTEXT_ROP_DMA_NOTIFY 0x00000180
215
216#define NV03_CONTEXT_ROP_ROP 0x00000300
217
218
219#define NV04_IMAGE_PATTERN_DMA_NOTIFY 0x00000180
220
221#define NV04_IMAGE_PATTERN_COLOR_FORMAT 0x00000300
222#define NV04_IMAGE_PATTERN_COLOR_FORMAT_A16R5G6B5 0x00000001
223#define NV04_IMAGE_PATTERN_COLOR_FORMAT_X16A1R5G5B5 0x00000002
224#define NV04_IMAGE_PATTERN_COLOR_FORMAT_A8R8G8B8 0x00000003
225
226#define NV04_IMAGE_PATTERN_MONOCHROME_FORMAT 0x00000304
227#define NV04_IMAGE_PATTERN_MONOCHROME_FORMAT_CGA6 0x00000001
228#define NV04_IMAGE_PATTERN_MONOCHROME_FORMAT_LE 0x00000002
229
230#define NV04_IMAGE_PATTERN_MONOCHROME_SHAPE 0x00000308
231#define NV04_IMAGE_PATTERN_MONOCHROME_SHAPE_8X8 0x00000000
232#define NV04_IMAGE_PATTERN_MONOCHROME_SHAPE_64X1 0x00000001
233#define NV04_IMAGE_PATTERN_MONOCHROME_SHAPE_1X64 0x00000002
234
235#define NV04_IMAGE_PATTERN_PATTERN_SELECT 0x0000030c
236#define NV04_IMAGE_PATTERN_PATTERN_SELECT_MONO 0x00000001
237#define NV04_IMAGE_PATTERN_PATTERN_SELECT_COLOR 0x00000002
238
239#define NV04_IMAGE_PATTERN_MONOCHROME_COLOR0 0x00000310
240
241#define NV04_IMAGE_PATTERN_MONOCHROME_COLOR1 0x00000314
242
243#define NV04_IMAGE_PATTERN_MONOCHROME_PATTERN0 0x00000318
244
245#define NV04_IMAGE_PATTERN_MONOCHROME_PATTERN1 0x0000031c
246
247#define NV04_IMAGE_PATTERN_PATTERN_Y8(i0) (0x00000400 + 0x4*(i0))
248#define NV04_IMAGE_PATTERN_PATTERN_Y8__ESIZE 0x00000004
249#define NV04_IMAGE_PATTERN_PATTERN_Y8__LEN 0x00000010
250#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y0__MASK 0x000000ff
251#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y0__SHIFT 0
252#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y1__MASK 0x0000ff00
253#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y1__SHIFT 8
254#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y2__MASK 0x00ff0000
255#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y2__SHIFT 16
256#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y3__MASK 0xff000000
257#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y3__SHIFT 24
258
259#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5(i0) (0x00000500 + 0x4*(i0))
260#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5__ESIZE 0x00000004
261#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5__LEN 0x00000020
262#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_B0__MASK 0x0000001f
263#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_B0__SHIFT 0
264#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_G0__MASK 0x000007e0
265#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_G0__SHIFT 5
266#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_R0__MASK 0x0000f800
267#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_R0__SHIFT 11
268#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_B1__MASK 0x001f0000
269#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_B1__SHIFT 16
270#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_G1__MASK 0x07e00000
271#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_G1__SHIFT 21
272#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_R1__MASK 0xf8000000
273#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_R1__SHIFT 27
274
275#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5(i0) (0x00000600 + 0x4*(i0))
276#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5__ESIZE 0x00000004
277#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5__LEN 0x00000020
278#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_B0__MASK 0x0000001f
279#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_B0__SHIFT 0
280#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_G0__MASK 0x000003e0
281#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_G0__SHIFT 5
282#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_R0__MASK 0x00007c00
283#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_R0__SHIFT 10
284#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_B1__MASK 0x001f0000
285#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_B1__SHIFT 16
286#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_G1__MASK 0x03e00000
287#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_G1__SHIFT 21
288#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_R1__MASK 0x7c000000
289#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_R1__SHIFT 26
290
291#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8(i0) (0x00000700 + 0x4*(i0))
292#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8__ESIZE 0x00000004
293#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8__LEN 0x00000040
294#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_B__MASK 0x000000ff
295#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_B__SHIFT 0
296#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_G__MASK 0x0000ff00
297#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_G__SHIFT 8
298#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_R__MASK 0x00ff0000
299#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_R__SHIFT 16
300
301
302#define NV01_RENDER_SOLID_LINE_PATCH 0x0000010c
303
304#define NV01_RENDER_SOLID_LINE_DMA_NOTIFY 0x00000180
305
306#define NV01_RENDER_SOLID_LINE_CLIP_RECTANGLE 0x00000184
307
308#define NV01_RENDER_SOLID_LINE_PATTERN 0x00000188
309
310#define NV04_RENDER_SOLID_LINE_PATTERN 0x00000188
311
312#define NV01_RENDER_SOLID_LINE_ROP 0x0000018c
313
314#define NV01_RENDER_SOLID_LINE_BETA1 0x00000190
315
316#define NV01_RENDER_SOLID_LINE_SURFACE_DST 0x00000194
317
318
319#define NV04_RENDER_SOLID_LINE_BETA4 0x00000194
320
321#define NV04_RENDER_SOLID_LINE_SURFACE 0x00000198
322
323#define NV01_RENDER_SOLID_LINE_OPERATION 0x000002fc
324#define NV01_RENDER_SOLID_LINE_OPERATION_SRCCOPY_AND 0x00000000
325#define NV01_RENDER_SOLID_LINE_OPERATION_ROP_AND 0x00000001
326#define NV01_RENDER_SOLID_LINE_OPERATION_BLEND_AND 0x00000002
327#define NV01_RENDER_SOLID_LINE_OPERATION_SRCCOPY 0x00000003
328#define NV01_RENDER_SOLID_LINE_OPERATION_SRCCOPY_PREMULT 0x00000004
329#define NV01_RENDER_SOLID_LINE_OPERATION_BLEND_PREMULT 0x00000005
330
331#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT 0x00000300
332#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT_A16R5G6B5 0x00000001
333#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT_X16A1R5G5B5 0x00000002
334#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT_A8R8G8B8 0x00000003
335
336#define NV01_RENDER_SOLID_LINE_COLOR 0x00000304
337
338#define NV01_RENDER_SOLID_LINE_LINE_POINT0(i0) (0x00000400 + 0x8*(i0))
339#define NV01_RENDER_SOLID_LINE_LINE_POINT0__ESIZE 0x00000008
340#define NV01_RENDER_SOLID_LINE_LINE_POINT0__LEN 0x00000010
341#define NV01_RENDER_SOLID_LINE_LINE_POINT0_X__MASK 0x0000ffff
342#define NV01_RENDER_SOLID_LINE_LINE_POINT0_X__SHIFT 0
343#define NV01_RENDER_SOLID_LINE_LINE_POINT0_Y__MASK 0xffff0000
344#define NV01_RENDER_SOLID_LINE_LINE_POINT0_Y__SHIFT 16
345
346#define NV01_RENDER_SOLID_LINE_LINE_POINT1(i0) (0x00000404 + 0x8*(i0))
347#define NV01_RENDER_SOLID_LINE_LINE_POINT1__ESIZE 0x00000008
348#define NV01_RENDER_SOLID_LINE_LINE_POINT1__LEN 0x00000010
349#define NV01_RENDER_SOLID_LINE_LINE_POINT1_X__MASK 0x0000ffff
350#define NV01_RENDER_SOLID_LINE_LINE_POINT1_X__SHIFT 0
351#define NV01_RENDER_SOLID_LINE_LINE_POINT1_Y__MASK 0xffff0000
352#define NV01_RENDER_SOLID_LINE_LINE_POINT1_Y__SHIFT 16
353
354#define NV01_RENDER_SOLID_LINE_LINE32_POINT0_X(i0) (0x00000480 + 0x10*(i0))
355#define NV01_RENDER_SOLID_LINE_LINE32_POINT0_X__ESIZE 0x00000010
356#define NV01_RENDER_SOLID_LINE_LINE32_POINT0_X__LEN 0x00000010
357
358#define NV01_RENDER_SOLID_LINE_LINE32_POINT0_Y(i0) (0x00000484 + 0x10*(i0))
359#define NV01_RENDER_SOLID_LINE_LINE32_POINT0_Y__ESIZE 0x00000010
360#define NV01_RENDER_SOLID_LINE_LINE32_POINT0_Y__LEN 0x00000010
361
362#define NV01_RENDER_SOLID_LINE_LINE32_POINT1_X(i0) (0x00000488 + 0x10*(i0))
363#define NV01_RENDER_SOLID_LINE_LINE32_POINT1_X__ESIZE 0x00000010
364#define NV01_RENDER_SOLID_LINE_LINE32_POINT1_X__LEN 0x00000010
365
366#define NV01_RENDER_SOLID_LINE_LINE32_POINT1_Y(i0) (0x0000048c + 0x10*(i0))
367#define NV01_RENDER_SOLID_LINE_LINE32_POINT1_Y__ESIZE 0x00000010
368#define NV01_RENDER_SOLID_LINE_LINE32_POINT1_Y__LEN 0x00000010
369
370#define NV01_RENDER_SOLID_LINE_POLYLINE(i0) (0x00000500 + 0x4*(i0))
371#define NV01_RENDER_SOLID_LINE_POLYLINE__ESIZE 0x00000004
372#define NV01_RENDER_SOLID_LINE_POLYLINE__LEN 0x00000020
373#define NV01_RENDER_SOLID_LINE_POLYLINE_X__MASK 0x0000ffff
374#define NV01_RENDER_SOLID_LINE_POLYLINE_X__SHIFT 0
375#define NV01_RENDER_SOLID_LINE_POLYLINE_Y__MASK 0xffff0000
376#define NV01_RENDER_SOLID_LINE_POLYLINE_Y__SHIFT 16
377
378#define NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_X(i0) (0x00000580 + 0x8*(i0))
379#define NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_X__ESIZE 0x00000008
380#define NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_X__LEN 0x00000010
381
382#define NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_Y(i0) (0x00000584 + 0x8*(i0))
383#define NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_Y__ESIZE 0x00000008
384#define NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_Y__LEN 0x00000010
385
386#define NV01_RENDER_SOLID_LINE_CPOLYLINE_COLOR(i0) (0x00000600 + 0x8*(i0))
387#define NV01_RENDER_SOLID_LINE_CPOLYLINE_COLOR__ESIZE 0x00000008
388#define NV01_RENDER_SOLID_LINE_CPOLYLINE_COLOR__LEN 0x00000010
389
390#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT(i0) (0x00000604 + 0x8*(i0))
391#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT__ESIZE 0x00000008
392#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT__LEN 0x00000010
393#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT_X__MASK 0x0000ffff
394#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT_X__SHIFT 0
395#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT_Y__MASK 0xffff0000
396#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT_Y__SHIFT 16
397
398
399#define NV01_RENDER_SOLID_TRIANGLE_PATCH 0x0000010c
400
401#define NV01_RENDER_SOLID_TRIANGLE_DMA_NOTIFY 0x00000180
402
403#define NV01_RENDER_SOLID_TRIANGLE_CLIP_RECTANGLE 0x00000184
404
405#define NV01_RENDER_SOLID_TRIANGLE_PATTERN 0x00000188
406
407#define NV04_RENDER_SOLID_TRIANGLE_PATTERN 0x00000188
408
409#define NV01_RENDER_SOLID_TRIANGLE_ROP 0x0000018c
410
411#define NV01_RENDER_SOLID_TRIANGLE_BETA1 0x00000190
412
413#define NV01_RENDER_SOLID_TRIANGLE_SURFACE_DST 0x00000194
414
415
416#define NV04_RENDER_SOLID_TRIANGLE_BETA4 0x00000194
417
418#define NV04_RENDER_SOLID_TRIANGLE_SURFACE 0x00000198
419
420#define NV01_RENDER_SOLID_TRIANGLE_OPERATION 0x000002fc
421#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_SRCCOPY_AND 0x00000000
422#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_ROP_AND 0x00000001
423#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_BLEND_AND 0x00000002
424#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_SRCCOPY 0x00000003
425#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_SRCCOPY_PREMULT 0x00000004
426#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_BLEND_PREMULT 0x00000005
427
428#define NV01_RENDER_SOLID_TRIANGLE_COLOR_FORMAT 0x00000300
429#define NV01_RENDER_SOLID_TRIANGLE_COLOR_FORMAT_A16R5G6B5 0x00000001
430#define NV01_RENDER_SOLID_TRIANGLE_COLOR_FORMAT_X16A1R5G5B5 0x00000002
431#define NV01_RENDER_SOLID_TRIANGLE_COLOR_FORMAT_A8R8G8B8 0x00000003
432
433#define NV01_RENDER_SOLID_TRIANGLE_COLOR 0x00000304
434
435#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0 0x00000310
436#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0_X__MASK 0x0000ffff
437#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0_X__SHIFT 0
438#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0_Y__MASK 0xffff0000
439#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0_Y__SHIFT 16
440
441#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1 0x00000314
442#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1_X__MASK 0x0000ffff
443#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1_X__SHIFT 0
444#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1_Y__MASK 0xffff0000
445#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1_Y__SHIFT 16
446
447#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2 0x00000318
448#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2_X__MASK 0x0000ffff
449#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2_X__SHIFT 0
450#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2_Y__MASK 0xffff0000
451#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2_Y__SHIFT 16
452
453#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT0_X 0x00000320
454
455#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT0_Y 0x00000324
456
457#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT1_X 0x00000328
458
459#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT1_Y 0x0000032c
460
461#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT2_X 0x00000330
462
463#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT2_Y 0x00000334
464
465#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH(i0) (0x00000400 + 0x4*(i0))
466#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH__ESIZE 0x00000004
467#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH__LEN 0x00000020
468#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH_X__MASK 0x0000ffff
469#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH_X__SHIFT 0
470#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH_Y__MASK 0xffff0000
471#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH_Y__SHIFT 16
472
473#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_X(i0) (0x00000480 + 0x8*(i0))
474#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_X__ESIZE 0x00000008
475#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_X__LEN 0x00000010
476
477#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_Y(i0) (0x00000484 + 0x8*(i0))
478#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_Y__ESIZE 0x00000008
479#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_Y__LEN 0x00000010
480
481#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_COLOR(i0) (0x00000500 + 0x10*(i0))
482#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_COLOR__ESIZE 0x00000010
483#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_COLOR__LEN 0x00000008
484
485#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0(i0) (0x00000504 + 0x10*(i0))
486#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0__ESIZE 0x00000010
487#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0__LEN 0x00000008
488#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0_X__MASK 0x0000ffff
489#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0_X__SHIFT 0
490#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0_Y__MASK 0xffff0000
491#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0_Y__SHIFT 16
492
493#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1(i0) (0x00000508 + 0x10*(i0))
494#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1__ESIZE 0x00000010
495#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1__LEN 0x00000008
496#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1_X__MASK 0x0000ffff
497#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1_X__SHIFT 0
498#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1_Y__MASK 0xffff0000
499#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1_Y__SHIFT 16
500
501#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2(i0) (0x0000050c + 0x10*(i0))
502#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2__ESIZE 0x00000010
503#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2__LEN 0x00000008
504#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2_X__MASK 0x0000ffff
505#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2_X__SHIFT 0
506#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2_Y__MASK 0xffff0000
507#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2_Y__SHIFT 16
508
509#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_COLOR(i0) (0x00000580 + 0x8*(i0))
510#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_COLOR__ESIZE 0x00000008
511#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_COLOR__LEN 0x00000010
512
513#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT(i0) (0x00000584 + 0x8*(i0))
514#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT__ESIZE 0x00000008
515#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT__LEN 0x00000010
516#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT_X__MASK 0x0000ffff
517#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT_X__SHIFT 0
518#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT_Y__MASK 0xffff0000
519#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT_Y__SHIFT 16
520
521
522#define NV01_RENDER_SOLID_RECTANGLE_PATCH 0x0000010c
523
524#define NV01_RENDER_SOLID_RECTANGLE_DMA_NOTIFY 0x00000180
525
526#define NV01_RENDER_SOLID_RECTANGLE_CLIP_RECTANGLE 0x00000184
527
528#define NV01_RENDER_SOLID_RECTANGLE_PATTERN 0x00000188
529
530#define NV04_RENDER_SOLID_RECTANGLE_PATTERN 0x00000188
531
532#define NV01_RENDER_SOLID_RECTANGLE_ROP 0x0000018c
533
534#define NV01_RENDER_SOLID_RECTANGLE_BETA1 0x00000190
535
536#define NV01_RENDER_SOLID_RECTANGLE_SURFACE_DST 0x00000194
537
538
539#define NV04_RENDER_SOLID_RECTANGLE_BETA4 0x00000194
540
541#define NV04_RENDER_SOLID_RECTANGLE_SURFACE 0x00000198
542
543#define NV01_RENDER_SOLID_RECTANGLE_OPERATION 0x000002fc
544#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_SRCCOPY_AND 0x00000000
545#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_ROP_AND 0x00000001
546#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_BLEND_AND 0x00000002
547#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_SRCCOPY 0x00000003
548#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_SRCCOPY_PREMULT 0x00000004
549#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_BLEND_PREMULT 0x00000005
550
551#define NV01_RENDER_SOLID_RECTANGLE_COLOR_FORMAT 0x00000300
552#define NV01_RENDER_SOLID_RECTANGLE_COLOR_FORMAT_A16R5G6B5 0x00000001
553#define NV01_RENDER_SOLID_RECTANGLE_COLOR_FORMAT_X16A1R5G5B5 0x00000002
554#define NV01_RENDER_SOLID_RECTANGLE_COLOR_FORMAT_A8R8G8B8 0x00000003
555
556#define NV01_RENDER_SOLID_RECTANGLE_COLOR 0x00000304
557
558#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT(i0) (0x00000400 + 0x8*(i0))
559#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT__ESIZE 0x00000008
560#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT__LEN 0x00000010
561#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT_X__MASK 0x0000ffff
562#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT_X__SHIFT 0
563#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT_Y__MASK 0xffff0000
564#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT_Y__SHIFT 16
565
566#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE(i0) (0x00000404 + 0x8*(i0))
567#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE__ESIZE 0x00000008
568#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE__LEN 0x00000010
569#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE_W__MASK 0x0000ffff
570#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE_W__SHIFT 0
571#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE_H__MASK 0xffff0000
572#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE_H__SHIFT 16
573
574
575#define NV01_IMAGE_BLIT_PATCH 0x0000010c
576
577
578#define NV11_IMAGE_BLIT_WAIT_FOR_IDLE 0x00000108
579
580#define NV11_IMAGE_BLIT_UNK120 0x00000120
581
582#define NV11_IMAGE_BLIT_UNK124 0x00000124
583
584#define NV11_IMAGE_BLIT_UNK128 0x00000128
585
586#define NV11_IMAGE_BLIT_UNK12C 0x0000012c
587
588#define NV11_IMAGE_BLIT_UNK130 0x00000130
589
590#define NV11_IMAGE_BLIT_UNK134 0x00000134
591
592#define NV01_IMAGE_BLIT_DMA_NOTIFY 0x00000180
593
594#define NV01_IMAGE_BLIT_COLOR_KEY 0x00000184
595
596#define NV04_IMAGE_BLIT_COLOR_KEY 0x00000184
597
598#define NV01_IMAGE_BLIT_CLIP_RECTANGLE 0x00000188
599
600#define NV01_IMAGE_BLIT_PATTERN 0x0000018c
601
602#define NV04_IMAGE_BLIT_PATTERN 0x0000018c
603
604#define NV01_IMAGE_BLIT_ROP 0x00000190
605
606#define NV01_IMAGE_BLIT_BETA1 0x00000194
607
608
609#define NV01_IMAGE_BLIT_SURFACE_SRC 0x00000198
610
611#define NV01_IMAGE_BLIT_SURFACE_DST 0x0000019c
612
613
614#define NV04_IMAGE_BLIT_BETA4 0x00000198
615
616#define NV04_IMAGE_BLIT_SURFACES 0x0000019c
617
618#define NV01_IMAGE_BLIT_OPERATION 0x000002fc
619#define NV01_IMAGE_BLIT_OPERATION_SRCCOPY_AND 0x00000000
620#define NV01_IMAGE_BLIT_OPERATION_ROP_AND 0x00000001
621#define NV01_IMAGE_BLIT_OPERATION_BLEND_AND 0x00000002
622#define NV01_IMAGE_BLIT_OPERATION_SRCCOPY 0x00000003
623#define NV01_IMAGE_BLIT_OPERATION_SRCCOPY_PREMULT 0x00000004
624#define NV01_IMAGE_BLIT_OPERATION_BLEND_PREMULT 0x00000005
625
626#define NV01_IMAGE_BLIT_POINT_IN 0x00000300
627#define NV01_IMAGE_BLIT_POINT_IN_X__MASK 0x0000ffff
628#define NV01_IMAGE_BLIT_POINT_IN_X__SHIFT 0
629#define NV01_IMAGE_BLIT_POINT_IN_Y__MASK 0xffff0000
630#define NV01_IMAGE_BLIT_POINT_IN_Y__SHIFT 16
631
632#define NV01_IMAGE_BLIT_POINT_OUT 0x00000304
633#define NV01_IMAGE_BLIT_POINT_OUT_X__MASK 0x0000ffff
634#define NV01_IMAGE_BLIT_POINT_OUT_X__SHIFT 0
635#define NV01_IMAGE_BLIT_POINT_OUT_Y__MASK 0xffff0000
636#define NV01_IMAGE_BLIT_POINT_OUT_Y__SHIFT 16
637
638#define NV01_IMAGE_BLIT_SIZE 0x00000308
639#define NV01_IMAGE_BLIT_SIZE_W__MASK 0x0000ffff
640#define NV01_IMAGE_BLIT_SIZE_W__SHIFT 0
641#define NV01_IMAGE_BLIT_SIZE_H__MASK 0xffff0000
642#define NV01_IMAGE_BLIT_SIZE_H__SHIFT 16
643
644
645#define NV04_INDEXED_IMAGE_FROM_CPU_PATCH 0x0000010c
646
647#define NV04_INDEXED_IMAGE_FROM_CPU_DMA_NOTIFY 0x00000180
648
649#define NV04_INDEXED_IMAGE_FROM_CPU_DMA_LUT 0x00000184
650
651#define NV04_INDEXED_IMAGE_FROM_CPU_COLOR_KEY 0x00000188
652
653#define NV04_INDEXED_IMAGE_FROM_CPU_CLIP_RECTANGLE 0x0000018c
654
655#define NV04_INDEXED_IMAGE_FROM_CPU_PATTERN 0x00000190
656
657#define NV04_INDEXED_IMAGE_FROM_CPU_ROP 0x00000194
658
659#define NV04_INDEXED_IMAGE_FROM_CPU_BETA1 0x00000198
660
661#define NV04_INDEXED_IMAGE_FROM_CPU_BETA4 0x0000019c
662
663#define NV04_INDEXED_IMAGE_FROM_CPU_SURFACE 0x000001a0
664
665#define NV05_INDEXED_IMAGE_FROM_CPU_SURFACE 0x000001a0
666
667#define NV05_INDEXED_IMAGE_FROM_CPU_COLOR_CONVERSION 0x000003e0
668
669#define NV04_INDEXED_IMAGE_FROM_CPU_OPERATION 0x000003e4
670
671#define NV04_INDEXED_IMAGE_FROM_CPU_COLOR_FORMAT 0x000003e8
672
673#define NV04_INDEXED_IMAGE_FROM_CPU_INDEX_FORMAT 0x000003ec
674
675#define NV04_INDEXED_IMAGE_FROM_CPU_LUT_OFFSET 0x000003f0
676
677#define NV04_INDEXED_IMAGE_FROM_CPU_POINT 0x000003f4
678
679#define NV04_INDEXED_IMAGE_FROM_CPU_SIZE_OUT 0x000003f8
680
681#define NV04_INDEXED_IMAGE_FROM_CPU_SIZE_IN 0x000003fc
682
683#define NV04_INDEXED_IMAGE_FROM_CPU_COLOR(i0) (0x00000400 + 0x4*(i0))
684#define NV04_INDEXED_IMAGE_FROM_CPU_COLOR__ESIZE 0x00000004
685#define NV04_INDEXED_IMAGE_FROM_CPU_COLOR__LEN 0x00000700
686
687
688#define NV10_IMAGE_FROM_CPU_WAIT_FOR_IDLE 0x00000108
689
690#define NV01_IMAGE_FROM_CPU_PATCH 0x0000010c
691
692#define NV01_IMAGE_FROM_CPU_DMA_NOTIFY 0x00000180
693
694#define NV01_IMAGE_FROM_CPU_COLOR_KEY 0x00000184
695
696#define NV04_IMAGE_FROM_CPU_COLOR_KEY 0x00000184
697
698#define NV01_IMAGE_FROM_CPU_CLIP_RECTANGLE 0x00000188
699
700#define NV01_IMAGE_FROM_CPU_PATTERN 0x0000018c
701
702#define NV04_IMAGE_FROM_CPU_PATTERN 0x0000018c
703
704#define NV01_IMAGE_FROM_CPU_ROP 0x00000190
705
706#define NV01_IMAGE_FROM_CPU_BETA1 0x00000194
707
708
709#define NV01_IMAGE_FROM_CPU_SURFACE_DST 0x00000198
710
711
712#define NV04_IMAGE_FROM_CPU_BETA4 0x00000198
713
714#define NV04_IMAGE_FROM_CPU_SURFACE 0x0000019c
715
716#define NV05_IMAGE_FROM_CPU_COLOR_CONVERSION 0x000002f8
717
718#define NV01_IMAGE_FROM_CPU_OPERATION 0x000002fc
719#define NV01_IMAGE_FROM_CPU_OPERATION_SRCCOPY_AND 0x00000000
720#define NV01_IMAGE_FROM_CPU_OPERATION_ROP_AND 0x00000001
721#define NV01_IMAGE_FROM_CPU_OPERATION_BLEND_AND 0x00000002
722#define NV01_IMAGE_FROM_CPU_OPERATION_SRCCOPY 0x00000003
723#define NV01_IMAGE_FROM_CPU_OPERATION_SRCCOPY_PREMULT 0x00000004
724#define NV01_IMAGE_FROM_CPU_OPERATION_BLEND_PREMULT 0x00000005
725
726#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT 0x00000300
727#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT_R5G6G5 0x00000001
728#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT_A1R5G5B5 0x00000002
729#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT_X1R5G5B5 0x00000003
730#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT_A8R8G8B8 0x00000004
731#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT_X8R8G8B8 0x00000005
732
733#define NV01_IMAGE_FROM_CPU_POINT 0x00000304
734#define NV01_IMAGE_FROM_CPU_POINT_X__MASK 0x0000ffff
735#define NV01_IMAGE_FROM_CPU_POINT_X__SHIFT 0
736#define NV01_IMAGE_FROM_CPU_POINT_Y__MASK 0xffff0000
737#define NV01_IMAGE_FROM_CPU_POINT_Y__SHIFT 16
738
739#define NV01_IMAGE_FROM_CPU_SIZE_OUT 0x00000308
740#define NV01_IMAGE_FROM_CPU_SIZE_OUT_W__MASK 0x0000ffff
741#define NV01_IMAGE_FROM_CPU_SIZE_OUT_W__SHIFT 0
742#define NV01_IMAGE_FROM_CPU_SIZE_OUT_H__MASK 0xffff0000
743#define NV01_IMAGE_FROM_CPU_SIZE_OUT_H__SHIFT 16
744
745#define NV01_IMAGE_FROM_CPU_SIZE_IN 0x0000030c
746#define NV01_IMAGE_FROM_CPU_SIZE_IN_W__MASK 0x0000ffff
747#define NV01_IMAGE_FROM_CPU_SIZE_IN_W__SHIFT 0
748#define NV01_IMAGE_FROM_CPU_SIZE_IN_H__MASK 0xffff0000
749#define NV01_IMAGE_FROM_CPU_SIZE_IN_H__SHIFT 16
750
751#define NV01_IMAGE_FROM_CPU_COLOR(i0) (0x00000400 + 0x4*(i0))
752#define NV01_IMAGE_FROM_CPU_COLOR__ESIZE 0x00000004
753#define NV01_IMAGE_FROM_CPU_COLOR__LEN 0x00000020
754
755#define NV04_IMAGE_FROM_CPU_COLOR(i0) (0x00000400 + 0x4*(i0))
756#define NV04_IMAGE_FROM_CPU_COLOR__ESIZE 0x00000004
757#define NV04_IMAGE_FROM_CPU_COLOR__LEN 0x00000700
758
759
760#define NV03_STRETCHED_IMAGE_FROM_CPU_PATCH 0x0000010c
761
762#define NV03_STRETCHED_IMAGE_FROM_CPU_DMA_NOTIFY 0x00000180
763
764#define NV03_STRETCHED_IMAGE_FROM_CPU_COLOR_KEY 0x00000184
765
766#define NV04_STRETCHED_IMAGE_FROM_CPU_COLOR_KEY 0x00000184
767
768#define NV03_STRETCHED_IMAGE_FROM_CPU_PATTERN 0x00000188
769
770#define NV04_STRETCHED_IMAGE_FROM_CPU_PATTERN 0x00000188
771
772#define NV03_STRETCHED_IMAGE_FROM_CPU_ROP 0x0000018c
773
774#define NV03_STRETCHED_IMAGE_FROM_CPU_BETA1 0x00000190
775
776
777#define NV03_STRETCHED_IMAGE_FROM_CPU_SURFACE_DST 0x00000194
778
779
780#define NV04_STRETCHED_IMAGE_FROM_CPU_BETA4 0x00000194
781
782#define NV04_STRETCHED_IMAGE_FROM_CPU_SURFACE 0x00000198
783
784#define NV05_STRETCHED_IMAGE_FROM_CPU_COLOR_CONVERSION 0x000002f8
785
786#define NV03_STRETCHED_IMAGE_FROM_CPU_OPERATION 0x000002fc
787
788#define NV03_STRETCHED_IMAGE_FROM_CPU_COLOR_FORMAT 0x00000300
789
790#define NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN 0x00000304
791#define NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN_W__MASK 0x0000ffff
792#define NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN_W__SHIFT 0
793#define NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN_H__MASK 0xffff0000
794#define NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN_H__SHIFT 16
795
796#define NV03_STRETCHED_IMAGE_FROM_CPU_DX_DU 0x00000308
797
798#define NV03_STRETCHED_IMAGE_FROM_CPU_DY_DV 0x0000030c
799
800#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT 0x00000310
801#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT_X__MASK 0x0000ffff
802#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT_X__SHIFT 0
803#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT_Y__MASK 0xffff0000
804#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT_Y__SHIFT 16
805
806#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE 0x00000314
807#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE_W__MASK 0x0000ffff
808#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE_W__SHIFT 0
809#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE_H__MASK 0xffff0000
810#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE_H__SHIFT 16
811
812#define NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4 0x00000318
813#define NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4_X__MASK 0x0000ffff
814#define NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4_X__SHIFT 0
815#define NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4_Y__MASK 0xffff0000
816#define NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4_Y__SHIFT 16
817
818#define NV03_STRETCHED_IMAGE_FROM_CPU_COLOR(i0) (0x00000400 + 0x4*(i0))
819#define NV03_STRETCHED_IMAGE_FROM_CPU_COLOR__ESIZE 0x00000004
820#define NV03_STRETCHED_IMAGE_FROM_CPU_COLOR__LEN 0x00000700
821
822
823#define NV10_SCALED_IMAGE_FROM_MEMORY_WAIT_FOR_IDLE 0x00000108
824
825#define NV03_SCALED_IMAGE_FROM_MEMORY_DMA_NOTIFY 0x00000180
826
827#define NV03_SCALED_IMAGE_FROM_MEMORY_DMA_IMAGE 0x00000184
828
829#define NV03_SCALED_IMAGE_FROM_MEMORY_PATTERN 0x00000188
830
831#define NV04_SCALED_IMAGE_FROM_MEMORY_PATTERN 0x00000188
832
833#define NV03_SCALED_IMAGE_FROM_MEMORY_ROP 0x0000018c
834
835#define NV03_SCALED_IMAGE_FROM_MEMORY_BETA1 0x00000190
836
837
838#define NV03_SCALED_IMAGE_FROM_MEMORY_SURFACE_DST 0x00000194
839
840
841#define NV04_SCALED_IMAGE_FROM_MEMORY_BETA4 0x00000194
842
843#define NV04_SCALED_IMAGE_FROM_MEMORY_SURFACE 0x00000198
844
845#define NV05_SCALED_IMAGE_FROM_MEMORY_SURFACE 0x00000198
846
847#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION 0x000002fc
848#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_DITHER 0x00000000
849#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_TRUNCATE 0x00000001
850#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_SUBTR_TRUNCATE 0x00000002
851
852#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT 0x00000300
853#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A1R5G5B5 0x00000001
854#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X1R5G5B5 0x00000002
855#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A8R8G8B8 0x00000003
856#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X8R8G8B8 0x00000004
857#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_V8YB8U8YA8 0x00000005
858#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_YB8V8YA8U8 0x00000006
859#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_R5G6B5 0x00000007
860#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_Y8 0x00000008
861#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_AY8 0x00000009
862
863#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION 0x00000304
864#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY_AND 0x00000000
865#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_ROP_AND 0x00000001
866#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_BLEND_AND 0x00000002
867#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY 0x00000003
868#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY_PREMULT 0x00000004
869#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_BLEND_PREMULT 0x00000005
870
871#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT 0x00000308
872#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_X__MASK 0x0000ffff
873#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_X__SHIFT 0
874#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_Y__MASK 0xffff0000
875#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_Y__SHIFT 16
876
877#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE 0x0000030c
878#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_W__MASK 0x0000ffff
879#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_W__SHIFT 0
880#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_H__MASK 0xffff0000
881#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_H__SHIFT 16
882
883#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT 0x00000310
884#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_X__MASK 0x0000ffff
885#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_X__SHIFT 0
886#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_Y__MASK 0xffff0000
887#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_Y__SHIFT 16
888
889#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE 0x00000314
890#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_W__MASK 0x0000ffff
891#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_W__SHIFT 0
892#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_H__MASK 0xffff0000
893#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_H__SHIFT 16
894
895#define NV03_SCALED_IMAGE_FROM_MEMORY_DU_DX 0x00000318
896
897#define NV03_SCALED_IMAGE_FROM_MEMORY_DV_DY 0x0000031c
898
899#define NV03_SCALED_IMAGE_FROM_MEMORY_SIZE 0x00000400
900#define NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_W__MASK 0x0000ffff
901#define NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_W__SHIFT 0
902#define NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_H__MASK 0xffff0000
903#define NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_H__SHIFT 16
904
905#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT 0x00000404
906#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_PITCH__MASK 0x0000ffff
907#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_PITCH__SHIFT 0
908#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN__MASK 0x00ff0000
909#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN__SHIFT 16
910#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CENTER 0x00010000
911#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CORNER 0x00020000
912#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER__MASK 0xff000000
913#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER__SHIFT 24
914#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_POINT_SAMPLE 0x00000000
915#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_BILINEAR 0x01000000
916
917#define NV03_SCALED_IMAGE_FROM_MEMORY_OFFSET 0x00000408
918
919#define NV03_SCALED_IMAGE_FROM_MEMORY_POINT 0x0000040c
920#define NV03_SCALED_IMAGE_FROM_MEMORY_POINT_U__MASK 0x0000ffff
921#define NV03_SCALED_IMAGE_FROM_MEMORY_POINT_U__SHIFT 0
922#define NV03_SCALED_IMAGE_FROM_MEMORY_POINT_V__MASK 0xffff0000
923#define NV03_SCALED_IMAGE_FROM_MEMORY_POINT_V__SHIFT 16
924
925
926#define NV50_SCALED_IMAGE_FROM_MEMORY_OFFSET_HIGH 0x00000410
927
928#define NV50_SCALED_IMAGE_FROM_MEMORY_SRC_LINEAR 0x00000414
929
930#define NV50_SCALED_IMAGE_FROM_MEMORY_SRC_TILE_MODE 0x00000418
931
932
933#define NV03_GDI_RECTANGLE_TEXT_DMA_NOTIFY 0x00000180
934
935#define NV03_GDI_RECTANGLE_TEXT_PATTERN 0x00000184
936
937#define NV03_GDI_RECTANGLE_TEXT_ROP 0x00000188
938
939#define NV03_GDI_RECTANGLE_TEXT_BETA1 0x0000019c
940
941#define NV03_GDI_RECTANGLE_TEXT_SURFACE_DST 0x00000190
942
943#define NV03_GDI_RECTANGLE_TEXT_OPERATION 0x000002fc
944
945#define NV03_GDI_RECTANGLE_TEXT_COLOR_FORMAT 0x00000300
946
947#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT 0x00000304
948
949#define NV03_GDI_RECTANGLE_TEXT_COLOR1_A 0x000003fc
950
951#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT 0x00000400
952#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_Y__MASK 0x0000ffff
953#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_Y__SHIFT 0
954#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_X__MASK 0xffff0000
955#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_X__SHIFT 16
956
957#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE 0x00000404
958#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_H__MASK 0x0000ffff
959#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_H__SHIFT 0
960#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_W__MASK 0xffff0000
961#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_W__SHIFT 16
962
963#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B 0x000007f4
964#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B_L__MASK 0x0000ffff
965#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B_L__SHIFT 0
966#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B_T__MASK 0xffff0000
967#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B_T__SHIFT 16
968
969#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B 0x000007f8
970#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B_R__MASK 0x0000ffff
971#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B_R__SHIFT 0
972#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B_B__MASK 0xffff0000
973#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B_B__SHIFT 16
974
975#define NV03_GDI_RECTANGLE_TEXT_COLOR1_B 0x000007fc
976
977#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0 0x00000800
978#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_L__MASK 0x0000ffff
979#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_L__SHIFT 0
980#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_T__MASK 0xffff0000
981#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_T__SHIFT 16
982
983#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1 0x00000804
984#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_R__MASK 0x0000ffff
985#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_R__SHIFT 0
986#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_B__MASK 0xffff0000
987#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_B__SHIFT 16
988
989#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0 0x00000bec
990#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_L__MASK 0x0000ffff
991#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_L__SHIFT 0
992#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_T__MASK 0xffff0000
993#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_T__SHIFT 16
994
995#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1 0x00000bf0
996#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_R__MASK 0x0000ffff
997#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_R__SHIFT 0
998#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_B__MASK 0xffff0000
999#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_B__SHIFT 16
1000
1001#define NV03_GDI_RECTANGLE_TEXT_COLOR1_C 0x00000bf4
1002
1003#define NV03_GDI_RECTANGLE_TEXT_SIZE_C 0x00000bf8
1004#define NV03_GDI_RECTANGLE_TEXT_SIZE_C_W__MASK 0x0000ffff
1005#define NV03_GDI_RECTANGLE_TEXT_SIZE_C_W__SHIFT 0
1006#define NV03_GDI_RECTANGLE_TEXT_SIZE_C_H__MASK 0xffff0000
1007#define NV03_GDI_RECTANGLE_TEXT_SIZE_C_H__SHIFT 16
1008
1009#define NV03_GDI_RECTANGLE_TEXT_POINT_C 0x00000bfc
1010#define NV03_GDI_RECTANGLE_TEXT_POINT_C_X__MASK 0x0000ffff
1011#define NV03_GDI_RECTANGLE_TEXT_POINT_C_X__SHIFT 0
1012#define NV03_GDI_RECTANGLE_TEXT_POINT_C_Y__MASK 0xffff0000
1013#define NV03_GDI_RECTANGLE_TEXT_POINT_C_Y__SHIFT 16
1014
1015#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C(i0) (0x00000c00 + 0x4*(i0))
1016#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C__ESIZE 0x00000004
1017#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C__LEN 0x00000020
1018
1019#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0 0x00000fe8
1020#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0_L__MASK 0x0000ffff
1021#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0_L__SHIFT 0
1022#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0_T__MASK 0xffff0000
1023#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0_T__SHIFT 16
1024
1025#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1 0x00000fec
1026#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1_R__MASK 0x0000ffff
1027#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1_R__SHIFT 0
1028#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1_B__MASK 0xffff0000
1029#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1_B__SHIFT 16
1030
1031#define NV03_GDI_RECTANGLE_TEXT_COLOR1_D 0x00000ff0
1032
1033#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D 0x00000ff4
1034#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D_W__MASK 0x0000ffff
1035#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D_W__SHIFT 0
1036#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D_H__MASK 0xffff0000
1037#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D_H__SHIFT 16
1038
1039#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D 0x00000ff8
1040#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D_W__MASK 0x0000ffff
1041#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D_W__SHIFT 0
1042#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D_H__MASK 0xffff0000
1043#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D_H__SHIFT 16
1044
1045#define NV03_GDI_RECTANGLE_TEXT_POINT_D 0x00000ffc
1046#define NV03_GDI_RECTANGLE_TEXT_POINT_D_X__MASK 0x0000ffff
1047#define NV03_GDI_RECTANGLE_TEXT_POINT_D_X__SHIFT 0
1048#define NV03_GDI_RECTANGLE_TEXT_POINT_D_Y__MASK 0xffff0000
1049#define NV03_GDI_RECTANGLE_TEXT_POINT_D_Y__SHIFT 16
1050
1051#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_D(i0) (0x00001000 + 0x4*(i0))
1052#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_D__ESIZE 0x00000004
1053#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_D__LEN 0x00000020
1054
1055#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0 0x000013e4
1056#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_L__MASK 0x0000ffff
1057#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_L__SHIFT 0
1058#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_T__MASK 0xffff0000
1059#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_T__SHIFT 16
1060
1061#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1 0x000013e8
1062#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_R__MASK 0x0000ffff
1063#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_R__SHIFT 0
1064#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_B__MASK 0xffff0000
1065#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_B__SHIFT 16
1066
1067#define NV03_GDI_RECTANGLE_TEXT_COLOR0_E 0x000013ec
1068
1069#define NV03_GDI_RECTANGLE_TEXT_COLOR1_E 0x000013f0
1070
1071#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E 0x000013f4
1072#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E_W__MASK 0x0000ffff
1073#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E_W__SHIFT 0
1074#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E_H__MASK 0xffff0000
1075#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E_H__SHIFT 16
1076
1077#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E 0x000013f8
1078#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E_W__MASK 0x0000ffff
1079#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E_W__SHIFT 0
1080#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E_H__MASK 0xffff0000
1081#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E_H__SHIFT 16
1082
1083#define NV03_GDI_RECTANGLE_TEXT_POINT_E 0x000013fc
1084#define NV03_GDI_RECTANGLE_TEXT_POINT_E_X__MASK 0x0000ffff
1085#define NV03_GDI_RECTANGLE_TEXT_POINT_E_X__SHIFT 0
1086#define NV03_GDI_RECTANGLE_TEXT_POINT_E_Y__MASK 0xffff0000
1087#define NV03_GDI_RECTANGLE_TEXT_POINT_E_Y__SHIFT 16
1088
1089#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E(i0) (0x00001400 + 0x4*(i0))
1090#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E__ESIZE 0x00000004
1091#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E__LEN 0x00000020
1092
1093
1094#define NV04_GDI_RECTANGLE_TEXT_PATCH 0x0000010c
1095
1096#define NV04_GDI_RECTANGLE_TEXT_DMA_NOTIFY 0x00000180
1097
1098#define NV04_GDI_RECTANGLE_TEXT_DMA_FONTS 0x00000184
1099
1100#define NV04_GDI_RECTANGLE_TEXT_PATTERN 0x00000188
1101
1102#define NV04_GDI_RECTANGLE_TEXT_ROP 0x0000018c
1103
1104#define NV04_GDI_RECTANGLE_TEXT_BETA1 0x00000190
1105
1106#define NV04_GDI_RECTANGLE_TEXT_BETA4 0x00000194
1107
1108#define NV04_GDI_RECTANGLE_TEXT_SURFACE 0x00000198
1109
1110#define NV04_GDI_RECTANGLE_TEXT_OPERATION 0x000002fc
1111#define NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY_AND 0x00000000
1112#define NV04_GDI_RECTANGLE_TEXT_OPERATION_ROP_AND 0x00000001
1113#define NV04_GDI_RECTANGLE_TEXT_OPERATION_BLEND_AND 0x00000002
1114#define NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY 0x00000003
1115#define NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY_PREMULT 0x00000004
1116#define NV04_GDI_RECTANGLE_TEXT_OPERATION_BLEND_PREMULT 0x00000005
1117
1118#define NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT 0x00000300
1119#define NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A16R5G6B5 0x00000001
1120#define NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_X16A1R5G5B5 0x00000002
1121#define NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8 0x00000003
1122
1123#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT 0x00000304
1124#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT_CGA6 0x00000001
1125#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT_LE 0x00000002
1126
1127#define NV04_GDI_RECTANGLE_TEXT_COLOR1_A 0x000003fc
1128
1129#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT(i0) (0x00000400 + 0x8*(i0))
1130#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT__ESIZE 0x00000008
1131#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT__LEN 0x00000020
1132#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_Y__MASK 0x0000ffff
1133#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_Y__SHIFT 0
1134#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_X__MASK 0xffff0000
1135#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_X__SHIFT 16
1136
1137#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE(i0) (0x00000404 + 0x8*(i0))
1138#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE__ESIZE 0x00000008
1139#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE__LEN 0x00000020
1140#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_H__MASK 0x0000ffff
1141#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_H__SHIFT 0
1142#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_W__MASK 0xffff0000
1143#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_W__SHIFT 16
1144
1145#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0 0x000005f4
1146#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0_L__MASK 0x0000ffff
1147#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0_L__SHIFT 0
1148#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0_T__MASK 0xffff0000
1149#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0_T__SHIFT 16
1150
1151#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1 0x000005f8
1152#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1_R__MASK 0x0000ffff
1153#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1_R__SHIFT 0
1154#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1_B__MASK 0xffff0000
1155#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1_B__SHIFT 16
1156
1157#define NV04_GDI_RECTANGLE_TEXT_COLOR1_B 0x000005fc
1158
1159#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0(i0) (0x00000600 + 0x8*(i0))
1160#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0__ESIZE 0x00000008
1161#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0__LEN 0x00000020
1162#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_L__MASK 0x0000ffff
1163#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_L__SHIFT 0
1164#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_T__MASK 0xffff0000
1165#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_T__SHIFT 16
1166
1167#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1(i0) (0x00000604 + 0x8*(i0))
1168#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1__ESIZE 0x00000008
1169#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1__LEN 0x00000020
1170#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_R__MASK 0x0000ffff
1171#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_R__SHIFT 0
1172#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_B__MASK 0xffff0000
1173#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_B__SHIFT 16
1174
1175#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0 0x000007ec
1176#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_L__MASK 0x0000ffff
1177#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_L__SHIFT 0
1178#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_T__MASK 0xffff0000
1179#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_T__SHIFT 16
1180
1181#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1 0x000007f0
1182#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_R__MASK 0x0000ffff
1183#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_R__SHIFT 0
1184#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_B__MASK 0xffff0000
1185#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_B__SHIFT 16
1186
1187#define NV04_GDI_RECTANGLE_TEXT_COLOR1_C 0x000007f4
1188
1189#define NV04_GDI_RECTANGLE_TEXT_SIZE_C 0x000007f8
1190#define NV04_GDI_RECTANGLE_TEXT_SIZE_C_W__MASK 0x0000ffff
1191#define NV04_GDI_RECTANGLE_TEXT_SIZE_C_W__SHIFT 0
1192#define NV04_GDI_RECTANGLE_TEXT_SIZE_C_H__MASK 0xffff0000
1193#define NV04_GDI_RECTANGLE_TEXT_SIZE_C_H__SHIFT 16
1194
1195#define NV04_GDI_RECTANGLE_TEXT_POINT_C 0x000007fc
1196#define NV04_GDI_RECTANGLE_TEXT_POINT_C_X__MASK 0x0000ffff
1197#define NV04_GDI_RECTANGLE_TEXT_POINT_C_X__SHIFT 0
1198#define NV04_GDI_RECTANGLE_TEXT_POINT_C_Y__MASK 0xffff0000
1199#define NV04_GDI_RECTANGLE_TEXT_POINT_C_Y__SHIFT 16
1200
1201#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C(i0) (0x00000800 + 0x4*(i0))
1202#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C__ESIZE 0x00000004
1203#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C__LEN 0x00000080
1204
1205#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0 0x00000be4
1206#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_L__MASK 0x0000ffff
1207#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_L__SHIFT 0
1208#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_T__MASK 0xffff0000
1209#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_T__SHIFT 16
1210
1211#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1 0x00000be8
1212#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_R__MASK 0x0000ffff
1213#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_R__SHIFT 0
1214#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_B__MASK 0xffff0000
1215#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_B__SHIFT 16
1216
1217#define NV04_GDI_RECTANGLE_TEXT_COLOR0_E 0x00000bec
1218
1219#define NV04_GDI_RECTANGLE_TEXT_COLOR1_E 0x00000bf0
1220
1221#define NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E 0x00000bf4
1222#define NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E_W__MASK 0x0000ffff
1223#define NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E_W__SHIFT 0
1224#define NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E_H__MASK 0xffff0000
1225#define NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E_H__SHIFT 16
1226
1227#define NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E 0x00000bf8
1228#define NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E_W__MASK 0x0000ffff
1229#define NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E_W__SHIFT 0
1230#define NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E_H__MASK 0xffff0000
1231#define NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E_H__SHIFT 16
1232
1233#define NV04_GDI_RECTANGLE_TEXT_POINT_E 0x00000bfc
1234#define NV04_GDI_RECTANGLE_TEXT_POINT_E_X__MASK 0x0000ffff
1235#define NV04_GDI_RECTANGLE_TEXT_POINT_E_X__SHIFT 0
1236#define NV04_GDI_RECTANGLE_TEXT_POINT_E_Y__MASK 0xffff0000
1237#define NV04_GDI_RECTANGLE_TEXT_POINT_E_Y__SHIFT 16
1238
1239#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E(i0) (0x00000c00 + 0x4*(i0))
1240#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E__ESIZE 0x00000004
1241#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E__LEN 0x00000080
1242
1243#define NV04_GDI_RECTANGLE_TEXT_FONT_F 0x00000ff0
1244#define NV04_GDI_RECTANGLE_TEXT_FONT_F_OFFSET__MASK 0x0fffffff
1245#define NV04_GDI_RECTANGLE_TEXT_FONT_F_OFFSET__SHIFT 0
1246#define NV04_GDI_RECTANGLE_TEXT_FONT_F_PITCH__MASK 0xf0000000
1247#define NV04_GDI_RECTANGLE_TEXT_FONT_F_PITCH__SHIFT 28
1248
1249#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0 0x00000ff4
1250#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0_L__MASK 0x0000ffff
1251#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0_L__SHIFT 0
1252#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0_T__MASK 0xffff0000
1253#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0_T__SHIFT 16
1254
1255#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1 0x00000ff8
1256#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1_R__MASK 0x0000ffff
1257#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1_R__SHIFT 0
1258#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1_B__MASK 0xffff0000
1259#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1_B__SHIFT 16
1260
1261#define NV04_GDI_RECTANGLE_TEXT_COLOR1_F 0x00000ffc
1262
1263#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F(i0) (0x00001000 + 0x4*(i0))
1264#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F__ESIZE 0x00000004
1265#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F__LEN 0x00000100
1266#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_INDEX__MASK 0x000000ff
1267#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_INDEX__SHIFT 0
1268#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_X__MASK 0x000fff00
1269#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_X__SHIFT 8
1270#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_Y__MASK 0xfff00000
1271#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_Y__SHIFT 20
1272
1273#define NV04_GDI_RECTANGLE_TEXT_FONT_G 0x000017f0
1274#define NV04_GDI_RECTANGLE_TEXT_FONT_G_OFFSET__MASK 0x0fffffff
1275#define NV04_GDI_RECTANGLE_TEXT_FONT_G_OFFSET__SHIFT 0
1276#define NV04_GDI_RECTANGLE_TEXT_FONT_G_PITCH__MASK 0xf0000000
1277#define NV04_GDI_RECTANGLE_TEXT_FONT_G_PITCH__SHIFT 28
1278
1279#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0 0x000017f4
1280#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0_L__MASK 0x0000ffff
1281#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0_L__SHIFT 0
1282#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0_T__MASK 0xffff0000
1283#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0_T__SHIFT 16
1284
1285#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1 0x000017f8
1286#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1_R__MASK 0x0000ffff
1287#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1_R__SHIFT 0
1288#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1_B__MASK 0xffff0000
1289#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1_B__SHIFT 16
1290
1291#define NV04_GDI_RECTANGLE_TEXT_COLOR1_G 0x000017fc
1292
1293#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT(i0) (0x00001800 + 0x8*(i0))
1294#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT__ESIZE 0x00000008
1295#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT__LEN 0x00000100
1296#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT_X__MASK 0x0000ffff
1297#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT_X__SHIFT 0
1298#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT_Y__MASK 0xffff0000
1299#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT_Y__SHIFT 16
1300
1301#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_INDEX(i0) (0x00001804 + 0x8*(i0))
1302#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_INDEX__ESIZE 0x00000008
1303#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_INDEX__LEN 0x00000100
1304
1305
1306#define NV10_TEXTURE_FROM_CPU_WAIT_FOR_IDLE 0x00000108
1307
1308#define NV10_TEXTURE_FROM_CPU_DMA_NOTIFY 0x00000180
1309
1310#define NV10_TEXTURE_FROM_CPU_SURFACE 0x00000184
1311
1312#define NV10_TEXTURE_FROM_CPU_COLOR_FORMAT 0x00000300
1313
1314#define NV10_TEXTURE_FROM_CPU_POINT 0x00000304
1315#define NV10_TEXTURE_FROM_CPU_POINT_X__MASK 0x0000ffff
1316#define NV10_TEXTURE_FROM_CPU_POINT_X__SHIFT 0
1317#define NV10_TEXTURE_FROM_CPU_POINT_Y__MASK 0xffff0000
1318#define NV10_TEXTURE_FROM_CPU_POINT_Y__SHIFT 16
1319
1320#define NV10_TEXTURE_FROM_CPU_SIZE 0x00000308
1321#define NV10_TEXTURE_FROM_CPU_SIZE_W__MASK 0x0000ffff
1322#define NV10_TEXTURE_FROM_CPU_SIZE_W__SHIFT 0
1323#define NV10_TEXTURE_FROM_CPU_SIZE_H__MASK 0xffff0000
1324#define NV10_TEXTURE_FROM_CPU_SIZE_H__SHIFT 16
1325
1326#define NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL 0x0000030c
1327#define NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL_X__MASK 0x0000ffff
1328#define NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL_X__SHIFT 0
1329#define NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL_W__MASK 0xffff0000
1330#define NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL_W__SHIFT 16
1331
1332#define NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL 0x00000310
1333#define NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL_Y__MASK 0x0000ffff
1334#define NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL_Y__SHIFT 0
1335#define NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL_H__MASK 0xffff0000
1336#define NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL_H__SHIFT 16
1337
1338#define NV10_TEXTURE_FROM_CPU_COLOR(i0) (0x00000400 + 0x4*(i0))
1339#define NV10_TEXTURE_FROM_CPU_COLOR__ESIZE 0x00000004
1340#define NV10_TEXTURE_FROM_CPU_COLOR__LEN 0x00000700
1341
1342
1343#endif /* NV01_2D_XML */
diff --git a/src/gallium/drivers/nvfx/nv04_2d.c b/src/gallium/drivers/nvfx/nv04_2d.c
deleted file mode 100644
index e2fadd33e1c..00000000000
--- a/src/gallium/drivers/nvfx/nv04_2d.c
+++ /dev/null
@@ -1,1393 +0,0 @@
1/**************************************************************************
2 *
3 * Copyright 2009 Ben Skeggs
4 * Copyright 2009 Younes Manton
5 * Copyright 2010 Luca Barbieri
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining
9 * a copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
18 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
19 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
20 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 * The above copyright notice and this permission notice (including the
26 * next paragraph) shall be included in all copies or substantial portions
27 * of the Software.
28 *
29 **************************************************************************/
30
31/* this code has no Mesa or Gallium dependency and can be reused in the classic Mesa driver or DDX */
32
33#include <stdlib.h>
34#include <stdio.h>
35#include <stdint.h>
36#include <nouveau/nouveau_device.h>
37#include <nouveau/nouveau_channel.h>
38#include <nouveau/nouveau_bo.h>
39#include <nouveau/nouveau_notifier.h>
40#include <nouveau/nouveau_grobj.h>
41#include <nouveau/nv04_pushbuf.h>
42#include "nv04_2d.h"
43
44#include "nouveau/nv_object.xml.h"
45#include "nouveau/nv_m2mf.xml.h"
46#include "nv01_2d.xml.h"
47
48/* avoid depending on Mesa/Gallium */
49#ifdef __GNUC__
50#define likely(x) __builtin_expect(!!(x), 1)
51#define unlikely(x) __builtin_expect(!!(x), 0)
52#else
53#define likely(x) !!(x)
54#define unlikely(x) !!(x)
55#endif
56
57#define MIN2( A, B ) ( (A)<(B) ? (A) : (B) )
58#define MAX2( A, B ) ( (A)>(B) ? (A) : (B) )
59
60struct nv04_2d_context
61{
62 struct nouveau_notifier *ntfy;
63 struct nouveau_grobj *surf2d;
64 struct nouveau_grobj *swzsurf;
65 struct nouveau_grobj *m2mf;
66 struct nouveau_grobj *rect;
67 struct nouveau_grobj *sifm;
68 struct nouveau_grobj *blit;
69};
70
71static inline int
72align(int value, int alignment)
73{
74 return (value + alignment - 1) & ~(alignment - 1);
75}
76
77static inline int
78util_is_pot(unsigned x)
79{
80 return (x & (x - 1)) == 0;
81}
82
83/* Integer base-2 logarithm, rounded towards zero. */
84static inline unsigned log2i(unsigned i)
85{
86 unsigned r = 0;
87
88 if (i & 0xffff0000) {
89 i >>= 16;
90 r += 16;
91 }
92 if (i & 0x0000ff00) {
93 i >>= 8;
94 r += 8;
95 }
96 if (i & 0x000000f0) {
97 i >>= 4;
98 r += 4;
99 }
100 if (i & 0x0000000c) {
101 i >>= 2;
102 r += 2;
103 }
104 if (i & 0x00000002) {
105 r += 1;
106 }
107 return r;
108}
109
110//#define NV04_REGION_DEBUG
111
112// Yes, we really want to inline everything, since all the functions are used only once
113#if defined(__GNUC__) && !defined(DEBUG)
114#define inline __attribute__((always_inline)) inline
115#endif
116
117static inline unsigned
118nv04_swizzle_bits_square(unsigned x, unsigned y)
119{
120 unsigned u = (x & 0x001) << 0 |
121 (x & 0x002) << 1 |
122 (x & 0x004) << 2 |
123 (x & 0x008) << 3 |
124 (x & 0x010) << 4 |
125 (x & 0x020) << 5 |
126 (x & 0x040) << 6 |
127 (x & 0x080) << 7 |
128 (x & 0x100) << 8 |
129 (x & 0x200) << 9 |
130 (x & 0x400) << 10 |
131 (x & 0x800) << 11;
132
133 unsigned v = (y & 0x001) << 1 |
134 (y & 0x002) << 2 |
135 (y & 0x004) << 3 |
136 (y & 0x008) << 4 |
137 (y & 0x010) << 5 |
138 (y & 0x020) << 6 |
139 (y & 0x040) << 7 |
140 (y & 0x080) << 8 |
141 (y & 0x100) << 9 |
142 (y & 0x200) << 10 |
143 (y & 0x400) << 11 |
144 (y & 0x800) << 12;
145 return v | u;
146}
147
148/* rectangular swizzled textures are linear concatenations of swizzled square tiles */
149static inline unsigned
150nv04_swizzle_bits_2d(unsigned x, unsigned y, unsigned w, unsigned h)
151{
152 if(h <= 1)
153 return x;
154 else
155 {
156 unsigned s = MIN2(w, h);
157 unsigned m = s - 1;
158 return (((x | y) & ~m) * s) | nv04_swizzle_bits_square(x & m, y & m);
159 }
160}
161
162// general 3D texture case
163static inline unsigned
164nv04_swizzle_bits(unsigned x, unsigned y, unsigned z, unsigned w, unsigned h, unsigned d)
165{
166 if(d <= 1)
167 return nv04_swizzle_bits_2d(x, y, w, h);
168 else
169 {
170 // TODO: autogenerate code for all possible texture sizes (13 * 13 * 13 with dims <= 4096) and do a single indirect call
171 unsigned v = 0;
172 w >>= 1;
173 h >>= 1;
174 d >>= 1;
175 for(int i = 0;;)
176 {
177 int oldi = i;
178 if(likely(w))
179 {
180 v |= (x & 1) << i;
181 x >>= 1;
182 w >>= 1;
183 ++i;
184 }
185
186 if(likely(h))
187 {
188 v |= (y & 1) << i;
189 y >>= 1;
190 h >>= 1;
191 ++i;
192 }
193
194 if(likely(d))
195 {
196 v |= (z & 1) << i;
197 z >>= 1;
198 d >>= 1;
199 ++i;
200 }
201
202 if(i == oldi)
203 break;
204 }
205 return v;
206 }
207}
208
209unsigned
210nv04_region_begin(struct nv04_region* rgn, unsigned w, unsigned h)
211{
212 if(rgn->pitch)
213 return rgn->pitch * rgn->y + (rgn->x << rgn->bpps);
214 else
215 return nv04_swizzle_bits(rgn->x, rgn->y, rgn->z, rgn->w, rgn->h, rgn->d) << rgn->bpps;
216}
217
218unsigned
219nv04_region_end(struct nv04_region* rgn, unsigned w, unsigned h)
220{
221 if(rgn->pitch)
222 return rgn->pitch * (rgn->y + h - 1) + ((rgn->x + w) << rgn->bpps);
223 else
224 return (nv04_swizzle_bits(rgn->x + w - 1, rgn->y + h - 1, rgn->z, rgn->w, rgn->h, rgn->d) + 1) << rgn->bpps;
225}
226
227// *pitch = -1 -> use 3D swizzling for (x, y), *pitch = 0 -> use 2D swizzling, other *pitch -> use linear calculations
228// returns 2 if pixel order is 3D-swizzled and 1 if subrect is 2D-swizzled
229/* *pitch == -1 ret = 0 -> 3D swizzled subrect
230 * *pitch == 0 ret = 0 -> 2D swizzled subrect
231 * *pitch > 0 ret = 0 -> linear subrect
232 * *pitch > 0 ret = 1 -> linear subrect, but with swizzled 3D data inside
233 */
234
235static inline void
236nv04_region_print(struct nv04_region* rgn)
237{
238 fprintf(stderr, "<%i[%i]> ", rgn->bo->handle, rgn->offset);
239 if(rgn->pitch)
240 fprintf(stderr, "lin %i", rgn->pitch);
241 else
242 fprintf(stderr, "swz %ix%ix%i", rgn->w, rgn->h, rgn->d);
243 fprintf(stderr, " (%i, %i, %i)", rgn->x, rgn->y, rgn->z);
244}
245
246static inline void
247nv04_region_assert(struct nv04_region* rgn, unsigned w, unsigned h)
248{
249 unsigned end = rgn->offset + nv04_region_end(rgn, w, h);
250
251 assert(rgn->offset <= (int)rgn->bo->size);
252 assert(end <= rgn->bo->size);
253 (void) end;
254 if(!rgn->pitch) {
255 assert(util_is_pot(rgn->w));
256 assert(util_is_pot(rgn->h));
257 }
258}
259
260/* determine if region can be linearized or fake-linearized */
261static inline int
262nv04_region_is_contiguous(struct nv04_region* rgn, int w, int h)
263{
264 int surf_min;
265 int rect_min;
266
267 if(rgn->pitch)
268 return rgn->pitch == w << rgn->bpps;
269
270 // redundant, but this is the fast path for the common case
271 if(w == rgn->w && h == rgn->h && rgn->d <= 1)
272 return 1;
273
274 // must be POT
275 if((w & (w - 1)) || (h & (h - 1)))
276 return 0;
277
278 // must be aligned
279 if((rgn->x & (w - 1)) || (rgn->y & (h - 1)))
280 return 0;
281
282 if(rgn->d > 1)
283 return 0;
284
285 surf_min = MIN2(rgn->w, rgn->h);
286 rect_min = MIN2(w, h);
287
288 if((rect_min == surf_min) || (w == h) || (w == 2 * h))
289 return 1;
290
291 return 0;
292}
293
294// double the pitch until it is larger than the alignment, or the height becomes odd or 1
295static inline void
296nv04_region_contiguous_shape(struct nv04_region* rgn, int* w, int* h, int align)
297{
298 while(!(*h & 1) && (*w << rgn->bpps) < (1 << align))
299 {
300 *w <<= 1;
301 *h >>= 1;
302 }
303
304 while((*w << rgn->bpps) > 16384 && !(*w & 1))
305 {
306 *w >>= 1;
307 *h <<= 1;
308 }
309
310#ifdef NV04_REGION_DEBUG
311 fprintf(stderr, "\tCONTIGUOUS %ix%i\n", *w, *h);
312#endif
313}
314
315static inline void
316nv04_region_linearize_contiguous(struct nv04_region* rgn, unsigned w, unsigned h)
317{
318 int pos;
319 if(rgn->pitch)
320 {
321 rgn->offset += rgn->y * rgn->pitch + (rgn->x << rgn->bpps);
322 rgn->x = 0;
323 rgn->y = 0;
324 }
325 else
326 {
327 rgn->offset += (rgn->w * rgn->h * rgn->z) << rgn->bpps;
328 pos = nv04_swizzle_bits(rgn->x, rgn->y, rgn->z, rgn->w, rgn->h, rgn->d);
329 rgn->x = pos & (w - 1);
330 rgn->y = pos / w;
331 }
332 rgn->pitch = w << rgn->bpps;
333
334#ifdef NV04_REGION_DEBUG
335 fprintf(stderr, "\tLINEARIZE ");
336 nv04_region_print(rgn);
337 fprintf(stderr, "\n");
338#endif
339}
340
341 /* preserve the offset! */
342 /*
343 rgn->pitch = util_format_get_stride(rgn->format, w);
344 int pos = nv04_swizzle_bits(rgn->x, rgn->y, rgn->z, rgn->w, rgn->h, rgn->d);
345 rgn->x = pos & (w - 1);
346 rgn->y = pos & ~(w - 1);
347 */
348
349 /*
350 rgn->offset +=
351 rgn->pitch = util_format_get_stride(rgn->format, w);
352 rgn->x = 0;
353 rgn->y = 0;
354 */
355
356/* This code will get used for, and always succeed on:
357 * - 4x2 1bpp swizzled texture mipmap levels
358 * - linear regions created by linearization
359 *
360 * This code will get used for, and MAY work for:
361 * - misaligned texture blanket
362 * - linear surfaces created without wide_pitch (in this case, it will only work if we are lucky)
363 *
364 * The general case requires splitting the region in 2.
365 */
366static inline int
367nv04_region_do_align_offset(struct nv04_region* rgn, unsigned w, unsigned h, int shift)
368{
369 if(rgn->pitch > 0)
370 {
371 assert(!(rgn->offset & ((1 << rgn->bpps) - 1))); // fatal!
372
373 if(h <= 1)
374 {
375 int delta;
376 rgn->offset += rgn->y * rgn->pitch + (rgn->x << rgn->bpps);
377 delta = rgn->offset & ((1 << shift) - 1);
378 rgn->y = 0;
379 rgn->x = delta >> rgn->bpps;
380 rgn->offset -= delta;
381 rgn->pitch = align((rgn->x + w) << rgn->bpps, 1 << shift);
382 }
383 else
384 {
385 int delta = rgn->offset & ((1 << shift) - 1);
386 int newxo = (rgn->x << rgn->bpps) + delta;
387 int dy = newxo / rgn->pitch;
388 newxo -= dy * rgn->pitch;
389 if((newxo + (w << rgn->bpps)) > rgn->pitch)
390 {
391 // TODO: split the region into two rectangles (!) if *really* necessary, unless the hardware actually supports "wrapping" rectangles
392 // this does not happen if the surface is pitch-aligned, which it should always be
393 assert(0);
394 return -1;
395 }
396 rgn->x = newxo >> rgn->bpps;
397 rgn->y += dy;
398 }
399 }
400 else
401 {
402 int size;
403 int min;
404 int v;
405
406 // we don't care about the alignment of 3D surfaces since the 2D engine can't use them
407 if(rgn->d < 0)
408 return -1;
409
410 min = MIN2(rgn->w, rgn->h);
411 size = min * min << rgn->bpps;
412
413 // this is unfixable, and should not be happening
414 if(rgn->offset & (size - 1))
415 return -1;
416
417 v = (rgn->offset & ((1 << shift) - 1)) / size;
418 rgn->offset -= v * size;
419
420 if(rgn->h == min)
421 {
422 unsigned w;
423 rgn->x += rgn->h * v;
424 w = rgn->w + rgn->h * v;
425
426 while(rgn->w < w)
427 rgn->w += rgn->w;
428 }
429 else
430 {
431 unsigned h;
432 rgn->y += rgn->w * v;
433 h = rgn->h + rgn->w * v;
434
435 while(rgn->h < h)
436 rgn->h += rgn->h;
437 }
438 }
439
440#ifdef NV04_REGION_DEBUG
441 fprintf(stderr, "\tALIGNED ");
442 nv04_region_print(rgn);
443 fprintf(stderr, "\n");
444#endif
445 return 0;
446}
447
448// both pitch and shift
449// will leave the region unchanged if it fails
450static inline int
451nv04_region_align(struct nv04_region* rgn, unsigned w, unsigned h, int shift)
452{
453 if(rgn->pitch & ((1 << shift) - 1))
454 {
455 if(h == 1)
456 goto do_align; /* this will fix pitch too in this case */
457 else
458 return -1;
459 }
460
461 if(rgn->offset & ((1 << shift) - 1))
462 {
463 do_align:
464 if(nv04_region_do_align_offset(rgn, w, h, shift))
465 return -1;
466 }
467 return 0;
468}
469
470/* this contains 22 different copy loops after preprocessing. unfortunately, it's necessary */
471void
472nv04_region_copy_cpu(struct nv04_region* dst, struct nv04_region* src, int w, int h)
473{
474 uint8_t* mdst;
475 uint8_t* msrc;
476 int size;
477
478 if(dst->bo != src->bo)
479 {
480 nouveau_bo_map(dst->bo, NOUVEAU_BO_WR);
481 nouveau_bo_map(src->bo, NOUVEAU_BO_RD);
482 }
483 else
484 nouveau_bo_map(dst->bo, NOUVEAU_BO_WR | NOUVEAU_BO_RD);
485
486 mdst = (uint8_t*)dst->bo->map + dst->offset;
487 msrc = (uint8_t*)src->bo->map + src->offset;
488
489 size = w << dst->bpps;
490
491 nv04_region_assert(dst, w, h);
492 nv04_region_assert(src, w, h);
493
494#ifdef NV04_REGION_DEBUG
495 fprintf(stderr, "\tRGN_COPY_CPU [%i, %i: %i] ", w, h, dst->bpps);
496 for(int i = 0; i < 2; ++i)
497 {
498 nv04_region_print(i ? src : dst);
499 fprintf(stderr, i ? "\n" : " <- ");
500 }
501
502// for(int i = 0; i < 16; ++i)
503// fprintf(stderr, "%02x ", msrc[i]);
504// fprintf(stderr, "\n");
505#endif
506
507 // TODO: support overlapping copies!
508 if(src->pitch && dst->pitch)
509 {
510 mdst += dst->y * dst->pitch + (dst->x << dst->bpps);
511 msrc += src->y * src->pitch + (src->x << src->bpps);
512 if(dst->bo != src->bo)
513 goto simple;
514 else if(mdst < msrc)
515 {
516 if(mdst + size <= msrc)
517 {
518simple:
519 for(int iy = 0; iy < h; ++iy)
520 {
521 assert(mdst + size <= (uint8_t*)dst->bo->map + dst->bo->size);
522 assert(msrc + size <= (uint8_t*)src->bo->map + src->bo->size);
523 memcpy(mdst, msrc, size);
524 msrc += src->pitch; mdst += dst->pitch;
525 }
526 }
527 else
528 {
529 for(int iy = 0; iy < h; ++iy)
530 {
531 assert(mdst + size <= (uint8_t*)dst->bo->map + dst->bo->size);
532 assert(msrc + size <= (uint8_t*)src->bo->map + src->bo->size);
533 memmove(mdst, msrc, size);
534 msrc += src->pitch; mdst += dst->pitch;
535 }
536 }
537 }
538 else
539 {
540 /* copy backwards so we don't destroy data we have to read yet */
541 if(msrc + size <= mdst)
542 {
543 for(int iy = h - 1; iy >= 0; --iy)
544 {
545 assert(mdst + size <= (uint8_t*)dst->bo->map + dst->bo->size);
546 assert(msrc + size <= (uint8_t*)src->bo->map + src->bo->size);
547 memcpy(mdst, msrc, size);
548 msrc += src->pitch; mdst += dst->pitch;
549 }
550 }
551 else
552 {
553 for(int iy = h - 1; iy >= 0; --iy)
554 {
555 assert(mdst + size <= (uint8_t*)dst->bo->map + dst->bo->size);
556 assert(msrc + size <= (uint8_t*)src->bo->map + src->bo->size);
557 memmove(mdst, msrc, size);
558 msrc += src->pitch; mdst += dst->pitch;
559 }
560 }
561 }
562 }
563 else
564 {
565 int* dswx = NULL;
566 int* dswy = NULL;
567 int* sswx = NULL;
568 int* sswy = NULL;
569 int dir;
570
571 if(!dst->pitch)
572 {
573 dswx = alloca(w * sizeof(int));
574 for(int ix = 0; ix < w; ++ix) // we are adding, so z cannot be contributed by both
575 dswx[ix] = nv04_swizzle_bits(dst->x + ix, 0, 0, dst->w, dst->h, dst->d);
576 dswy = alloca(h * sizeof(int));
577 for(int iy = 0; iy < h; ++iy)
578 dswy[iy] = nv04_swizzle_bits(0, dst->y + iy, dst->z, dst->w, dst->h, dst->d);
579 }
580
581 if(!src->pitch)
582 {
583 sswx = alloca(w * sizeof(int));
584 for(int ix = 0; ix < w; ++ix)
585 sswx[ix] = nv04_swizzle_bits(src->x + ix, 0, 0, src->w, src->h, src->d);
586 sswy = alloca(h * sizeof(int));
587 for(int iy = 0; iy < h; ++iy)
588 sswy[iy] = nv04_swizzle_bits(0, src->y + iy, src->z, src->w, src->h, src->d);
589 }
590
591 dir = 1;
592 /* do backwards copies for overlapping swizzled surfaces */
593 if(dst->pitch == src->pitch && dst->offset == src->offset)
594 {
595 if(dst->y > src->y || (dst->y == src->y && dst->x > src->x))
596 dir = -1;
597 }
598
599#define SWIZZLED_COPY_LOOPS
600 if(dir == 1)
601 {
602 int dir = 1;
603#define LOOP_Y for(int iy = 0; iy < h; ++iy)
604#define LOOP_X for(int ix = 0; ix < w; ++ix)
605#include "nv04_2d_loops.h"
606#undef LOOP_X
607#undef LOOP_Y
608 }
609 else
610 {
611 int dir = -1;
612#define LOOP_Y for(int iy = h - 1; iy >= 0; --iy)
613#define LOOP_X for(int ix = w - 1; ix >= 0; --ix)
614#include "nv04_2d_loops.h"
615#undef LOOP_X
616#undef LOOP_Y
617 }
618#undef SWIZZLED_COPY_LOOP
619 }
620
621 if(src->bo != dst->bo)
622 nouveau_bo_unmap(src->bo);
623 nouveau_bo_unmap(dst->bo);
624}
625
626/* TODO: if the destination is swizzled, we are doing random writes, which causes write combining to fail
627 * the alternative is to read, modify and copy back, which may or may not be faster
628 * loading 3D textures is a common case that hits this and could probably benefit from the temporary
629 */
630void
631nv04_region_fill_cpu(struct nv04_region* dst, int w, int h, unsigned value)
632{
633 uint8_t* mdst = (nouveau_bo_map(dst->bo, NOUVEAU_BO_WR), (uint8_t*)dst->bo->map + dst->offset);
634
635#ifdef NV04_REGION_DEBUG
636 fprintf(stderr, "\tRGN_FILL_CPU ");
637 nv04_region_print(dst);
638 fprintf(stderr, "\n");
639#endif
640
641 nv04_region_assert(dst, w, h);
642
643 if(dst->pitch)
644 {
645 unsigned size = w << dst->bpps;
646
647#define FILL(T) do { \
648 for(int iy = 0; iy < h; ++iy) \
649 { \
650 assert((char*)((T*)mdst + w) <= (char*)dst->bo->map + dst->bo->size); \
651 for(int ix = 0; ix < w; ++ix) \
652 ((T*)mdst)[ix] = (T)value; \
653 mdst += dst->pitch; \
654 } \
655 } while(0)
656
657 mdst += dst->y * dst->pitch + (dst->x << dst->bpps);
658
659 if(dst->bpps == 0)
660 {
661ms:
662 assert(mdst + size * h <= (uint8_t*)dst->bo->map + dst->bo->size);
663 if(size == dst->pitch)
664 memset(mdst, (uint8_t)value, size * h);
665 else
666 {
667 for(int iy = 0; iy < h; ++iy)
668 {
669 assert(mdst + size <= (uint8_t*)dst->bo->map + dst->bo->size);
670 memset(mdst, (uint8_t)value, size);
671 mdst += dst->pitch;
672 }
673 }
674 }
675 else if(dst->bpps == 1)
676 {
677 if(!((uint8_t)value ^ (uint8_t)(value >> 8)))
678 goto ms;
679
680 FILL(uint16_t);
681 }
682 else if(dst->bpps == 2)
683 {
684 if(value == (uint8_t)value * 0x1010101)
685 goto ms;
686 FILL(uint32_t);
687 }
688 else
689 assert(0);
690#undef FILL
691 }
692 else
693 {
694 int* dswx;
695 int* dswy;
696
697 dswx = alloca(w * sizeof(int));
698 for(int ix = 0; ix < w; ++ix)
699 dswx[ix] = nv04_swizzle_bits(dst->x + ix, 0, dst->z, dst->w, dst->h, dst->d);
700 dswy = alloca(h * sizeof(int));
701 for(int iy = 0; iy < h; ++iy)
702 dswy[iy] = nv04_swizzle_bits(0, dst->y + iy, dst->z, dst->w, dst->h, dst->d);
703
704#define FILL(T) do { \
705 T tvalue = (T)value; \
706 for(int iy = 0; iy < h; ++iy) \
707 { \
708 T* pdst = (T*)mdst + dswy[iy]; \
709 for(int ix = 0; ix < w; ++ix) \
710 { \
711 assert((uint8_t*)&pdst[dswx[ix] + 1] <= (uint8_t*)dst->bo->map + dst->bo->size); \
712 pdst[dswx[ix]] = tvalue; \
713 } \
714 } \
715 } while(0)
716
717 if(dst->bpps == 0)
718 FILL(uint8_t);
719 else if(dst->bpps == 1)
720 FILL(uint16_t);
721 else if(dst->bpps == 2)
722 FILL(uint32_t);
723 else
724 assert(0 && "unhandled bpp");
725#undef FILL
726 }
727
728 nouveau_bo_unmap(dst->bo);
729}
730
731static inline int
732nv04_region_cs2d_format(struct nv04_region* rgn)
733{
734 switch(rgn->bpps) {
735 case 0:
736 return NV04_CONTEXT_SURFACES_2D_FORMAT_Y8;
737 case 1:
738 if(rgn->one_bits >= 1)
739 return NV04_CONTEXT_SURFACES_2D_FORMAT_X1R5G5B5_X1R5G5B5;
740 else
741 return NV04_CONTEXT_SURFACES_2D_FORMAT_R5G6B5;
742 case 2:
743 if(rgn->one_bits >= 8)
744 return NV04_CONTEXT_SURFACES_2D_FORMAT_X8R8G8B8_X8R8G8B8;
745 else
746 return NV04_CONTEXT_SURFACES_2D_FORMAT_A8R8G8B8;
747 default:
748 return -1;
749 }
750}
751
752static inline int
753nv04_region_sifm_format(struct nv04_region* rgn)
754{
755 switch(rgn->bpps) {
756 case 0:
757 return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_Y8;
758 case 1:
759 if(rgn->one_bits >= 1)
760 return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X1R5G5B5;
761 else
762 return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_R5G6B5;
763 case 2:
764 if(rgn->one_bits >= 8)
765 return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X8R8G8B8;
766 else
767 return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A8R8G8B8;
768 default:
769 return -1;
770 }
771}
772static void
773nv04_region_copy_swizzle(struct nv04_2d_context *ctx,
774 struct nv04_region* dst,
775 struct nv04_region* src,
776 int w, int h)
777{
778 struct nouveau_channel *chan = ctx->swzsurf->channel;
779 struct nouveau_grobj *swzsurf = ctx->swzsurf;
780 struct nouveau_grobj *sifm = ctx->sifm;
781 int cs2d_format = nv04_region_cs2d_format(dst);
782 int sifm_format = nv04_region_sifm_format(src);
783 /* Max width & height may not be the same on all HW, but must be POT */
784 unsigned max_shift = 10;
785 unsigned cw = 1 << max_shift;
786 unsigned ch = 1 << max_shift;
787 unsigned sx = dst->x >> max_shift;
788 unsigned sy = dst->y >> max_shift;
789 unsigned ex = (dst->x + w - 1) >> max_shift;
790 unsigned ey = (dst->y + h - 1) >> max_shift;
791 unsigned chunks = (ex - sx + 1) * (ey - sy + 1);
792 unsigned chunk_size;
793 if(dst->w < cw)
794 cw = dst->w;
795 if(dst->h < ch)
796 ch = dst->h;
797 chunk_size = cw * ch << dst->bpps;
798
799#ifdef NV04_REGION_DEBUG
800 fprintf(stderr, "\tRGN_COPY_SWIZZLE [%i, %i: %i] ", w, h, dst->bpps);
801 for(int i = 0; i < 2; ++i)
802 {
803 nv04_region_print(i ? src : dst);
804 fprintf(stderr, i ? "\n" : " <- ");
805 }
806#endif
807
808 nv04_region_assert(dst, w, h);
809 nv04_region_assert(src, w, h);
810
811 MARK_RING (chan, 8 + chunks * 17, 2 + chunks * 2);
812
813 BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_DMA_IMAGE, 1);
814 OUT_RELOCo(chan, dst->bo,
815 NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
816
817 BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_FORMAT, 1);
818 OUT_RING (chan, cs2d_format |
819 log2i(cw) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U__SHIFT |
820 log2i(ch) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V__SHIFT);
821
822 BEGIN_RING(chan, sifm, NV03_SCALED_IMAGE_FROM_MEMORY_DMA_IMAGE, 1);
823 OUT_RELOCo(chan, src->bo,
824 NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
825 BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_SURFACE, 1);
826 OUT_RING (chan, swzsurf->handle);
827
828 assert(!(dst->offset & 63));
829
830 for (int cy = sy; cy <= ey; ++cy) {
831 int ry = MAX2(0, (int)(dst->y - ch * cy));
832 int rh = MIN2((int)ch, (int)(dst->y - ch * cy + h)) - ry;
833 for (int cx = sx; cx <= ex; ++cx) {
834 int rx = MAX2(0, (int)(dst->x - cw * cx));
835 int rw = MIN2((int)cw, (int)(dst->x - cw * cx + w)) - rx;
836 unsigned dst_offset;
837 unsigned src_offset;
838
839 BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_OFFSET, 1);
840
841 dst_offset = dst->offset + (nv04_swizzle_bits_2d(cx * cw, cy * ch, dst->w, dst->h) << dst->bpps);
842 assert(dst_offset <= dst->bo->size);
843 assert(dst_offset + chunk_size <= dst->bo->size);
844 OUT_RELOCl(chan, dst->bo, dst_offset,
845 NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
846
847 BEGIN_RING(chan, sifm, NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION, 9);
848 OUT_RING (chan, NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_TRUNCATE);
849 OUT_RING (chan, sifm_format);
850 OUT_RING (chan, NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY);
851 OUT_RING (chan, rx | (ry << NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_Y__SHIFT));
852 OUT_RING (chan, rh << NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_H__SHIFT | rw);
853 OUT_RING (chan, rx | (ry << NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_Y__SHIFT));
854 OUT_RING (chan, rh << NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_H__SHIFT | rw);
855 OUT_RING (chan, 1 << 20);
856 OUT_RING (chan, 1 << 20);
857
858 BEGIN_RING(chan, sifm, NV03_SCALED_IMAGE_FROM_MEMORY_SIZE, 4);
859 OUT_RING (chan, rh << NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_H__SHIFT | align(rw, 8));
860 OUT_RING (chan, src->pitch |
861 NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CENTER |
862 NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_POINT_SAMPLE);
863 src_offset = src->offset + (cy * ch + ry + src->y - dst->y) * src->pitch + ((cx * cw + rx + src->x - dst->x) << src->bpps);
864 assert(src_offset <= src->bo->size);
865 assert(src_offset + (src->pitch * (rh - 1)) + (rw << src->bpps) <= src->bo->size);
866 OUT_RELOCl(chan, src->bo, src_offset,
867 NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
868 OUT_RING (chan, 0);
869 }
870 }
871}
872
873static inline void
874nv04_copy_m2mf_begin(struct nv04_2d_context *ctx, struct nouveau_bo* dstbo, struct nouveau_bo* srcbo, unsigned commands)
875{
876 struct nouveau_channel *chan = ctx->m2mf->channel;
877 struct nouveau_grobj *m2mf = ctx->m2mf;
878 MARK_RING (chan, 3 + commands * 9, 2 + commands * 2);
879 BEGIN_RING(chan, m2mf, NV04_M2MF_DMA_BUFFER_IN, 2);
880 OUT_RELOCo(chan, srcbo,
881 NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
882 OUT_RELOCo(chan, dstbo,
883 NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
884}
885
886static inline void
887nv04_copy_m2mf_body(struct nv04_2d_context *ctx, struct nouveau_bo* dstbo, int* pdstoff, unsigned dstpitch, struct nouveau_bo* srcbo, int* psrcoff, unsigned srcpitch, unsigned size, unsigned lines)
888{
889 struct nouveau_channel *chan = ctx->m2mf->channel;
890 struct nouveau_grobj *m2mf = ctx->m2mf;
891
892#ifdef NV04_REGION_DEBUG
893 fprintf(stderr, "\t\t\tCOPY_M2MF_BODY [%i, %i] <%i[%u]> lin %u <- <%i[%u]> lin %u\n", size, lines, dstbo->handle, *pdstoff, dstpitch, srcbo->handle, *psrcoff, srcpitch);
894#endif
895
896 BEGIN_RING(chan, m2mf, NV04_M2MF_OFFSET_IN, 8);
897 OUT_RELOCl(chan, srcbo, *psrcoff,
898 NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD);
899 OUT_RELOCl(chan, dstbo, *pdstoff,
900 NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_WR);
901 OUT_RING (chan, srcpitch);
902 OUT_RING (chan, dstpitch);
903 OUT_RING (chan, size);
904 OUT_RING (chan, lines);
905 OUT_RING (chan, 0x0101);
906 OUT_RING (chan, 0);
907
908 *psrcoff += srcpitch * lines;
909 *pdstoff += dstpitch * lines;
910}
911
912static void
913nv04_copy_m2mf(struct nv04_2d_context *ctx,
914 struct nouveau_bo* dstbo, int dstoff, unsigned dstpitch,
915 struct nouveau_bo* srcbo, int srcoff, unsigned srcpitch,
916 unsigned size, unsigned h)
917{
918 unsigned max_pitch = 32767;
919 unsigned max_lines = 2047;
920
921#ifdef NV04_REGION_DEBUG
922 fprintf(stderr, "\t\tCOPY_M2MF [%i, %i] <%i[%i]> lin %u <- <%i[%i]> lin %u\n", size, h, dstbo->handle, dstoff, dstpitch, srcbo->handle, srcoff, srcpitch);
923#endif
924
925 if(srcpitch <= max_pitch && dstpitch <= max_pitch)
926 {
927 unsigned full_pages = h / max_lines;
928 unsigned leftover_lines = h - full_pages * max_lines;
929
930 nv04_copy_m2mf_begin(ctx, dstbo, srcbo, full_pages + !!leftover_lines);
931
932 for(unsigned i = 0; i < full_pages; ++i)
933 nv04_copy_m2mf_body(ctx, dstbo, &dstoff, dstpitch, srcbo, &srcoff, srcpitch, size, max_lines);
934
935 if(leftover_lines)
936 nv04_copy_m2mf_body(ctx, dstbo, &dstoff, dstpitch, srcbo, &srcoff, srcpitch, size, leftover_lines);
937 }
938 else
939 {
940 unsigned lines = size / max_pitch;
941 unsigned leftover = size - lines * max_pitch;
942 unsigned full_pages = lines / max_lines;
943 unsigned leftover_lines = lines - full_pages * max_lines;
944 unsigned srcgap = srcpitch - size;
945 unsigned dstgap = dstpitch - size;
946
947 nv04_copy_m2mf_begin(ctx, dstbo, srcbo, h * (full_pages + !!leftover_lines + !!leftover));
948
949 for(unsigned i = 0; i < h; ++i)
950 {
951 for(unsigned j = 0; j < full_pages; ++j)
952 nv04_copy_m2mf_body(ctx, dstbo, &dstoff, max_pitch, srcbo, &srcoff, max_pitch, max_pitch, max_lines);
953
954 if(leftover_lines)
955 nv04_copy_m2mf_body(ctx, dstbo, &dstoff, max_pitch, srcbo, &srcoff, max_pitch, max_pitch, leftover_lines);
956
957 if(leftover)
958 nv04_copy_m2mf_body(ctx, dstbo, &dstoff, leftover, srcbo, &srcoff, leftover, leftover, 1);
959
960 srcoff += srcgap;
961 dstoff += dstgap;
962 }
963 }
964}
965
966void
967nv04_memcpy(struct nv04_2d_context *ctx, struct nouveau_bo* dstbo, int dstoff, struct nouveau_bo* srcbo, int srcoff, unsigned size)
968{
969#ifdef NV04_REGION_DEBUG
970 fprintf(stderr, "\tMEMCPY [%i] <%i[%i]> <- <%i[%i]>\n", size, dstbo->handle, dstoff, srcbo->handle, srcoff);
971#endif
972
973 nv04_copy_m2mf(ctx, dstbo, dstoff, size, srcbo, srcoff, size, size, 1);
974}
975
976static void
977nv04_region_copy_m2mf(struct nv04_2d_context *ctx, struct nv04_region *dst, struct nv04_region *src, int w, int h)
978{
979#ifdef NV04_REGION_DEBUG
980 fprintf(stderr, "\tRGN_COPY_M2MF [%i, %i: %i] ", w, h, dst->bpps);
981 for(int i = 0; i < 2; ++i)
982 {
983 nv04_region_print(i ? src : dst);
984 fprintf(stderr, i ? "\n" : " <- ");
985 }
986#endif
987
988 nv04_region_assert(dst, w, h);
989 nv04_region_assert(src, w, h);
990 assert(src->pitch);
991 assert(dst->pitch);
992
993 nv04_copy_m2mf(ctx,
994 dst->bo, dst->offset + dst->y * dst->pitch + (dst->x << dst->bpps), dst->pitch,
995 src->bo, src->offset + src->y * src->pitch + (src->x << src->bpps), src->pitch,
996 w << src->bpps, h);
997}
998
999static inline void
1000nv04_region_copy_blit(struct nv04_2d_context *ctx, struct nv04_region* dst, struct nv04_region* src, int w, int h)
1001{
1002 struct nouveau_channel *chan = ctx->surf2d->channel;
1003 struct nouveau_grobj *surf2d = ctx->surf2d;
1004 struct nouveau_grobj *blit = ctx->blit;
1005 int cs2d_format = nv04_region_cs2d_format(dst);
1006
1007#ifdef NV04_REGION_DEBUG
1008 fprintf(stderr, "\tRGN_COPY_BLIT [%i, %i: %i] ", w, h, dst->bpps);
1009 for(int i = 0; i < 2; ++i)
1010 {
1011 nv04_region_print(i ? src : dst);
1012 fprintf(stderr, i ? "\n" : " <- ");
1013 }
1014#endif
1015
1016 assert(!(src->pitch & 63) && src->pitch);
1017 assert(!(dst->pitch & 63) && dst->pitch);
1018 nv04_region_assert(dst, w, h);
1019 nv04_region_assert(src, w, h);
1020
1021 MARK_RING (chan, 12, 4);
1022 BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
1023 OUT_RELOCo(chan, src->bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
1024 OUT_RELOCo(chan, dst->bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
1025 BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_FORMAT, 4);
1026 OUT_RING (chan, cs2d_format);
1027 OUT_RING (chan, (dst->pitch << 16) | src->pitch);
1028 OUT_RELOCl(chan, src->bo, src->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
1029 OUT_RELOCl(chan, dst->bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
1030
1031 BEGIN_RING(chan, blit, 0x0300, 3);
1032 OUT_RING (chan, (src->y << 16) | src->x);
1033 OUT_RING (chan, (dst->y << 16) | dst->x);
1034 OUT_RING (chan, ( h << 16) | w);
1035}
1036
1037/* THEOREM: a non-linearizable swizzled destination is always 64 byte aligned, except for 4x2 mipmap levels of swizzled 1bpp surfaces
1038 * HYPOTESIS:
1039 * 1. The first mipmap level is 64-byte-aligned
1040 * PROOF:
1041 * 1. Thus, all mipmaps level with a parent which is 64-byte or more in size are.
1042 * 2. At 1bpp, the smallest levels with a <= 32-byte parent are either Nx1 or 1xN or size <=8, thus 4x2, 2x2 or 2x4
1043 * 3. Nx1, 1xN, 2x4, 2x2 have all subrects linearizable. 4x2 does not.
1044 * 4. At 2/4bpp or more, the smallest levels with a 32-byte parent are 1xN, Nx1 or 2x2
1045 *
1046 * However, nv04_region_align handles that.
1047 */
1048
1049// 0 -> done, 1 -> do with 3D engine or CPU, -1 -> do with CPU
1050// dst and src may be modified, and the possibly modified version should be passed to nv04_region_cpu if necessary
1051int
1052nv04_region_copy_2d(struct nv04_2d_context *ctx, struct nv04_region* dst, struct nv04_region* src,
1053 int w, int h, int dst_to_gpu, int src_on_gpu)
1054{
1055 assert(src->bpps == dst->bpps);
1056
1057#ifdef NV04_REGION_DEBUG
1058 fprintf(stderr, "RGN_COPY [%i, %i: %i] ", w, h, dst->bpps);
1059 for(int i = 0; i < 2; ++i)
1060 {
1061 int gpu = i ? src_on_gpu : dst_to_gpu;
1062 nv04_region_print(i ? src : dst);
1063 fprintf(stderr, " %s", gpu ? "gpu" : "cpu");
1064 fprintf(stderr, i ? "\n" : " <- ");
1065 }
1066#endif
1067
1068 // if they are contiguous and either both swizzled or both linear, reshape
1069 if(!dst->pitch == !src->pitch
1070 && nv04_region_is_contiguous(dst, w, h)
1071 && nv04_region_is_contiguous(src, w, h))
1072 {
1073 nv04_region_contiguous_shape(dst, &w, &h, 6);
1074 nv04_region_linearize_contiguous(dst, w, h);
1075 nv04_region_linearize_contiguous(src, w, h);
1076 }
1077
1078#ifdef NV04_REGION_DEBUG
1079 fprintf(stderr, "\tOPT ");
1080 for(int i = 0; i < 2; ++i)
1081 {
1082 nv04_region_print(i ? src : dst);
1083 fprintf(stderr, i ? "\n" : " <- ");
1084 }
1085#endif
1086
1087 /* if the destination is not for GPU _and_ source is on CPU, use CPU */
1088 /* if the destination is not for GPU _or_ source is on CPU, use CPU only if we think it's faster than the GPU */
1089 /* TODO: benchmark to find out in which cases exactly we should prefer the CPU */
1090 if((!dst_to_gpu && !src_on_gpu)
1091 || (!dst->pitch && dst->d > 1)
1092 /* 3D swizzled destination are unwritable by the GPU, and 2D swizzled ones are readable only by the 3D engine */
1093 )
1094 return -1;
1095 /* there is no known way to read 2D/3D-swizzled surfaces with the 2D engine
1096 * ask the caller to use the 3D engine
1097 * If a format cannot be sampled from the 3D engine there is no point in making it swizzled, so we must not do so
1098 */
1099 else if(!src->pitch)
1100 {
1101#ifdef NV04_REGION_DEBUG
1102 fprintf(stderr, "\tCOPY_ENG3D\n");
1103#endif
1104 return 1;
1105 }
1106 /* Setup transfer to swizzle the texture to vram if needed */
1107 else
1108 {
1109 if (!dst->pitch)
1110 {
1111 if(!dst_to_gpu)
1112 {
1113#ifdef NV04_REGION_DEBUG
1114 fprintf(stderr, "\tCOPY_ENG3D\n");
1115#endif
1116 return 1;
1117 }
1118 else
1119 {
1120 assert(!nv04_region_align(dst, w, h, 6));
1121
1122 nv04_region_copy_swizzle(ctx, dst, src, w, h);
1123 return 0;
1124 }
1125 }
1126 else
1127 {
1128 /* NV_CONTEXT_SURFACES_2D has buffer alignment restrictions, fallback
1129 * to NV_M2MF in this case.
1130 * TODO: is this also true for the source? possibly not
1131 * TODO: should we just always use m2mf?
1132 * TODO: if not, add support for multiple operations to copy_blit
1133 */
1134
1135 if (!dst_to_gpu
1136 || w > 2047
1137 || h > 2047
1138 || (w & 1)
1139 || nv04_region_align(src, w, h, 6)
1140 || nv04_region_align(dst, w, h, 6)
1141 )
1142 nv04_region_copy_m2mf(ctx, dst, src, w, h);
1143 else
1144 nv04_region_copy_blit(ctx, dst, src, w, h);
1145
1146 return 0;
1147 }
1148 }
1149}
1150
1151static inline void
1152nv04_region_fill_gdirect(struct nv04_2d_context *ctx, struct nv04_region* dst, int w, int h, unsigned value)
1153{
1154 struct nouveau_channel *chan = ctx->surf2d->channel;
1155 struct nouveau_grobj *surf2d = ctx->surf2d;
1156 struct nouveau_grobj *rect = ctx->rect;
1157 int cs2d_format, gdirect_format;
1158
1159#ifdef NV04_REGION_DEBUG
1160 fprintf(stderr, "\tFILL_GDIRECT\n");
1161#endif
1162
1163 assert(!(dst->pitch & 63) && dst->pitch);
1164 nv04_region_assert(dst, w, h);
1165
1166 switch(dst->bpps)
1167 {
1168 case 0:
1169 gdirect_format = NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8;
1170 cs2d_format = NV04_CONTEXT_SURFACES_2D_FORMAT_Y8;
1171 break;
1172 case 1:
1173 gdirect_format = NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A16R5G6B5;
1174 cs2d_format = NV04_CONTEXT_SURFACES_2D_FORMAT_Y16;
1175 break;
1176 case 2:
1177 gdirect_format = NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8;
1178 cs2d_format = NV04_CONTEXT_SURFACES_2D_FORMAT_Y32;
1179 break;
1180 default:
1181 assert(0);
1182 gdirect_format = 0;
1183 cs2d_format = 0;
1184 break;
1185 }
1186
1187 MARK_RING (chan, 15, 4);
1188 BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
1189 OUT_RELOCo(chan, dst->bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
1190 OUT_RELOCo(chan, dst->bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
1191 BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_FORMAT, 4);
1192 OUT_RING (chan, cs2d_format);
1193 OUT_RING (chan, (dst->pitch << 16) | dst->pitch);
1194 OUT_RELOCl(chan, dst->bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
1195 OUT_RELOCl(chan, dst->bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
1196
1197 BEGIN_RING(chan, rect, NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT, 1);
1198 OUT_RING (chan, gdirect_format);
1199 BEGIN_RING(chan, rect, NV04_GDI_RECTANGLE_TEXT_COLOR1_A, 1);
1200 OUT_RING (chan, value);
1201 BEGIN_RING(chan, rect, NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT(0), 2);
1202 OUT_RING (chan, (dst->x << 16) | dst->y);
1203 OUT_RING (chan, ( w << 16) | h);
1204}
1205
1206int
1207nv04_region_fill_2d(struct nv04_2d_context *ctx, struct nv04_region *dst,
1208 int w, int h, unsigned value)
1209{
1210 if(!w || !h)
1211 return 0;
1212
1213#ifdef NV04_REGION_DEBUG
1214 fprintf(stderr, "FILL [%i, %i: %i] ", w, h, dst->bpps);
1215 nv04_region_print(dst);
1216 fprintf(stderr, " <- 0x%x\n", value);
1217#endif
1218
1219 if(nv04_region_is_contiguous(dst, w, h))
1220 {
1221 nv04_region_contiguous_shape(dst, &w, &h, 6);
1222 nv04_region_linearize_contiguous(dst, w, h);
1223 }
1224
1225 // TODO: maybe do intermediate copies for some cases instead of using the 3D engine/CPU
1226 /* GdiRect doesn't work together with swzsurf, so the 3D engine, or an intermediate copy, is the only option here */
1227 if(!dst->pitch)
1228 {
1229#ifdef NV04_REGION_DEBUG
1230 fprintf(stderr, "\tFILL_ENG3D\n");
1231#endif
1232 return 1;
1233 }
1234 else if(!nv04_region_align(dst, w, h, 6))
1235 {
1236 nv04_region_fill_gdirect(ctx, dst, w, h, value);
1237 return 0;
1238 }
1239 else
1240 return -1;
1241}
1242
1243
1244void
1245nv04_2d_context_takedown(struct nv04_2d_context *ctx)
1246{
1247 nouveau_notifier_free(&ctx->ntfy);
1248 nouveau_grobj_free(&ctx->m2mf);
1249 nouveau_grobj_free(&ctx->surf2d);
1250 nouveau_grobj_free(&ctx->swzsurf);
1251 nouveau_grobj_free(&ctx->rect);
1252 nouveau_grobj_free(&ctx->blit);
1253 nouveau_grobj_free(&ctx->sifm);
1254
1255 free(ctx);
1256}
1257
1258struct nv04_2d_context *
1259nv04_2d_context_init(struct nouveau_channel* chan)
1260{
1261 struct nv04_2d_context *ctx = calloc(1, sizeof(struct nv04_2d_context));
1262 unsigned handle = 0x88000000, class;
1263 int ret;
1264
1265 if (!ctx)
1266 return NULL;
1267
1268 ret = nouveau_notifier_alloc(chan, handle++, 1, &ctx->ntfy);
1269 if (ret) {
1270 nv04_2d_context_takedown(ctx);
1271 return NULL;
1272 }
1273
1274 ret = nouveau_grobj_alloc(chan, handle++, 0x0039, &ctx->m2mf);
1275 if (ret) {
1276 nv04_2d_context_takedown(ctx);
1277 return NULL;
1278 }
1279
1280 BEGIN_RING(chan, ctx->m2mf, NV04_M2MF_DMA_NOTIFY, 1);
1281 OUT_RING (chan, ctx->ntfy->handle);
1282
1283 if (chan->device->chipset < 0x10)
1284 class = NV04_CONTEXT_SURFACES_2D;
1285 else
1286 class = NV10_CONTEXT_SURFACES_2D;
1287
1288 ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->surf2d);
1289 if (ret) {
1290 nv04_2d_context_takedown(ctx);
1291 return NULL;
1292 }
1293
1294 BEGIN_RING(chan, ctx->surf2d,
1295 NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
1296 OUT_RING (chan, chan->vram->handle);
1297 OUT_RING (chan, chan->vram->handle);
1298
1299 if (chan->device->chipset < 0x10)
1300 class = NV04_IMAGE_BLIT;
1301 else
1302 class = NV11_IMAGE_BLIT;
1303
1304 ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->blit);
1305 if (ret) {
1306 nv04_2d_context_takedown(ctx);
1307 return NULL;
1308 }
1309
1310 BEGIN_RING(chan, ctx->blit, NV01_IMAGE_BLIT_DMA_NOTIFY, 1);
1311 OUT_RING (chan, ctx->ntfy->handle);
1312 BEGIN_RING(chan, ctx->blit, NV04_IMAGE_BLIT_SURFACES, 1);
1313 OUT_RING (chan, ctx->surf2d->handle);
1314 BEGIN_RING(chan, ctx->blit, NV01_IMAGE_BLIT_OPERATION, 1);
1315 OUT_RING (chan, NV01_IMAGE_BLIT_OPERATION_SRCCOPY);
1316
1317 ret = nouveau_grobj_alloc(chan, handle++, NV04_GDI_RECTANGLE_TEXT,
1318 &ctx->rect);
1319 if (ret) {
1320 nv04_2d_context_takedown(ctx);
1321 return NULL;
1322 }
1323
1324 BEGIN_RING(chan, ctx->rect, NV04_GDI_RECTANGLE_TEXT_DMA_NOTIFY, 1);
1325 OUT_RING (chan, ctx->ntfy->handle);
1326 BEGIN_RING(chan, ctx->rect, NV04_GDI_RECTANGLE_TEXT_SURFACE, 1);
1327 OUT_RING (chan, ctx->surf2d->handle);
1328 BEGIN_RING(chan, ctx->rect, NV04_GDI_RECTANGLE_TEXT_OPERATION, 1);
1329 OUT_RING (chan, NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY);
1330 BEGIN_RING(chan, ctx->rect,
1331 NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT, 1);
1332 OUT_RING (chan, NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT_LE);
1333
1334 switch (chan->device->chipset & 0xf0) {
1335 case 0x00:
1336 case 0x10:
1337 class = NV04_SWIZZLED_SURFACE;
1338 break;
1339 case 0x20:
1340 class = NV11_SWIZZLED_SURFACE;
1341 break;
1342 case 0x30:
1343 class = NV30_SWIZZLED_SURFACE;
1344 break;
1345 case 0x40:
1346 case 0x60:
1347 class = NV40_SWIZZLED_SURFACE;
1348 break;
1349 default:
1350 /* Famous last words: this really can't happen.. */
1351 assert(0);
1352 break;
1353 }
1354
1355 ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->swzsurf);
1356 if (ret) {
1357 nv04_2d_context_takedown(ctx);
1358 return NULL;
1359 }
1360
1361 /* all the Gallium MARK_RING calculations assume no autobinding, so do that now */
1362 if(ctx->swzsurf->bound == NOUVEAU_GROBJ_UNBOUND)
1363 nouveau_grobj_autobind(ctx->swzsurf);
1364
1365 switch (chan->device->chipset & 0xf0) {
1366 case 0x10:
1367 case 0x20:
1368 class = NV10_SCALED_IMAGE_FROM_MEMORY;
1369 break;
1370 case 0x30:
1371 class = NV30_SCALED_IMAGE_FROM_MEMORY;
1372 break;
1373 case 0x40:
1374 case 0x60:
1375 class = NV40_SCALED_IMAGE_FROM_MEMORY;
1376 break;
1377 default:
1378 class = NV04_SCALED_IMAGE_FROM_MEMORY;
1379 break;
1380 }
1381
1382 ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->sifm);
1383 if (ret) {
1384 nv04_2d_context_takedown(ctx);
1385 return NULL;
1386 }
1387
1388 /* all the Gallium MARK_RING calculations assume no autobinding, so do that now */
1389 if(ctx->sifm->bound == NOUVEAU_GROBJ_UNBOUND)
1390 nouveau_grobj_autobind(ctx->sifm);
1391
1392 return ctx;
1393}
diff --git a/src/gallium/drivers/nvfx/nv04_2d.h b/src/gallium/drivers/nvfx/nv04_2d.h
deleted file mode 100644
index 00ee5bc0b23..00000000000
--- a/src/gallium/drivers/nvfx/nv04_2d.h
+++ /dev/null
@@ -1,107 +0,0 @@
1/**************************************************************************
2 *
3 * Copyright 2009 Ben Skeggs
4 * Copyright 2009 Younes Manton
5 * Copyright 2010 Luca Barbieri
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining
9 * a copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
18 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
19 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
20 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 * The above copyright notice and this permission notice (including the
26 * next paragraph) shall be included in all copies or substantial portions
27 * of the Software.
28 *
29 **************************************************************************/
30
31/* this code has no Mesa or Gallium dependency and can be reused in the classic Mesa driver or DDX */
32
33#ifndef __NV04_2D_H__
34#define __NV04_2D_H__
35
36struct nv04_2d_context;
37struct nouveau_channel;
38struct nouveau_bo;
39
40// NOTE: all functions taking this as a parameter will CLOBBER it (except for ->bo)
41struct nv04_region {
42 struct nouveau_bo* bo;
43 int offset;
44 unsigned pitch; // 0 -> swizzled
45 unsigned bpps; // bpp shift (0, 1, 2; 3, 4 for fp/compressed)
46 unsigned one_bits; // number of high bits read and written as ones (for "no-alpha" optimization)
47 unsigned x, y, z;
48 unsigned w, h, d;
49};
50
51static inline void
52nv04_region_try_to_linearize(struct nv04_region* rgn)
53{
54 assert(!rgn->pitch);
55
56 if(rgn->d <= 1)
57 {
58 if(rgn->h <= 1 || rgn->w <= 2)
59 rgn->pitch = rgn->w << rgn->bpps;
60 }
61 else
62 {
63 if(rgn->h <= 2 && rgn->w <= 2)
64 {
65 rgn->pitch = rgn->w << rgn->bpps;
66 rgn->offset += rgn->z * rgn->h * rgn->pitch;
67 }
68 }
69}
70
71void
72nv04_memcpy(struct nv04_2d_context *ctx,
73 struct nouveau_bo* dstbo, int dstoff,
74 struct nouveau_bo* srcbo, int srcoff,
75 unsigned size);
76
77unsigned
78nv04_region_begin(struct nv04_region* rgn, unsigned w, unsigned h);
79
80unsigned
81nv04_region_end(struct nv04_region* rgn, unsigned w, unsigned h);
82
83void
84nv04_2d_context_takedown(struct nv04_2d_context *pctx);
85
86struct nv04_2d_context *
87nv04_2d_context_init(struct nouveau_channel* chan);
88
89void
90nv04_region_copy_cpu(struct nv04_region* dst, struct nv04_region* src, int w, int h);
91
92void
93nv04_region_fill_cpu(struct nv04_region* dst, int w, int h, unsigned value);
94
95int
96nv04_region_copy_2d(struct nv04_2d_context *ctx,
97 struct nv04_region* dst, struct nv04_region* src,
98 int w, int h,
99 int dst_to_gpu, int src_on_gpu);
100
101int
102nv04_region_fill_2d(struct nv04_2d_context *ctx,
103 struct nv04_region *dst,
104 int w, int h,
105 unsigned value);
106
107#endif
diff --git a/src/gallium/drivers/nvfx/nv04_2d_loops.h b/src/gallium/drivers/nvfx/nv04_2d_loops.h
deleted file mode 100644
index 3a6787c0717..00000000000
--- a/src/gallium/drivers/nvfx/nv04_2d_loops.h
+++ /dev/null
@@ -1,70 +0,0 @@
1#ifndef T
2{
3 if(dst->bpps == 0)
4#define T uint8_t
5#include "nv04_2d_loops.h"
6#undef T
7 else if(dst->bpps == 1)
8#define T uint16_t
9#include "nv04_2d_loops.h"
10#undef T
11 else if(dst->bpps == 2)
12#define T uint32_t
13#include "nv04_2d_loops.h"
14#undef T
15 else
16 assert(0);
17}
18#else
19#ifdef SWIZZLED_COPY_LOOPS
20{
21 if(!dst->pitch)
22 {
23 if(!src->pitch)
24 {
25 LOOP_Y
26 {
27 T* pdst = (T*)mdst + dswy[iy];
28 T* psrc = (T*)msrc + sswy[iy];
29 LOOP_X
30 {
31 assert((char*)&psrc[sswx[ix] + 1] <= ((char*)src->bo->map + src->bo->size));
32 assert((char*)&pdst[dswx[ix] + 1] <= ((char*)dst->bo->map + dst->bo->size));
33 pdst[dswx[ix]] = psrc[sswx[ix]];
34 }
35 }
36 }
37 else
38 {
39 T* psrc = (T*)(msrc + ((dir > 0) ? src->y : (src->y + h - 1)) * src->pitch) + src->x;
40 LOOP_Y
41 {
42 T* pdst = (T*)mdst + dswy[iy];
43 LOOP_X
44 {
45 assert((char*)&psrc[ix + 1] <= ((char*)src->bo->map + src->bo->size));
46 assert((char*)&pdst[dswx[ix] + 1] <= ((char*)dst->bo->map + dst->bo->size));
47 pdst[dswx[ix]] = psrc[ix];
48 }
49 psrc = (T*)((char*)psrc + dir * src->pitch);
50 }
51 }
52 }
53 else
54 {
55 T* pdst = (T*)(mdst + ((dir > 0) ? dst->y : (dst->y + h - 1)) * dst->pitch) + dst->x;
56 LOOP_Y
57 {
58 T* psrc = (T*)msrc + sswy[iy];
59 LOOP_X
60 {
61 assert((char*)&psrc[sswx[ix] + 1] <= ((char*)src->bo->map + src->bo->size));
62 assert((char*)&pdst[ix + 1] <= ((char*)dst->bo->map + dst->bo->size));
63 pdst[ix] = psrc[sswx[ix]];
64 }
65 pdst = (T*)((char*)pdst + dir * dst->pitch);
66 }
67 }
68}
69#endif
70#endif
diff --git a/src/gallium/drivers/nvfx/nv30-40_3d.xml.h b/src/gallium/drivers/nvfx/nv30-40_3d.xml.h
deleted file mode 100644
index a705a6bd3f2..00000000000
--- a/src/gallium/drivers/nvfx/nv30-40_3d.xml.h
+++ /dev/null
@@ -1,2022 +0,0 @@
1#ifndef NV30_40_3D_XML
2#define NV30_40_3D_XML
3
4/* Autogenerated file, DO NOT EDIT manually!
5
6This file was generated by the rules-ng-ng headergen tool in this git repository:
7http://0x04.net/cgit/index.cgi/rules-ng-ng
8git clone git://0x04.net/rules-ng-ng
9
10The rules-ng-ng source files this header was generated from are:
11- nv30-40_3d.xml ( 31709 bytes, from 2010-09-05 08:00:50)
12- copyright.xml ( 6503 bytes, from 2010-04-10 23:15:50)
13- nv_3ddefs.xml ( 15391 bytes, from 2010-09-05 08:00:46)
14- nv_defs.xml ( 4437 bytes, from 2010-08-05 19:38:53)
15- nv_object.xml ( 10424 bytes, from 2010-08-05 19:38:53)
16- nvchipsets.xml ( 2824 bytes, from 2010-08-05 19:38:53)
17
18Copyright (C) 2006-2010 by the following authors:
19- Artur Huillet <arthur.huillet@free.fr> (ahuillet)
20- Ben Skeggs (darktama, darktama_)
21- B. R. <koala_br@users.sourceforge.net> (koala_br)
22- Carlos Martin <carlosmn@users.sf.net> (carlosmn)
23- Christoph Bumiller <e0425955@student.tuwien.ac.at> (calim, chrisbmr)
24- Dawid Gajownik <gajownik@users.sf.net> (gajownik)
25- Dmitry Baryshkov
26- Dmitry Eremin-Solenikov <lumag@users.sf.net> (lumag)
27- EdB <edb_@users.sf.net> (edb_)
28- Erik Waling <erikwailing@users.sf.net> (erikwaling)
29- Francisco Jerez <currojerez@riseup.net> (curro, curro_, currojerez)
30- imirkin <imirkin@users.sf.net> (imirkin)
31- jb17bsome <jb17bsome@bellsouth.net> (jb17bsome)
32- Jeremy Kolb <kjeremy@users.sf.net> (kjeremy)
33- Laurent Carlier <lordheavym@gmail.com> (lordheavy)
34- Luca Barbieri <luca@luca-barbieri.com> (lb, lb1)
35- Maarten Maathuis <madman2003@gmail.com> (stillunknown)
36- Marcin Kościelnicki <koriakin@0x04.net> (mwk, koriakin)
37- Mark Carey <mark.carey@gmail.com> (careym)
38- Matthieu Castet <matthieu.castet@parrot.com> (mat-c)
39- nvidiaman <nvidiaman@users.sf.net> (nvidiaman)
40- Patrice Mandin <mandin.patrice@orange.fr> (pmandin, pmdata)
41- Pekka Paalanen <pq@iki.fi> (pq, ppaalanen)
42- Peter Popov <ironpeter@users.sf.net> (ironpeter)
43- Richard Hughes <hughsient@users.sf.net> (hughsient)
44- Rudi Cilibrasi <cilibrar@users.sf.net> (cilibrar)
45- Serge Martin
46- Simon Raffeiner
47- Stephane Loeuillet <leroutier@users.sf.net> (leroutier)
48- Stephane Marchesin <stephane.marchesin@gmail.com> (marcheu)
49- sturmflut <sturmflut@users.sf.net> (sturmflut)
50- Sylvain Munaut <tnt@246tNt.com>
51- Victor Stinner <victor.stinner@haypocalc.com> (haypo)
52- Wladmir van der Laan <laanwj@gmail.com> (miathan6)
53- Younes Manton <younes.m@gmail.com> (ymanton)
54
55Permission is hereby granted, free of charge, to any person obtaining
56a copy of this software and associated documentation files (the
57"Software"), to deal in the Software without restriction, including
58without limitation the rights to use, copy, modify, merge, publish,
59distribute, sublicense, and/or sell copies of the Software, and to
60permit persons to whom the Software is furnished to do so, subject to
61the following conditions:
62
63The above copyright notice and this permission notice (including the
64next paragraph) shall be included in all copies or substantial
65portions of the Software.
66
67THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
68EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
69MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
70IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
71LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
72OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
73WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
74*/
75
76
77
78#define NV30_3D_DMA_NOTIFY 0x00000180
79
80#define NV30_3D_DMA_TEXTURE0 0x00000184
81
82#define NV30_3D_DMA_TEXTURE1 0x00000188
83
84#define NV30_3D_DMA_COLOR1 0x0000018c
85
86#define NV30_3D_DMA_UNK190 0x00000190
87
88#define NV30_3D_DMA_COLOR0 0x00000194
89
90#define NV30_3D_DMA_ZETA 0x00000198
91
92#define NV30_3D_DMA_VTXBUF0 0x0000019c
93
94#define NV30_3D_DMA_VTXBUF1 0x000001a0
95
96#define NV30_3D_DMA_FENCE 0x000001a4
97
98#define NV30_3D_DMA_QUERY 0x000001a8
99
100#define NV30_3D_DMA_UNK1AC 0x000001ac
101
102#define NV30_3D_DMA_UNK1B0 0x000001b0
103
104#define NV40_3D_DMA_COLOR2 0x000001b4
105
106#define NV40_3D_DMA_COLOR3 0x000001b8
107
108#define NV30_3D_RT_HORIZ 0x00000200
109#define NV30_3D_RT_HORIZ_X__MASK 0x0000ffff
110#define NV30_3D_RT_HORIZ_X__SHIFT 0
111#define NV30_3D_RT_HORIZ_W__MASK 0xffff0000
112#define NV30_3D_RT_HORIZ_W__SHIFT 16
113
114#define NV30_3D_RT_VERT 0x00000204
115#define NV30_3D_RT_VERT_Y__MASK 0x0000ffff
116#define NV30_3D_RT_VERT_Y__SHIFT 0
117#define NV30_3D_RT_VERT_H__MASK 0xffff0000
118#define NV30_3D_RT_VERT_H__SHIFT 16
119
120#define NV30_3D_RT_FORMAT 0x00000208
121#define NV30_3D_RT_FORMAT_COLOR__MASK 0x0000001f
122#define NV30_3D_RT_FORMAT_COLOR__SHIFT 0
123#define NV30_3D_RT_FORMAT_COLOR_R5G6B5 0x00000003
124#define NV30_3D_RT_FORMAT_COLOR_X8R8G8B8 0x00000005
125#define NV30_3D_RT_FORMAT_COLOR_A8R8G8B8 0x00000008
126#define NV30_3D_RT_FORMAT_COLOR_B8 0x00000009
127#define NV30_3D_RT_FORMAT_COLOR_A16B16G16R16_FLOAT 0x0000000b
128#define NV30_3D_RT_FORMAT_COLOR_A32B32G32R32_FLOAT 0x0000000c
129#define NV30_3D_RT_FORMAT_COLOR_R32_FLOAT 0x0000000d
130#define NV30_3D_RT_FORMAT_COLOR_UNK0D 0x0000000d
131#define NV30_3D_RT_FORMAT_COLOR_X8B8G8R8 0x0000000f
132#define NV30_3D_RT_FORMAT_COLOR_A8B8G8R8 0x00000010
133#define NV30_3D_RT_FORMAT_ZETA__MASK 0x000000e0
134#define NV30_3D_RT_FORMAT_ZETA__SHIFT 5
135#define NV30_3D_RT_FORMAT_ZETA_Z16 0x00000020
136#define NV30_3D_RT_FORMAT_ZETA_Z24S8 0x00000040
137#define NV30_3D_RT_FORMAT_TYPE__MASK 0x00000f00
138#define NV30_3D_RT_FORMAT_TYPE__SHIFT 8
139#define NV30_3D_RT_FORMAT_TYPE_LINEAR 0x00000100
140#define NV30_3D_RT_FORMAT_TYPE_SWIZZLED 0x00000200
141#define NV30_3D_RT_FORMAT_LOG2_WIDTH__MASK 0x00ff0000
142#define NV30_3D_RT_FORMAT_LOG2_WIDTH__SHIFT 16
143#define NV30_3D_RT_FORMAT_LOG2_HEIGHT__MASK 0xff000000
144#define NV30_3D_RT_FORMAT_LOG2_HEIGHT__SHIFT 24
145
146#define NV30_3D_COLOR0_PITCH 0x0000020c
147#define NV30_3D_COLOR0_PITCH_COLOR0__MASK 0x0000ffff
148#define NV30_3D_COLOR0_PITCH_COLOR0__SHIFT 0
149#define NV30_3D_COLOR0_PITCH_ZETA__MASK 0xffff0000
150#define NV30_3D_COLOR0_PITCH_ZETA__SHIFT 16
151
152#define NV40_3D_COLOR0_PITCH 0x0000020c
153
154#define NV30_3D_COLOR0_OFFSET 0x00000210
155
156#define NV30_3D_ZETA_OFFSET 0x00000214
157
158#define NV30_3D_COLOR1_OFFSET 0x00000218
159
160#define NV30_3D_COLOR1_PITCH 0x0000021c
161
162#define NV30_3D_RT_ENABLE 0x00000220
163#define NV30_3D_RT_ENABLE_COLOR0 0x00000001
164#define NV30_3D_RT_ENABLE_COLOR1 0x00000002
165#define NV40_3D_RT_ENABLE_COLOR2 0x00000004
166#define NV40_3D_RT_ENABLE_COLOR3 0x00000008
167#define NV30_3D_RT_ENABLE_MRT 0x00000010
168
169#define NV40_3D_ZETA_PITCH 0x0000022c
170
171#define NV30_3D_LMA_DEPTH_PITCH 0x0000022c
172
173#define NV30_3D_LMA_DEPTH_OFFSET 0x00000230
174
175#define NV30_3D_TEX_UNITS_ENABLE 0x0000023c
176#define NV30_3D_TEX_UNITS_ENABLE_TX0 0x00000001
177#define NV30_3D_TEX_UNITS_ENABLE_TX1 0x00000002
178#define NV30_3D_TEX_UNITS_ENABLE_TX2 0x00000004
179#define NV30_3D_TEX_UNITS_ENABLE_TX3 0x00000008
180#define NV30_3D_TEX_UNITS_ENABLE_TX4 0x00000010
181#define NV30_3D_TEX_UNITS_ENABLE_TX5 0x00000020
182#define NV30_3D_TEX_UNITS_ENABLE_TX6 0x00000040
183#define NV30_3D_TEX_UNITS_ENABLE_TX7 0x00000080
184
185#define NV30_3D_TEX_MATRIX_ENABLE(i0) (0x00000240 + 0x4*(i0))
186#define NV30_3D_TEX_MATRIX_ENABLE__ESIZE 0x00000004
187#define NV30_3D_TEX_MATRIX_ENABLE__LEN 0x00000008
188
189#define NV40_3D_COLOR2_PITCH 0x00000280
190
191#define NV40_3D_COLOR3_PITCH 0x00000284
192
193#define NV40_3D_COLOR2_OFFSET 0x00000288
194
195#define NV40_3D_COLOR3_OFFSET 0x0000028c
196
197#define NV30_3D_VIEWPORT_TX_ORIGIN 0x000002b8
198#define NV30_3D_VIEWPORT_TX_ORIGIN_X__MASK 0x0000ffff
199#define NV30_3D_VIEWPORT_TX_ORIGIN_X__SHIFT 0
200#define NV30_3D_VIEWPORT_TX_ORIGIN_Y__MASK 0xffff0000
201#define NV30_3D_VIEWPORT_TX_ORIGIN_Y__SHIFT 16
202
203#define NV30_3D_VIEWPORT_CLIP_MODE 0x000002bc
204
205#define NV30_3D_VIEWPORT_CLIP_HORIZ(i0) (0x000002c0 + 0x8*(i0))
206#define NV30_3D_VIEWPORT_CLIP_HORIZ__ESIZE 0x00000008
207#define NV30_3D_VIEWPORT_CLIP_HORIZ__LEN 0x00000008
208#define NV30_3D_VIEWPORT_CLIP_HORIZ_L__MASK 0x0000ffff
209#define NV30_3D_VIEWPORT_CLIP_HORIZ_L__SHIFT 0
210#define NV30_3D_VIEWPORT_CLIP_HORIZ_R__MASK 0xffff0000
211#define NV30_3D_VIEWPORT_CLIP_HORIZ_R__SHIFT 16
212
213#define NV30_3D_VIEWPORT_CLIP_VERT(i0) (0x000002c4 + 0x8*(i0))
214#define NV30_3D_VIEWPORT_CLIP_VERT__ESIZE 0x00000008
215#define NV30_3D_VIEWPORT_CLIP_VERT__LEN 0x00000008
216#define NV30_3D_VIEWPORT_CLIP_VERT_T__MASK 0x0000ffff
217#define NV30_3D_VIEWPORT_CLIP_VERT_T__SHIFT 0
218#define NV30_3D_VIEWPORT_CLIP_VERT_D__MASK 0xffff0000
219#define NV30_3D_VIEWPORT_CLIP_VERT_D__SHIFT 16
220
221#define NV30_3D_DITHER_ENABLE 0x00000300
222
223#define NV30_3D_ALPHA_FUNC_ENABLE 0x00000304
224
225#define NV30_3D_ALPHA_FUNC_FUNC 0x00000308
226#define NV30_3D_ALPHA_FUNC_FUNC_NEVER 0x00000200
227#define NV30_3D_ALPHA_FUNC_FUNC_LESS 0x00000201
228#define NV30_3D_ALPHA_FUNC_FUNC_EQUAL 0x00000202
229#define NV30_3D_ALPHA_FUNC_FUNC_LEQUAL 0x00000203
230#define NV30_3D_ALPHA_FUNC_FUNC_GREATER 0x00000204
231#define NV30_3D_ALPHA_FUNC_FUNC_NOTEQUAL 0x00000205
232#define NV30_3D_ALPHA_FUNC_FUNC_GEQUAL 0x00000206
233#define NV30_3D_ALPHA_FUNC_FUNC_ALWAYS 0x00000207
234
235#define NV30_3D_ALPHA_FUNC_REF 0x0000030c
236
237#define NV30_3D_BLEND_FUNC_ENABLE 0x00000310
238
239#define NV30_3D_BLEND_FUNC_SRC 0x00000314
240#define NV30_3D_BLEND_FUNC_SRC_RGB__MASK 0x0000ffff
241#define NV30_3D_BLEND_FUNC_SRC_RGB__SHIFT 0
242#define NV30_3D_BLEND_FUNC_SRC_RGB_ZERO 0x00000000
243#define NV30_3D_BLEND_FUNC_SRC_RGB_ONE 0x00000001
244#define NV30_3D_BLEND_FUNC_SRC_RGB_SRC_COLOR 0x00000300
245#define NV30_3D_BLEND_FUNC_SRC_RGB_ONE_MINUS_SRC_COLOR 0x00000301
246#define NV30_3D_BLEND_FUNC_SRC_RGB_SRC_ALPHA 0x00000302
247#define NV30_3D_BLEND_FUNC_SRC_RGB_ONE_MINUS_SRC_ALPHA 0x00000303
248#define NV30_3D_BLEND_FUNC_SRC_RGB_DST_ALPHA 0x00000304
249#define NV30_3D_BLEND_FUNC_SRC_RGB_ONE_MINUS_DST_ALPHA 0x00000305
250#define NV30_3D_BLEND_FUNC_SRC_RGB_DST_COLOR 0x00000306
251#define NV30_3D_BLEND_FUNC_SRC_RGB_ONE_MINUS_DST_COLOR 0x00000307
252#define NV30_3D_BLEND_FUNC_SRC_RGB_SRC_ALPHA_SATURATE 0x00000308
253#define NV30_3D_BLEND_FUNC_SRC_RGB_CONSTANT_COLOR 0x00008001
254#define NV30_3D_BLEND_FUNC_SRC_RGB_ONE_MINUS_CONSTANT_COLOR 0x00008002
255#define NV30_3D_BLEND_FUNC_SRC_RGB_CONSTANT_ALPHA 0x00008003
256#define NV30_3D_BLEND_FUNC_SRC_RGB_ONE_MINUS_CONSTANT_ALPHA 0x00008004
257#define NV30_3D_BLEND_FUNC_SRC_ALPHA__MASK 0xffff0000
258#define NV30_3D_BLEND_FUNC_SRC_ALPHA__SHIFT 16
259#define NV30_3D_BLEND_FUNC_SRC_ALPHA_ZERO 0x00000000
260#define NV30_3D_BLEND_FUNC_SRC_ALPHA_ONE 0x00010000
261#define NV30_3D_BLEND_FUNC_SRC_ALPHA_SRC_COLOR 0x03000000
262#define NV30_3D_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_SRC_COLOR 0x03010000
263#define NV30_3D_BLEND_FUNC_SRC_ALPHA_SRC_ALPHA 0x03020000
264#define NV30_3D_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_SRC_ALPHA 0x03030000
265#define NV30_3D_BLEND_FUNC_SRC_ALPHA_DST_ALPHA 0x03040000
266#define NV30_3D_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_DST_ALPHA 0x03050000
267#define NV30_3D_BLEND_FUNC_SRC_ALPHA_DST_COLOR 0x03060000
268#define NV30_3D_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_DST_COLOR 0x03070000
269#define NV30_3D_BLEND_FUNC_SRC_ALPHA_SRC_ALPHA_SATURATE 0x03080000
270#define NV30_3D_BLEND_FUNC_SRC_ALPHA_CONSTANT_COLOR 0x80010000
271#define NV30_3D_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_CONSTANT_COLOR 0x80020000
272#define NV30_3D_BLEND_FUNC_SRC_ALPHA_CONSTANT_ALPHA 0x80030000
273#define NV30_3D_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_CONSTANT_ALPHA 0x80040000
274
275#define NV30_3D_BLEND_FUNC_DST 0x00000318
276#define NV30_3D_BLEND_FUNC_DST_RGB__MASK 0x0000ffff
277#define NV30_3D_BLEND_FUNC_DST_RGB__SHIFT 0
278#define NV30_3D_BLEND_FUNC_DST_RGB_ZERO 0x00000000
279#define NV30_3D_BLEND_FUNC_DST_RGB_ONE 0x00000001
280#define NV30_3D_BLEND_FUNC_DST_RGB_SRC_COLOR 0x00000300
281#define NV30_3D_BLEND_FUNC_DST_RGB_ONE_MINUS_SRC_COLOR 0x00000301
282#define NV30_3D_BLEND_FUNC_DST_RGB_SRC_ALPHA 0x00000302
283#define NV30_3D_BLEND_FUNC_DST_RGB_ONE_MINUS_SRC_ALPHA 0x00000303
284#define NV30_3D_BLEND_FUNC_DST_RGB_DST_ALPHA 0x00000304
285#define NV30_3D_BLEND_FUNC_DST_RGB_ONE_MINUS_DST_ALPHA 0x00000305
286#define NV30_3D_BLEND_FUNC_DST_RGB_DST_COLOR 0x00000306
287#define NV30_3D_BLEND_FUNC_DST_RGB_ONE_MINUS_DST_COLOR 0x00000307
288#define NV30_3D_BLEND_FUNC_DST_RGB_SRC_ALPHA_SATURATE 0x00000308
289#define NV30_3D_BLEND_FUNC_DST_RGB_CONSTANT_COLOR 0x00008001
290#define NV30_3D_BLEND_FUNC_DST_RGB_ONE_MINUS_CONSTANT_COLOR 0x00008002
291#define NV30_3D_BLEND_FUNC_DST_RGB_CONSTANT_ALPHA 0x00008003
292#define NV30_3D_BLEND_FUNC_DST_RGB_ONE_MINUS_CONSTANT_ALPHA 0x00008004
293#define NV30_3D_BLEND_FUNC_DST_ALPHA__MASK 0xffff0000
294#define NV30_3D_BLEND_FUNC_DST_ALPHA__SHIFT 16
295#define NV30_3D_BLEND_FUNC_DST_ALPHA_ZERO 0x00000000
296#define NV30_3D_BLEND_FUNC_DST_ALPHA_ONE 0x00010000
297#define NV30_3D_BLEND_FUNC_DST_ALPHA_SRC_COLOR 0x03000000
298#define NV30_3D_BLEND_FUNC_DST_ALPHA_ONE_MINUS_SRC_COLOR 0x03010000
299#define NV30_3D_BLEND_FUNC_DST_ALPHA_SRC_ALPHA 0x03020000
300#define NV30_3D_BLEND_FUNC_DST_ALPHA_ONE_MINUS_SRC_ALPHA 0x03030000
301#define NV30_3D_BLEND_FUNC_DST_ALPHA_DST_ALPHA 0x03040000
302#define NV30_3D_BLEND_FUNC_DST_ALPHA_ONE_MINUS_DST_ALPHA 0x03050000
303#define NV30_3D_BLEND_FUNC_DST_ALPHA_DST_COLOR 0x03060000
304#define NV30_3D_BLEND_FUNC_DST_ALPHA_ONE_MINUS_DST_COLOR 0x03070000
305#define NV30_3D_BLEND_FUNC_DST_ALPHA_SRC_ALPHA_SATURATE 0x03080000
306#define NV30_3D_BLEND_FUNC_DST_ALPHA_CONSTANT_COLOR 0x80010000
307#define NV30_3D_BLEND_FUNC_DST_ALPHA_ONE_MINUS_CONSTANT_COLOR 0x80020000
308#define NV30_3D_BLEND_FUNC_DST_ALPHA_CONSTANT_ALPHA 0x80030000
309#define NV30_3D_BLEND_FUNC_DST_ALPHA_ONE_MINUS_CONSTANT_ALPHA 0x80040000
310
311#define NV30_3D_BLEND_COLOR 0x0000031c
312#define NV30_3D_BLEND_COLOR_B__MASK 0x000000ff
313#define NV30_3D_BLEND_COLOR_B__SHIFT 0
314#define NV30_3D_BLEND_COLOR_G__MASK 0x0000ff00
315#define NV30_3D_BLEND_COLOR_G__SHIFT 8
316#define NV30_3D_BLEND_COLOR_R__MASK 0x00ff0000
317#define NV30_3D_BLEND_COLOR_R__SHIFT 16
318#define NV30_3D_BLEND_COLOR_A__MASK 0xff000000
319#define NV30_3D_BLEND_COLOR_A__SHIFT 24
320
321#define NV30_3D_BLEND_EQUATION 0x00000320
322#define NV30_3D_BLEND_EQUATION_FUNC_ADD 0x00008006
323#define NV30_3D_BLEND_EQUATION_MIN 0x00008007
324#define NV30_3D_BLEND_EQUATION_MAX 0x00008008
325#define NV30_3D_BLEND_EQUATION_FUNC_SUBTRACT 0x0000800a
326#define NV30_3D_BLEND_EQUATION_FUNC_REVERSE_SUBTRACT 0x0000800b
327
328#define NV40_3D_BLEND_EQUATION 0x00000320
329#define NV40_3D_BLEND_EQUATION_RGB__MASK 0x0000ffff
330#define NV40_3D_BLEND_EQUATION_RGB__SHIFT 0
331#define NV40_3D_BLEND_EQUATION_RGB_FUNC_ADD 0x00008006
332#define NV40_3D_BLEND_EQUATION_RGB_MIN 0x00008007
333#define NV40_3D_BLEND_EQUATION_RGB_MAX 0x00008008
334#define NV40_3D_BLEND_EQUATION_RGB_FUNC_SUBTRACT 0x0000800a
335#define NV40_3D_BLEND_EQUATION_RGB_FUNC_REVERSE_SUBTRACT 0x0000800b
336#define NV40_3D_BLEND_EQUATION_ALPHA__MASK 0xffff0000
337#define NV40_3D_BLEND_EQUATION_ALPHA__SHIFT 16
338#define NV40_3D_BLEND_EQUATION_ALPHA_FUNC_ADD 0x80060000
339#define NV40_3D_BLEND_EQUATION_ALPHA_MIN 0x80070000
340#define NV40_3D_BLEND_EQUATION_ALPHA_MAX 0x80080000
341#define NV40_3D_BLEND_EQUATION_ALPHA_FUNC_SUBTRACT 0x800a0000
342#define NV40_3D_BLEND_EQUATION_ALPHA_FUNC_REVERSE_SUBTRACT 0x800b0000
343
344#define NV30_3D_COLOR_MASK 0x00000324
345#define NV30_3D_COLOR_MASK_B 0x000000ff
346#define NV30_3D_COLOR_MASK_G 0x0000ff00
347#define NV30_3D_COLOR_MASK_R 0x00ff0000
348#define NV30_3D_COLOR_MASK_A 0xff000000
349
350#define NV30_3D_STENCIL(i0) (0x00000328 + 0x20*(i0))
351#define NV30_3D_STENCIL__ESIZE 0x00000020
352#define NV30_3D_STENCIL__LEN 0x00000002
353
354#define NV30_3D_STENCIL_ENABLE(i0) (0x00000328 + 0x20*(i0))
355
356#define NV30_3D_STENCIL_MASK(i0) (0x0000032c + 0x20*(i0))
357
358#define NV30_3D_STENCIL_FUNC_FUNC(i0) (0x00000330 + 0x20*(i0))
359#define NV30_3D_STENCIL_FUNC_FUNC_NEVER 0x00000200
360#define NV30_3D_STENCIL_FUNC_FUNC_LESS 0x00000201
361#define NV30_3D_STENCIL_FUNC_FUNC_EQUAL 0x00000202
362#define NV30_3D_STENCIL_FUNC_FUNC_LEQUAL 0x00000203
363#define NV30_3D_STENCIL_FUNC_FUNC_GREATER 0x00000204
364#define NV30_3D_STENCIL_FUNC_FUNC_NOTEQUAL 0x00000205
365#define NV30_3D_STENCIL_FUNC_FUNC_GEQUAL 0x00000206
366#define NV30_3D_STENCIL_FUNC_FUNC_ALWAYS 0x00000207
367
368#define NV30_3D_STENCIL_FUNC_REF(i0) (0x00000334 + 0x20*(i0))
369
370#define NV30_3D_STENCIL_FUNC_MASK(i0) (0x00000338 + 0x20*(i0))
371
372#define NV30_3D_STENCIL_OP_FAIL(i0) (0x0000033c + 0x20*(i0))
373#define NV30_3D_STENCIL_OP_FAIL_ZERO 0x00000000
374#define NV30_3D_STENCIL_OP_FAIL_INVERT 0x0000150a
375#define NV30_3D_STENCIL_OP_FAIL_KEEP 0x00001e00
376#define NV30_3D_STENCIL_OP_FAIL_REPLACE 0x00001e01
377#define NV30_3D_STENCIL_OP_FAIL_INCR 0x00001e02
378#define NV30_3D_STENCIL_OP_FAIL_DECR 0x00001e03
379#define NV30_3D_STENCIL_OP_FAIL_INCR_WRAP 0x00008507
380#define NV30_3D_STENCIL_OP_FAIL_DECR_WRAP 0x00008508
381
382#define NV30_3D_STENCIL_OP_ZFAIL(i0) (0x00000340 + 0x20*(i0))
383#define NV30_3D_STENCIL_OP_ZFAIL_ZERO 0x00000000
384#define NV30_3D_STENCIL_OP_ZFAIL_INVERT 0x0000150a
385#define NV30_3D_STENCIL_OP_ZFAIL_KEEP 0x00001e00
386#define NV30_3D_STENCIL_OP_ZFAIL_REPLACE 0x00001e01
387#define NV30_3D_STENCIL_OP_ZFAIL_INCR 0x00001e02
388#define NV30_3D_STENCIL_OP_ZFAIL_DECR 0x00001e03
389#define NV30_3D_STENCIL_OP_ZFAIL_INCR_WRAP 0x00008507
390#define NV30_3D_STENCIL_OP_ZFAIL_DECR_WRAP 0x00008508
391
392#define NV30_3D_STENCIL_OP_ZPASS(i0) (0x00000344 + 0x20*(i0))
393#define NV30_3D_STENCIL_OP_ZPASS_ZERO 0x00000000
394#define NV30_3D_STENCIL_OP_ZPASS_INVERT 0x0000150a
395#define NV30_3D_STENCIL_OP_ZPASS_KEEP 0x00001e00
396#define NV30_3D_STENCIL_OP_ZPASS_REPLACE 0x00001e01
397#define NV30_3D_STENCIL_OP_ZPASS_INCR 0x00001e02
398#define NV30_3D_STENCIL_OP_ZPASS_DECR 0x00001e03
399#define NV30_3D_STENCIL_OP_ZPASS_INCR_WRAP 0x00008507
400#define NV30_3D_STENCIL_OP_ZPASS_DECR_WRAP 0x00008508
401
402#define NV30_3D_SHADE_MODEL 0x00000368
403#define NV30_3D_SHADE_MODEL_FLAT 0x00001d00
404#define NV30_3D_SHADE_MODEL_SMOOTH 0x00001d01
405
406#define NV30_3D_FOG_ENABLE 0x0000036c
407
408#define NV30_3D_FOG_COLOR 0x00000370
409#define NV30_3D_FOG_COLOR_R__MASK 0x000000ff
410#define NV30_3D_FOG_COLOR_R__SHIFT 0
411#define NV30_3D_FOG_COLOR_G__MASK 0x0000ff00
412#define NV30_3D_FOG_COLOR_G__SHIFT 8
413#define NV30_3D_FOG_COLOR_B__MASK 0x00ff0000
414#define NV30_3D_FOG_COLOR_B__SHIFT 16
415#define NV30_3D_FOG_COLOR_A__MASK 0xff000000
416#define NV30_3D_FOG_COLOR_A__SHIFT 24
417
418#define NV40_3D_MRT_COLOR_MASK 0x00000370
419#define NV40_3D_MRT_COLOR_MASK_BUFFER1_A 0x00000010
420#define NV40_3D_MRT_COLOR_MASK_BUFFER1_R 0x00000020
421#define NV40_3D_MRT_COLOR_MASK_BUFFER1_G 0x00000040
422#define NV40_3D_MRT_COLOR_MASK_BUFFER1_B 0x00000080
423#define NV40_3D_MRT_COLOR_MASK_BUFFER2_A 0x00000100
424#define NV40_3D_MRT_COLOR_MASK_BUFFER2_R 0x00000200
425#define NV40_3D_MRT_COLOR_MASK_BUFFER2_G 0x00000400
426#define NV40_3D_MRT_COLOR_MASK_BUFFER2_B 0x00000800
427#define NV40_3D_MRT_COLOR_MASK_BUFFER3_A 0x00001000
428#define NV40_3D_MRT_COLOR_MASK_BUFFER3_R 0x00002000
429#define NV40_3D_MRT_COLOR_MASK_BUFFER3_G 0x00004000
430#define NV40_3D_MRT_COLOR_MASK_BUFFER3_B 0x00008000
431
432#define NV30_3D_COLOR_LOGIC_OP_ENABLE 0x00000374
433
434#define NV30_3D_COLOR_LOGIC_OP_OP 0x00000378
435#define NV30_3D_COLOR_LOGIC_OP_OP_CLEAR 0x00001500
436#define NV30_3D_COLOR_LOGIC_OP_OP_AND 0x00001501
437#define NV30_3D_COLOR_LOGIC_OP_OP_AND_REVERSE 0x00001502
438#define NV30_3D_COLOR_LOGIC_OP_OP_COPY 0x00001503
439#define NV30_3D_COLOR_LOGIC_OP_OP_AND_INVERTED 0x00001504
440#define NV30_3D_COLOR_LOGIC_OP_OP_NOOP 0x00001505
441#define NV30_3D_COLOR_LOGIC_OP_OP_XOR 0x00001506
442#define NV30_3D_COLOR_LOGIC_OP_OP_OR 0x00001507
443#define NV30_3D_COLOR_LOGIC_OP_OP_NOR 0x00001508
444#define NV30_3D_COLOR_LOGIC_OP_OP_EQUIV 0x00001509
445#define NV30_3D_COLOR_LOGIC_OP_OP_INVERT 0x0000150a
446#define NV30_3D_COLOR_LOGIC_OP_OP_OR_REVERSE 0x0000150b
447#define NV30_3D_COLOR_LOGIC_OP_OP_COPY_INVERTED 0x0000150c
448#define NV30_3D_COLOR_LOGIC_OP_OP_OR_INVERTED 0x0000150d
449#define NV30_3D_COLOR_LOGIC_OP_OP_NAND 0x0000150e
450#define NV30_3D_COLOR_LOGIC_OP_OP_SET 0x0000150f
451
452#define NV30_3D_NORMALIZE_ENABLE 0x0000037c
453
454#define NV30_3D_COLOR_MATERIAL 0x00000390
455#define NV30_3D_COLOR_MATERIAL_FRONT_EMISSION_ENABLE 0x00000001
456#define NV30_3D_COLOR_MATERIAL_FRONT_AMBIENT_ENABLE 0x00000004
457#define NV30_3D_COLOR_MATERIAL_FRONT_DIFFUSE_ENABLE 0x00000010
458#define NV30_3D_COLOR_MATERIAL_FRONT_SPECULAR_ENABLE 0x00000040
459#define NV30_3D_COLOR_MATERIAL_BACK_EMISSION_ENABLE 0x00000100
460#define NV30_3D_COLOR_MATERIAL_BACK_AMBIENT_ENABLE 0x00000400
461#define NV30_3D_COLOR_MATERIAL_BACK_DIFFUSE_ENABLE 0x00001000
462#define NV30_3D_COLOR_MATERIAL_BACK_SPECULAR_ENABLE 0x00004000
463
464#define NV30_3D_DEPTH_RANGE_NEAR 0x00000394
465
466#define NV30_3D_DEPTH_RANGE_FAR 0x00000398
467
468#define NV30_3D_COLOR_MATERIAL_FRONT 0x000003a0
469
470
471#define NV30_3D_COLOR_MATERIAL_FRONT_R 0x000003a0
472
473#define NV30_3D_COLOR_MATERIAL_FRONT_G 0x000003a4
474
475#define NV30_3D_COLOR_MATERIAL_FRONT_B 0x000003a8
476
477#define NV30_3D_COLOR_MATERIAL_FRONT_A 0x000003ac
478
479#define NV40_3D_MIPMAP_ROUNDING 0x000003b0
480#define NV40_3D_MIPMAP_ROUNDING_MODE__MASK 0x00100000
481#define NV40_3D_MIPMAP_ROUNDING_MODE__SHIFT 20
482#define NV40_3D_MIPMAP_ROUNDING_MODE_UP 0x00000000
483#define NV40_3D_MIPMAP_ROUNDING_MODE_DOWN 0x00100000
484
485#define NV30_3D_LINE_WIDTH 0x000003b8
486
487#define NV30_3D_LINE_SMOOTH_ENABLE 0x000003bc
488
489
490
491#define NV30_3D_TEX_GEN_MODE(i0, i1) (0x00000400 + 0x10*(i0) + 0x4*(i1))
492#define NV30_3D_TEX_GEN_MODE__ESIZE 0x00000004
493#define NV30_3D_TEX_GEN_MODE__LEN 0x00000004
494#define NV30_3D_TEX_GEN_MODE_FALSE 0x00000000
495#define NV30_3D_TEX_GEN_MODE_EYE_LINEAR 0x00002400
496#define NV30_3D_TEX_GEN_MODE_OBJECT_LINEAR 0x00002401
497#define NV30_3D_TEX_GEN_MODE_SPHERE_MAP 0x00002402
498#define NV30_3D_TEX_GEN_MODE_NORMAL_MAP 0x00008511
499#define NV30_3D_TEX_GEN_MODE_REFLECTION_MAP 0x00008512
500
501#define NV30_3D_MODELVIEW_MATRIX(i0) (0x00000480 + 0x4*(i0))
502#define NV30_3D_MODELVIEW_MATRIX__ESIZE 0x00000004
503#define NV30_3D_MODELVIEW_MATRIX__LEN 0x00000010
504
505#define NV30_3D_INVERSE_MODELVIEW_MATRIX(i0) (0x00000580 + 0x4*(i0))
506#define NV30_3D_INVERSE_MODELVIEW_MATRIX__ESIZE 0x00000004
507#define NV30_3D_INVERSE_MODELVIEW_MATRIX__LEN 0x0000000c
508
509#define NV30_3D_PROJECTION_MATRIX(i0) (0x00000680 + 0x4*(i0))
510#define NV30_3D_PROJECTION_MATRIX__ESIZE 0x00000004
511#define NV30_3D_PROJECTION_MATRIX__LEN 0x00000010
512
513
514#define NV30_3D_TEX_MATRIX(i0, i1) (0x000006c0 + 0x40*(i0) + 0x4*(i1))
515#define NV30_3D_TEX_MATRIX__ESIZE 0x00000004
516#define NV30_3D_TEX_MATRIX__LEN 0x00000010
517
518#define NV30_3D_SCISSOR_HORIZ 0x000008c0
519#define NV30_3D_SCISSOR_HORIZ_X__MASK 0x0000ffff
520#define NV30_3D_SCISSOR_HORIZ_X__SHIFT 0
521#define NV30_3D_SCISSOR_HORIZ_W__MASK 0xffff0000
522#define NV30_3D_SCISSOR_HORIZ_W__SHIFT 16
523
524#define NV30_3D_SCISSOR_VERT 0x000008c4
525#define NV30_3D_SCISSOR_VERT_Y__MASK 0x0000ffff
526#define NV30_3D_SCISSOR_VERT_Y__SHIFT 0
527#define NV30_3D_SCISSOR_VERT_H__MASK 0xffff0000
528#define NV30_3D_SCISSOR_VERT_H__SHIFT 16
529
530#define NV30_3D_FOG_COORD_DIST 0x000008c8
531
532#define NV30_3D_FOG_MODE 0x000008cc
533
534#define NV30_3D_FOG_EQUATION_CONSTANT 0x000008d0
535
536#define NV30_3D_FOG_EQUATION_LINEAR 0x000008d4
537
538#define NV30_3D_FOG_EQUATION_QUADRATIC 0x000008d8
539
540#define NV30_3D_FP_ACTIVE_PROGRAM 0x000008e4
541#define NV30_3D_FP_ACTIVE_PROGRAM_DMA0 0x00000001
542#define NV30_3D_FP_ACTIVE_PROGRAM_DMA1 0x00000002
543#define NV30_3D_FP_ACTIVE_PROGRAM_OFFSET__MASK 0xfffffffc
544#define NV30_3D_FP_ACTIVE_PROGRAM_OFFSET__SHIFT 2
545
546
547#define NV30_3D_RC_COLOR0 0x000008ec
548#define NV30_3D_RC_COLOR0_B__MASK 0x000000ff
549#define NV30_3D_RC_COLOR0_B__SHIFT 0
550#define NV30_3D_RC_COLOR0_G__MASK 0x0000ff00
551#define NV30_3D_RC_COLOR0_G__SHIFT 8
552#define NV30_3D_RC_COLOR0_R__MASK 0x00ff0000
553#define NV30_3D_RC_COLOR0_R__SHIFT 16
554#define NV30_3D_RC_COLOR0_A__MASK 0xff000000
555#define NV30_3D_RC_COLOR0_A__SHIFT 24
556
557#define NV30_3D_RC_COLOR1 0x000008f0
558#define NV30_3D_RC_COLOR1_B__MASK 0x000000ff
559#define NV30_3D_RC_COLOR1_B__SHIFT 0
560#define NV30_3D_RC_COLOR1_G__MASK 0x0000ff00
561#define NV30_3D_RC_COLOR1_G__SHIFT 8
562#define NV30_3D_RC_COLOR1_R__MASK 0x00ff0000
563#define NV30_3D_RC_COLOR1_R__SHIFT 16
564#define NV30_3D_RC_COLOR1_A__MASK 0xff000000
565#define NV30_3D_RC_COLOR1_A__SHIFT 24
566
567#define NV30_3D_RC_FINAL0 0x000008f4
568#define NV30_3D_RC_FINAL0_D_INPUT__MASK 0x0000000f
569#define NV30_3D_RC_FINAL0_D_INPUT__SHIFT 0
570#define NV30_3D_RC_FINAL0_D_INPUT_ZERO 0x00000000
571#define NV30_3D_RC_FINAL0_D_INPUT_CONSTANT_COLOR0 0x00000001
572#define NV30_3D_RC_FINAL0_D_INPUT_CONSTANT_COLOR1 0x00000002
573#define NV30_3D_RC_FINAL0_D_INPUT_FOG 0x00000003
574#define NV30_3D_RC_FINAL0_D_INPUT_PRIMARY_COLOR 0x00000004
575#define NV30_3D_RC_FINAL0_D_INPUT_SECONDARY_COLOR 0x00000005
576#define NV30_3D_RC_FINAL0_D_INPUT_TEXTURE0 0x00000008
577#define NV30_3D_RC_FINAL0_D_INPUT_TEXTURE1 0x00000009
578#define NV30_3D_RC_FINAL0_D_INPUT_TEXTURE2 0x0000000a
579#define NV30_3D_RC_FINAL0_D_INPUT_TEXTURE3 0x0000000b
580#define NV30_3D_RC_FINAL0_D_INPUT_SPARE0 0x0000000c
581#define NV30_3D_RC_FINAL0_D_INPUT_SPARE1 0x0000000d
582#define NV30_3D_RC_FINAL0_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e
583#define NV30_3D_RC_FINAL0_D_INPUT_E_TIMES_F 0x0000000f
584#define NV30_3D_RC_FINAL0_D_COMPONENT_USAGE__MASK 0x00000010
585#define NV30_3D_RC_FINAL0_D_COMPONENT_USAGE__SHIFT 4
586#define NV30_3D_RC_FINAL0_D_COMPONENT_USAGE_RGB 0x00000000
587#define NV30_3D_RC_FINAL0_D_COMPONENT_USAGE_ALPHA 0x00000010
588#define NV30_3D_RC_FINAL0_D_MAPPING__MASK 0x000000e0
589#define NV30_3D_RC_FINAL0_D_MAPPING__SHIFT 5
590#define NV30_3D_RC_FINAL0_D_MAPPING_UNSIGNED_IDENTITY 0x00000000
591#define NV30_3D_RC_FINAL0_D_MAPPING_UNSIGNED_INVERT 0x00000020
592#define NV30_3D_RC_FINAL0_D_MAPPING_EXPAND_NORMAL 0x00000040
593#define NV30_3D_RC_FINAL0_D_MAPPING_EXPAND_NEGATE 0x00000060
594#define NV30_3D_RC_FINAL0_D_MAPPING_HALF_BIAS_NORMAL 0x00000080
595#define NV30_3D_RC_FINAL0_D_MAPPING_HALF_BIAS_NEGATE 0x000000a0
596#define NV30_3D_RC_FINAL0_D_MAPPING_SIGNED_IDENTITY 0x000000c0
597#define NV30_3D_RC_FINAL0_D_MAPPING_SIGNED_NEGATE 0x000000e0
598#define NV30_3D_RC_FINAL0_C_INPUT__MASK 0x00000f00
599#define NV30_3D_RC_FINAL0_C_INPUT__SHIFT 8
600#define NV30_3D_RC_FINAL0_C_INPUT_ZERO 0x00000000
601#define NV30_3D_RC_FINAL0_C_INPUT_CONSTANT_COLOR0 0x00000100
602#define NV30_3D_RC_FINAL0_C_INPUT_CONSTANT_COLOR1 0x00000200
603#define NV30_3D_RC_FINAL0_C_INPUT_FOG 0x00000300
604#define NV30_3D_RC_FINAL0_C_INPUT_PRIMARY_COLOR 0x00000400
605#define NV30_3D_RC_FINAL0_C_INPUT_SECONDARY_COLOR 0x00000500
606#define NV30_3D_RC_FINAL0_C_INPUT_TEXTURE0 0x00000800
607#define NV30_3D_RC_FINAL0_C_INPUT_TEXTURE1 0x00000900
608#define NV30_3D_RC_FINAL0_C_INPUT_TEXTURE2 0x00000a00
609#define NV30_3D_RC_FINAL0_C_INPUT_TEXTURE3 0x00000b00
610#define NV30_3D_RC_FINAL0_C_INPUT_SPARE0 0x00000c00
611#define NV30_3D_RC_FINAL0_C_INPUT_SPARE1 0x00000d00
612#define NV30_3D_RC_FINAL0_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00
613#define NV30_3D_RC_FINAL0_C_INPUT_E_TIMES_F 0x00000f00
614#define NV30_3D_RC_FINAL0_C_COMPONENT_USAGE__MASK 0x00001000
615#define NV30_3D_RC_FINAL0_C_COMPONENT_USAGE__SHIFT 12
616#define NV30_3D_RC_FINAL0_C_COMPONENT_USAGE_RGB 0x00000000
617#define NV30_3D_RC_FINAL0_C_COMPONENT_USAGE_ALPHA 0x00001000
618#define NV30_3D_RC_FINAL0_C_MAPPING__MASK 0x0000e000
619#define NV30_3D_RC_FINAL0_C_MAPPING__SHIFT 13
620#define NV30_3D_RC_FINAL0_C_MAPPING_UNSIGNED_IDENTITY 0x00000000
621#define NV30_3D_RC_FINAL0_C_MAPPING_UNSIGNED_INVERT 0x00002000
622#define NV30_3D_RC_FINAL0_C_MAPPING_EXPAND_NORMAL 0x00004000
623#define NV30_3D_RC_FINAL0_C_MAPPING_EXPAND_NEGATE 0x00006000
624#define NV30_3D_RC_FINAL0_C_MAPPING_HALF_BIAS_NORMAL 0x00008000
625#define NV30_3D_RC_FINAL0_C_MAPPING_HALF_BIAS_NEGATE 0x0000a000
626#define NV30_3D_RC_FINAL0_C_MAPPING_SIGNED_IDENTITY 0x0000c000
627#define NV30_3D_RC_FINAL0_C_MAPPING_SIGNED_NEGATE 0x0000e000
628#define NV30_3D_RC_FINAL0_B_INPUT__MASK 0x000f0000
629#define NV30_3D_RC_FINAL0_B_INPUT__SHIFT 16
630#define NV30_3D_RC_FINAL0_B_INPUT_ZERO 0x00000000
631#define NV30_3D_RC_FINAL0_B_INPUT_CONSTANT_COLOR0 0x00010000
632#define NV30_3D_RC_FINAL0_B_INPUT_CONSTANT_COLOR1 0x00020000
633#define NV30_3D_RC_FINAL0_B_INPUT_FOG 0x00030000
634#define NV30_3D_RC_FINAL0_B_INPUT_PRIMARY_COLOR 0x00040000
635#define NV30_3D_RC_FINAL0_B_INPUT_SECONDARY_COLOR 0x00050000
636#define NV30_3D_RC_FINAL0_B_INPUT_TEXTURE0 0x00080000
637#define NV30_3D_RC_FINAL0_B_INPUT_TEXTURE1 0x00090000
638#define NV30_3D_RC_FINAL0_B_INPUT_TEXTURE2 0x000a0000
639#define NV30_3D_RC_FINAL0_B_INPUT_TEXTURE3 0x000b0000
640#define NV30_3D_RC_FINAL0_B_INPUT_SPARE0 0x000c0000
641#define NV30_3D_RC_FINAL0_B_INPUT_SPARE1 0x000d0000
642#define NV30_3D_RC_FINAL0_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000
643#define NV30_3D_RC_FINAL0_B_INPUT_E_TIMES_F 0x000f0000
644#define NV30_3D_RC_FINAL0_B_COMPONENT_USAGE__MASK 0x00100000
645#define NV30_3D_RC_FINAL0_B_COMPONENT_USAGE__SHIFT 20
646#define NV30_3D_RC_FINAL0_B_COMPONENT_USAGE_RGB 0x00000000
647#define NV30_3D_RC_FINAL0_B_COMPONENT_USAGE_ALPHA 0x00100000
648#define NV30_3D_RC_FINAL0_B_MAPPING__MASK 0x00e00000
649#define NV30_3D_RC_FINAL0_B_MAPPING__SHIFT 21
650#define NV30_3D_RC_FINAL0_B_MAPPING_UNSIGNED_IDENTITY 0x00000000
651#define NV30_3D_RC_FINAL0_B_MAPPING_UNSIGNED_INVERT 0x00200000
652#define NV30_3D_RC_FINAL0_B_MAPPING_EXPAND_NORMAL 0x00400000
653#define NV30_3D_RC_FINAL0_B_MAPPING_EXPAND_NEGATE 0x00600000
654#define NV30_3D_RC_FINAL0_B_MAPPING_HALF_BIAS_NORMAL 0x00800000
655#define NV30_3D_RC_FINAL0_B_MAPPING_HALF_BIAS_NEGATE 0x00a00000
656#define NV30_3D_RC_FINAL0_B_MAPPING_SIGNED_IDENTITY 0x00c00000
657#define NV30_3D_RC_FINAL0_B_MAPPING_SIGNED_NEGATE 0x00e00000
658#define NV30_3D_RC_FINAL0_A_INPUT__MASK 0x0f000000
659#define NV30_3D_RC_FINAL0_A_INPUT__SHIFT 24
660#define NV30_3D_RC_FINAL0_A_INPUT_ZERO 0x00000000
661#define NV30_3D_RC_FINAL0_A_INPUT_CONSTANT_COLOR0 0x01000000
662#define NV30_3D_RC_FINAL0_A_INPUT_CONSTANT_COLOR1 0x02000000
663#define NV30_3D_RC_FINAL0_A_INPUT_FOG 0x03000000
664#define NV30_3D_RC_FINAL0_A_INPUT_PRIMARY_COLOR 0x04000000
665#define NV30_3D_RC_FINAL0_A_INPUT_SECONDARY_COLOR 0x05000000
666#define NV30_3D_RC_FINAL0_A_INPUT_TEXTURE0 0x08000000
667#define NV30_3D_RC_FINAL0_A_INPUT_TEXTURE1 0x09000000
668#define NV30_3D_RC_FINAL0_A_INPUT_TEXTURE2 0x0a000000
669#define NV30_3D_RC_FINAL0_A_INPUT_TEXTURE3 0x0b000000
670#define NV30_3D_RC_FINAL0_A_INPUT_SPARE0 0x0c000000
671#define NV30_3D_RC_FINAL0_A_INPUT_SPARE1 0x0d000000
672#define NV30_3D_RC_FINAL0_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000
673#define NV30_3D_RC_FINAL0_A_INPUT_E_TIMES_F 0x0f000000
674#define NV30_3D_RC_FINAL0_A_COMPONENT_USAGE__MASK 0x10000000
675#define NV30_3D_RC_FINAL0_A_COMPONENT_USAGE__SHIFT 28
676#define NV30_3D_RC_FINAL0_A_COMPONENT_USAGE_RGB 0x00000000
677#define NV30_3D_RC_FINAL0_A_COMPONENT_USAGE_ALPHA 0x10000000
678#define NV30_3D_RC_FINAL0_A_MAPPING__MASK 0xe0000000
679#define NV30_3D_RC_FINAL0_A_MAPPING__SHIFT 29
680#define NV30_3D_RC_FINAL0_A_MAPPING_UNSIGNED_IDENTITY 0x00000000
681#define NV30_3D_RC_FINAL0_A_MAPPING_UNSIGNED_INVERT 0x20000000
682#define NV30_3D_RC_FINAL0_A_MAPPING_EXPAND_NORMAL 0x40000000
683#define NV30_3D_RC_FINAL0_A_MAPPING_EXPAND_NEGATE 0x60000000
684#define NV30_3D_RC_FINAL0_A_MAPPING_HALF_BIAS_NORMAL 0x80000000
685#define NV30_3D_RC_FINAL0_A_MAPPING_HALF_BIAS_NEGATE 0xa0000000
686#define NV30_3D_RC_FINAL0_A_MAPPING_SIGNED_IDENTITY 0xc0000000
687#define NV30_3D_RC_FINAL0_A_MAPPING_SIGNED_NEGATE 0xe0000000
688
689#define NV30_3D_RC_FINAL1 0x000008f8
690#define NV30_3D_RC_FINAL1_COLOR_SUM_CLAMP 0x00000080
691#define NV30_3D_RC_FINAL1_G_INPUT__MASK 0x00000f00
692#define NV30_3D_RC_FINAL1_G_INPUT__SHIFT 8
693#define NV30_3D_RC_FINAL1_G_INPUT_ZERO 0x00000000
694#define NV30_3D_RC_FINAL1_G_INPUT_CONSTANT_COLOR0 0x00000100
695#define NV30_3D_RC_FINAL1_G_INPUT_CONSTANT_COLOR1 0x00000200
696#define NV30_3D_RC_FINAL1_G_INPUT_FOG 0x00000300
697#define NV30_3D_RC_FINAL1_G_INPUT_PRIMARY_COLOR 0x00000400
698#define NV30_3D_RC_FINAL1_G_INPUT_SECONDARY_COLOR 0x00000500
699#define NV30_3D_RC_FINAL1_G_INPUT_TEXTURE0 0x00000800
700#define NV30_3D_RC_FINAL1_G_INPUT_TEXTURE1 0x00000900
701#define NV30_3D_RC_FINAL1_G_INPUT_TEXTURE2 0x00000a00
702#define NV30_3D_RC_FINAL1_G_INPUT_TEXTURE3 0x00000b00
703#define NV30_3D_RC_FINAL1_G_INPUT_SPARE0 0x00000c00
704#define NV30_3D_RC_FINAL1_G_INPUT_SPARE1 0x00000d00
705#define NV30_3D_RC_FINAL1_G_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00
706#define NV30_3D_RC_FINAL1_G_INPUT_E_TIMES_F 0x00000f00
707#define NV30_3D_RC_FINAL1_G_COMPONENT_USAGE__MASK 0x00001000
708#define NV30_3D_RC_FINAL1_G_COMPONENT_USAGE__SHIFT 12
709#define NV30_3D_RC_FINAL1_G_COMPONENT_USAGE_RGB 0x00000000
710#define NV30_3D_RC_FINAL1_G_COMPONENT_USAGE_ALPHA 0x00001000
711#define NV30_3D_RC_FINAL1_G_MAPPING__MASK 0x0000e000
712#define NV30_3D_RC_FINAL1_G_MAPPING__SHIFT 13
713#define NV30_3D_RC_FINAL1_G_MAPPING_UNSIGNED_IDENTITY 0x00000000
714#define NV30_3D_RC_FINAL1_G_MAPPING_UNSIGNED_INVERT 0x00002000
715#define NV30_3D_RC_FINAL1_G_MAPPING_EXPAND_NORMAL 0x00004000
716#define NV30_3D_RC_FINAL1_G_MAPPING_EXPAND_NEGATE 0x00006000
717#define NV30_3D_RC_FINAL1_G_MAPPING_HALF_BIAS_NORMAL 0x00008000
718#define NV30_3D_RC_FINAL1_G_MAPPING_HALF_BIAS_NEGATE 0x0000a000
719#define NV30_3D_RC_FINAL1_G_MAPPING_SIGNED_IDENTITY 0x0000c000
720#define NV30_3D_RC_FINAL1_G_MAPPING_SIGNED_NEGATE 0x0000e000
721#define NV30_3D_RC_FINAL1_F_INPUT__MASK 0x000f0000
722#define NV30_3D_RC_FINAL1_F_INPUT__SHIFT 16
723#define NV30_3D_RC_FINAL1_F_INPUT_ZERO 0x00000000
724#define NV30_3D_RC_FINAL1_F_INPUT_CONSTANT_COLOR0 0x00010000
725#define NV30_3D_RC_FINAL1_F_INPUT_CONSTANT_COLOR1 0x00020000
726#define NV30_3D_RC_FINAL1_F_INPUT_FOG 0x00030000
727#define NV30_3D_RC_FINAL1_F_INPUT_PRIMARY_COLOR 0x00040000
728#define NV30_3D_RC_FINAL1_F_INPUT_SECONDARY_COLOR 0x00050000
729#define NV30_3D_RC_FINAL1_F_INPUT_TEXTURE0 0x00080000
730#define NV30_3D_RC_FINAL1_F_INPUT_TEXTURE1 0x00090000
731#define NV30_3D_RC_FINAL1_F_INPUT_TEXTURE2 0x000a0000
732#define NV30_3D_RC_FINAL1_F_INPUT_TEXTURE3 0x000b0000
733#define NV30_3D_RC_FINAL1_F_INPUT_SPARE0 0x000c0000
734#define NV30_3D_RC_FINAL1_F_INPUT_SPARE1 0x000d0000
735#define NV30_3D_RC_FINAL1_F_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000
736#define NV30_3D_RC_FINAL1_F_INPUT_E_TIMES_F 0x000f0000
737#define NV30_3D_RC_FINAL1_F_COMPONENT_USAGE__MASK 0x00100000
738#define NV30_3D_RC_FINAL1_F_COMPONENT_USAGE__SHIFT 20
739#define NV30_3D_RC_FINAL1_F_COMPONENT_USAGE_RGB 0x00000000
740#define NV30_3D_RC_FINAL1_F_COMPONENT_USAGE_ALPHA 0x00100000
741#define NV30_3D_RC_FINAL1_F_MAPPING__MASK 0x00e00000
742#define NV30_3D_RC_FINAL1_F_MAPPING__SHIFT 21
743#define NV30_3D_RC_FINAL1_F_MAPPING_UNSIGNED_IDENTITY 0x00000000
744#define NV30_3D_RC_FINAL1_F_MAPPING_UNSIGNED_INVERT 0x00200000
745#define NV30_3D_RC_FINAL1_F_MAPPING_EXPAND_NORMAL 0x00400000
746#define NV30_3D_RC_FINAL1_F_MAPPING_EXPAND_NEGATE 0x00600000
747#define NV30_3D_RC_FINAL1_F_MAPPING_HALF_BIAS_NORMAL 0x00800000
748#define NV30_3D_RC_FINAL1_F_MAPPING_HALF_BIAS_NEGATE 0x00a00000
749#define NV30_3D_RC_FINAL1_F_MAPPING_SIGNED_IDENTITY 0x00c00000
750#define NV30_3D_RC_FINAL1_F_MAPPING_SIGNED_NEGATE 0x00e00000
751#define NV30_3D_RC_FINAL1_E_INPUT__MASK 0x0f000000
752#define NV30_3D_RC_FINAL1_E_INPUT__SHIFT 24
753#define NV30_3D_RC_FINAL1_E_INPUT_ZERO 0x00000000
754#define NV30_3D_RC_FINAL1_E_INPUT_CONSTANT_COLOR0 0x01000000
755#define NV30_3D_RC_FINAL1_E_INPUT_CONSTANT_COLOR1 0x02000000
756#define NV30_3D_RC_FINAL1_E_INPUT_FOG 0x03000000
757#define NV30_3D_RC_FINAL1_E_INPUT_PRIMARY_COLOR 0x04000000
758#define NV30_3D_RC_FINAL1_E_INPUT_SECONDARY_COLOR 0x05000000
759#define NV30_3D_RC_FINAL1_E_INPUT_TEXTURE0 0x08000000
760#define NV30_3D_RC_FINAL1_E_INPUT_TEXTURE1 0x09000000
761#define NV30_3D_RC_FINAL1_E_INPUT_TEXTURE2 0x0a000000
762#define NV30_3D_RC_FINAL1_E_INPUT_TEXTURE3 0x0b000000
763#define NV30_3D_RC_FINAL1_E_INPUT_SPARE0 0x0c000000
764#define NV30_3D_RC_FINAL1_E_INPUT_SPARE1 0x0d000000
765#define NV30_3D_RC_FINAL1_E_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000
766#define NV30_3D_RC_FINAL1_E_INPUT_E_TIMES_F 0x0f000000
767#define NV30_3D_RC_FINAL1_E_COMPONENT_USAGE__MASK 0x10000000
768#define NV30_3D_RC_FINAL1_E_COMPONENT_USAGE__SHIFT 28
769#define NV30_3D_RC_FINAL1_E_COMPONENT_USAGE_RGB 0x00000000
770#define NV30_3D_RC_FINAL1_E_COMPONENT_USAGE_ALPHA 0x10000000
771#define NV30_3D_RC_FINAL1_E_MAPPING__MASK 0xe0000000
772#define NV30_3D_RC_FINAL1_E_MAPPING__SHIFT 29
773#define NV30_3D_RC_FINAL1_E_MAPPING_UNSIGNED_IDENTITY 0x00000000
774#define NV30_3D_RC_FINAL1_E_MAPPING_UNSIGNED_INVERT 0x20000000
775#define NV30_3D_RC_FINAL1_E_MAPPING_EXPAND_NORMAL 0x40000000
776#define NV30_3D_RC_FINAL1_E_MAPPING_EXPAND_NEGATE 0x60000000
777#define NV30_3D_RC_FINAL1_E_MAPPING_HALF_BIAS_NORMAL 0x80000000
778#define NV30_3D_RC_FINAL1_E_MAPPING_HALF_BIAS_NEGATE 0xa0000000
779#define NV30_3D_RC_FINAL1_E_MAPPING_SIGNED_IDENTITY 0xc0000000
780#define NV30_3D_RC_FINAL1_E_MAPPING_SIGNED_NEGATE 0xe0000000
781
782#define NV30_3D_RC_ENABLE 0x000008fc
783#define NV30_3D_RC_ENABLE_NUM_COMBINERS__MASK 0x0000000f
784#define NV30_3D_RC_ENABLE_NUM_COMBINERS__SHIFT 0
785#define NV30_3D_RC_ENABLE_STAGE_CONSTANT_COLOR0 0x0000f000
786#define NV30_3D_RC_ENABLE_STAGE_CONSTANT_COLOR1 0x000f0000
787
788
789#define NV30_3D_RC_IN_ALPHA(i0) (0x00000900 + 0x20*(i0))
790#define NV30_3D_RC_IN_ALPHA_D_INPUT__MASK 0x0000000f
791#define NV30_3D_RC_IN_ALPHA_D_INPUT__SHIFT 0
792#define NV30_3D_RC_IN_ALPHA_D_INPUT_ZERO 0x00000000
793#define NV30_3D_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR0 0x00000001
794#define NV30_3D_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR1 0x00000002
795#define NV30_3D_RC_IN_ALPHA_D_INPUT_FOG 0x00000003
796#define NV30_3D_RC_IN_ALPHA_D_INPUT_PRIMARY_COLOR 0x00000004
797#define NV30_3D_RC_IN_ALPHA_D_INPUT_SECONDARY_COLOR 0x00000005
798#define NV30_3D_RC_IN_ALPHA_D_INPUT_TEXTURE0 0x00000008
799#define NV30_3D_RC_IN_ALPHA_D_INPUT_TEXTURE1 0x00000009
800#define NV30_3D_RC_IN_ALPHA_D_INPUT_TEXTURE2 0x0000000a
801#define NV30_3D_RC_IN_ALPHA_D_INPUT_TEXTURE3 0x0000000b
802#define NV30_3D_RC_IN_ALPHA_D_INPUT_SPARE0 0x0000000c
803#define NV30_3D_RC_IN_ALPHA_D_INPUT_SPARE1 0x0000000d
804#define NV30_3D_RC_IN_ALPHA_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e
805#define NV30_3D_RC_IN_ALPHA_D_INPUT_E_TIMES_F 0x0000000f
806#define NV30_3D_RC_IN_ALPHA_D_COMPONENT_USAGE__MASK 0x00000010
807#define NV30_3D_RC_IN_ALPHA_D_COMPONENT_USAGE__SHIFT 4
808#define NV30_3D_RC_IN_ALPHA_D_COMPONENT_USAGE_BLUE 0x00000000
809#define NV30_3D_RC_IN_ALPHA_D_COMPONENT_USAGE_ALPHA 0x00000010
810#define NV30_3D_RC_IN_ALPHA_D_MAPPING__MASK 0x000000e0
811#define NV30_3D_RC_IN_ALPHA_D_MAPPING__SHIFT 5
812#define NV30_3D_RC_IN_ALPHA_D_MAPPING_UNSIGNED_IDENTITY 0x00000000
813#define NV30_3D_RC_IN_ALPHA_D_MAPPING_UNSIGNED_INVERT 0x00000020
814#define NV30_3D_RC_IN_ALPHA_D_MAPPING_EXPAND_NORMAL 0x00000040
815#define NV30_3D_RC_IN_ALPHA_D_MAPPING_EXPAND_NEGATE 0x00000060
816#define NV30_3D_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NORMAL 0x00000080
817#define NV30_3D_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NEGATE 0x000000a0
818#define NV30_3D_RC_IN_ALPHA_D_MAPPING_SIGNED_IDENTITY 0x000000c0
819#define NV30_3D_RC_IN_ALPHA_D_MAPPING_SIGNED_NEGATE 0x000000e0
820#define NV30_3D_RC_IN_ALPHA_C_INPUT__MASK 0x00000f00
821#define NV30_3D_RC_IN_ALPHA_C_INPUT__SHIFT 8
822#define NV30_3D_RC_IN_ALPHA_C_INPUT_ZERO 0x00000000
823#define NV30_3D_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR0 0x00000100
824#define NV30_3D_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR1 0x00000200
825#define NV30_3D_RC_IN_ALPHA_C_INPUT_FOG 0x00000300
826#define NV30_3D_RC_IN_ALPHA_C_INPUT_PRIMARY_COLOR 0x00000400
827#define NV30_3D_RC_IN_ALPHA_C_INPUT_SECONDARY_COLOR 0x00000500
828#define NV30_3D_RC_IN_ALPHA_C_INPUT_TEXTURE0 0x00000800
829#define NV30_3D_RC_IN_ALPHA_C_INPUT_TEXTURE1 0x00000900
830#define NV30_3D_RC_IN_ALPHA_C_INPUT_TEXTURE2 0x00000a00
831#define NV30_3D_RC_IN_ALPHA_C_INPUT_TEXTURE3 0x00000b00
832#define NV30_3D_RC_IN_ALPHA_C_INPUT_SPARE0 0x00000c00
833#define NV30_3D_RC_IN_ALPHA_C_INPUT_SPARE1 0x00000d00
834#define NV30_3D_RC_IN_ALPHA_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00
835#define NV30_3D_RC_IN_ALPHA_C_INPUT_E_TIMES_F 0x00000f00
836#define NV30_3D_RC_IN_ALPHA_C_COMPONENT_USAGE__MASK 0x00001000
837#define NV30_3D_RC_IN_ALPHA_C_COMPONENT_USAGE__SHIFT 12
838#define NV30_3D_RC_IN_ALPHA_C_COMPONENT_USAGE_BLUE 0x00000000
839#define NV30_3D_RC_IN_ALPHA_C_COMPONENT_USAGE_ALPHA 0x00001000
840#define NV30_3D_RC_IN_ALPHA_C_MAPPING__MASK 0x0000e000
841#define NV30_3D_RC_IN_ALPHA_C_MAPPING__SHIFT 13
842#define NV30_3D_RC_IN_ALPHA_C_MAPPING_UNSIGNED_IDENTITY 0x00000000
843#define NV30_3D_RC_IN_ALPHA_C_MAPPING_UNSIGNED_INVERT 0x00002000
844#define NV30_3D_RC_IN_ALPHA_C_MAPPING_EXPAND_NORMAL 0x00004000
845#define NV30_3D_RC_IN_ALPHA_C_MAPPING_EXPAND_NEGATE 0x00006000
846#define NV30_3D_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NORMAL 0x00008000
847#define NV30_3D_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NEGATE 0x0000a000
848#define NV30_3D_RC_IN_ALPHA_C_MAPPING_SIGNED_IDENTITY 0x0000c000
849#define NV30_3D_RC_IN_ALPHA_C_MAPPING_SIGNED_NEGATE 0x0000e000
850#define NV30_3D_RC_IN_ALPHA_B_INPUT__MASK 0x000f0000
851#define NV30_3D_RC_IN_ALPHA_B_INPUT__SHIFT 16
852#define NV30_3D_RC_IN_ALPHA_B_INPUT_ZERO 0x00000000
853#define NV30_3D_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR0 0x00010000
854#define NV30_3D_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR1 0x00020000
855#define NV30_3D_RC_IN_ALPHA_B_INPUT_FOG 0x00030000
856#define NV30_3D_RC_IN_ALPHA_B_INPUT_PRIMARY_COLOR 0x00040000
857#define NV30_3D_RC_IN_ALPHA_B_INPUT_SECONDARY_COLOR 0x00050000
858#define NV30_3D_RC_IN_ALPHA_B_INPUT_TEXTURE0 0x00080000
859#define NV30_3D_RC_IN_ALPHA_B_INPUT_TEXTURE1 0x00090000
860#define NV30_3D_RC_IN_ALPHA_B_INPUT_TEXTURE2 0x000a0000
861#define NV30_3D_RC_IN_ALPHA_B_INPUT_TEXTURE3 0x000b0000
862#define NV30_3D_RC_IN_ALPHA_B_INPUT_SPARE0 0x000c0000
863#define NV30_3D_RC_IN_ALPHA_B_INPUT_SPARE1 0x000d0000
864#define NV30_3D_RC_IN_ALPHA_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000
865#define NV30_3D_RC_IN_ALPHA_B_INPUT_E_TIMES_F 0x000f0000
866#define NV30_3D_RC_IN_ALPHA_B_COMPONENT_USAGE__MASK 0x00100000
867#define NV30_3D_RC_IN_ALPHA_B_COMPONENT_USAGE__SHIFT 20
868#define NV30_3D_RC_IN_ALPHA_B_COMPONENT_USAGE_BLUE 0x00000000
869#define NV30_3D_RC_IN_ALPHA_B_COMPONENT_USAGE_ALPHA 0x00100000
870#define NV30_3D_RC_IN_ALPHA_B_MAPPING__MASK 0x00e00000
871#define NV30_3D_RC_IN_ALPHA_B_MAPPING__SHIFT 21
872#define NV30_3D_RC_IN_ALPHA_B_MAPPING_UNSIGNED_IDENTITY 0x00000000
873#define NV30_3D_RC_IN_ALPHA_B_MAPPING_UNSIGNED_INVERT 0x00200000
874#define NV30_3D_RC_IN_ALPHA_B_MAPPING_EXPAND_NORMAL 0x00400000
875#define NV30_3D_RC_IN_ALPHA_B_MAPPING_EXPAND_NEGATE 0x00600000
876#define NV30_3D_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NORMAL 0x00800000
877#define NV30_3D_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NEGATE 0x00a00000
878#define NV30_3D_RC_IN_ALPHA_B_MAPPING_SIGNED_IDENTITY 0x00c00000
879#define NV30_3D_RC_IN_ALPHA_B_MAPPING_SIGNED_NEGATE 0x00e00000
880#define NV30_3D_RC_IN_ALPHA_A_INPUT__MASK 0x0f000000
881#define NV30_3D_RC_IN_ALPHA_A_INPUT__SHIFT 24
882#define NV30_3D_RC_IN_ALPHA_A_INPUT_ZERO 0x00000000
883#define NV30_3D_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR0 0x01000000
884#define NV30_3D_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR1 0x02000000
885#define NV30_3D_RC_IN_ALPHA_A_INPUT_FOG 0x03000000
886#define NV30_3D_RC_IN_ALPHA_A_INPUT_PRIMARY_COLOR 0x04000000
887#define NV30_3D_RC_IN_ALPHA_A_INPUT_SECONDARY_COLOR 0x05000000
888#define NV30_3D_RC_IN_ALPHA_A_INPUT_TEXTURE0 0x08000000
889#define NV30_3D_RC_IN_ALPHA_A_INPUT_TEXTURE1 0x09000000
890#define NV30_3D_RC_IN_ALPHA_A_INPUT_TEXTURE2 0x0a000000
891#define NV30_3D_RC_IN_ALPHA_A_INPUT_TEXTURE3 0x0b000000
892#define NV30_3D_RC_IN_ALPHA_A_INPUT_SPARE0 0x0c000000
893#define NV30_3D_RC_IN_ALPHA_A_INPUT_SPARE1 0x0d000000
894#define NV30_3D_RC_IN_ALPHA_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000
895#define NV30_3D_RC_IN_ALPHA_A_INPUT_E_TIMES_F 0x0f000000
896#define NV30_3D_RC_IN_ALPHA_A_COMPONENT_USAGE__MASK 0x10000000
897#define NV30_3D_RC_IN_ALPHA_A_COMPONENT_USAGE__SHIFT 28
898#define NV30_3D_RC_IN_ALPHA_A_COMPONENT_USAGE_BLUE 0x00000000
899#define NV30_3D_RC_IN_ALPHA_A_COMPONENT_USAGE_ALPHA 0x10000000
900#define NV30_3D_RC_IN_ALPHA_A_MAPPING__MASK 0xe0000000
901#define NV30_3D_RC_IN_ALPHA_A_MAPPING__SHIFT 29
902#define NV30_3D_RC_IN_ALPHA_A_MAPPING_UNSIGNED_IDENTITY 0x00000000
903#define NV30_3D_RC_IN_ALPHA_A_MAPPING_UNSIGNED_INVERT 0x20000000
904#define NV30_3D_RC_IN_ALPHA_A_MAPPING_EXPAND_NORMAL 0x40000000
905#define NV30_3D_RC_IN_ALPHA_A_MAPPING_EXPAND_NEGATE 0x60000000
906#define NV30_3D_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NORMAL 0x80000000
907#define NV30_3D_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NEGATE 0xa0000000
908#define NV30_3D_RC_IN_ALPHA_A_MAPPING_SIGNED_IDENTITY 0xc0000000
909#define NV30_3D_RC_IN_ALPHA_A_MAPPING_SIGNED_NEGATE 0xe0000000
910
911#define NV30_3D_RC_IN_RGB(i0) (0x00000904 + 0x20*(i0))
912#define NV30_3D_RC_IN_RGB_D_INPUT__MASK 0x0000000f
913#define NV30_3D_RC_IN_RGB_D_INPUT__SHIFT 0
914#define NV30_3D_RC_IN_RGB_D_INPUT_ZERO 0x00000000
915#define NV30_3D_RC_IN_RGB_D_INPUT_CONSTANT_COLOR0 0x00000001
916#define NV30_3D_RC_IN_RGB_D_INPUT_CONSTANT_COLOR1 0x00000002
917#define NV30_3D_RC_IN_RGB_D_INPUT_FOG 0x00000003
918#define NV30_3D_RC_IN_RGB_D_INPUT_PRIMARY_COLOR 0x00000004
919#define NV30_3D_RC_IN_RGB_D_INPUT_SECONDARY_COLOR 0x00000005
920#define NV30_3D_RC_IN_RGB_D_INPUT_TEXTURE0 0x00000008
921#define NV30_3D_RC_IN_RGB_D_INPUT_TEXTURE1 0x00000009
922#define NV30_3D_RC_IN_RGB_D_INPUT_TEXTURE2 0x0000000a
923#define NV30_3D_RC_IN_RGB_D_INPUT_TEXTURE3 0x0000000b
924#define NV30_3D_RC_IN_RGB_D_INPUT_SPARE0 0x0000000c
925#define NV30_3D_RC_IN_RGB_D_INPUT_SPARE1 0x0000000d
926#define NV30_3D_RC_IN_RGB_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e
927#define NV30_3D_RC_IN_RGB_D_INPUT_E_TIMES_F 0x0000000f
928#define NV30_3D_RC_IN_RGB_D_COMPONENT_USAGE__MASK 0x00000010
929#define NV30_3D_RC_IN_RGB_D_COMPONENT_USAGE__SHIFT 4
930#define NV30_3D_RC_IN_RGB_D_COMPONENT_USAGE_RGB 0x00000000
931#define NV30_3D_RC_IN_RGB_D_COMPONENT_USAGE_ALPHA 0x00000010
932#define NV30_3D_RC_IN_RGB_D_MAPPING__MASK 0x000000e0
933#define NV30_3D_RC_IN_RGB_D_MAPPING__SHIFT 5
934#define NV30_3D_RC_IN_RGB_D_MAPPING_UNSIGNED_IDENTITY 0x00000000
935#define NV30_3D_RC_IN_RGB_D_MAPPING_UNSIGNED_INVERT 0x00000020
936#define NV30_3D_RC_IN_RGB_D_MAPPING_EXPAND_NORMAL 0x00000040
937#define NV30_3D_RC_IN_RGB_D_MAPPING_EXPAND_NEGATE 0x00000060
938#define NV30_3D_RC_IN_RGB_D_MAPPING_HALF_BIAS_NORMAL 0x00000080
939#define NV30_3D_RC_IN_RGB_D_MAPPING_HALF_BIAS_NEGATE 0x000000a0
940#define NV30_3D_RC_IN_RGB_D_MAPPING_SIGNED_IDENTITY 0x000000c0
941#define NV30_3D_RC_IN_RGB_D_MAPPING_SIGNED_NEGATE 0x000000e0
942#define NV30_3D_RC_IN_RGB_C_INPUT__MASK 0x00000f00
943#define NV30_3D_RC_IN_RGB_C_INPUT__SHIFT 8
944#define NV30_3D_RC_IN_RGB_C_INPUT_ZERO 0x00000000
945#define NV30_3D_RC_IN_RGB_C_INPUT_CONSTANT_COLOR0 0x00000100
946#define NV30_3D_RC_IN_RGB_C_INPUT_CONSTANT_COLOR1 0x00000200
947#define NV30_3D_RC_IN_RGB_C_INPUT_FOG 0x00000300
948#define NV30_3D_RC_IN_RGB_C_INPUT_PRIMARY_COLOR 0x00000400
949#define NV30_3D_RC_IN_RGB_C_INPUT_SECONDARY_COLOR 0x00000500
950#define NV30_3D_RC_IN_RGB_C_INPUT_TEXTURE0 0x00000800
951#define NV30_3D_RC_IN_RGB_C_INPUT_TEXTURE1 0x00000900
952#define NV30_3D_RC_IN_RGB_C_INPUT_TEXTURE2 0x00000a00
953#define NV30_3D_RC_IN_RGB_C_INPUT_TEXTURE3 0x00000b00
954#define NV30_3D_RC_IN_RGB_C_INPUT_SPARE0 0x00000c00
955#define NV30_3D_RC_IN_RGB_C_INPUT_SPARE1 0x00000d00
956#define NV30_3D_RC_IN_RGB_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00
957#define NV30_3D_RC_IN_RGB_C_INPUT_E_TIMES_F 0x00000f00
958#define NV30_3D_RC_IN_RGB_C_COMPONENT_USAGE__MASK 0x00001000
959#define NV30_3D_RC_IN_RGB_C_COMPONENT_USAGE__SHIFT 12
960#define NV30_3D_RC_IN_RGB_C_COMPONENT_USAGE_RGB 0x00000000
961#define NV30_3D_RC_IN_RGB_C_COMPONENT_USAGE_ALPHA 0x00001000
962#define NV30_3D_RC_IN_RGB_C_MAPPING__MASK 0x0000e000
963#define NV30_3D_RC_IN_RGB_C_MAPPING__SHIFT 13
964#define NV30_3D_RC_IN_RGB_C_MAPPING_UNSIGNED_IDENTITY 0x00000000
965#define NV30_3D_RC_IN_RGB_C_MAPPING_UNSIGNED_INVERT 0x00002000
966#define NV30_3D_RC_IN_RGB_C_MAPPING_EXPAND_NORMAL 0x00004000
967#define NV30_3D_RC_IN_RGB_C_MAPPING_EXPAND_NEGATE 0x00006000
968#define NV30_3D_RC_IN_RGB_C_MAPPING_HALF_BIAS_NORMAL 0x00008000
969#define NV30_3D_RC_IN_RGB_C_MAPPING_HALF_BIAS_NEGATE 0x0000a000
970#define NV30_3D_RC_IN_RGB_C_MAPPING_SIGNED_IDENTITY 0x0000c000
971#define NV30_3D_RC_IN_RGB_C_MAPPING_SIGNED_NEGATE 0x0000e000
972#define NV30_3D_RC_IN_RGB_B_INPUT__MASK 0x000f0000
973#define NV30_3D_RC_IN_RGB_B_INPUT__SHIFT 16
974#define NV30_3D_RC_IN_RGB_B_INPUT_ZERO 0x00000000
975#define NV30_3D_RC_IN_RGB_B_INPUT_CONSTANT_COLOR0 0x00010000
976#define NV30_3D_RC_IN_RGB_B_INPUT_CONSTANT_COLOR1 0x00020000
977#define NV30_3D_RC_IN_RGB_B_INPUT_FOG 0x00030000
978#define NV30_3D_RC_IN_RGB_B_INPUT_PRIMARY_COLOR 0x00040000
979#define NV30_3D_RC_IN_RGB_B_INPUT_SECONDARY_COLOR 0x00050000
980#define NV30_3D_RC_IN_RGB_B_INPUT_TEXTURE0 0x00080000
981#define NV30_3D_RC_IN_RGB_B_INPUT_TEXTURE1 0x00090000
982#define NV30_3D_RC_IN_RGB_B_INPUT_TEXTURE2 0x000a0000
983#define NV30_3D_RC_IN_RGB_B_INPUT_TEXTURE3 0x000b0000
984#define NV30_3D_RC_IN_RGB_B_INPUT_SPARE0 0x000c0000
985#define NV30_3D_RC_IN_RGB_B_INPUT_SPARE1 0x000d0000
986#define NV30_3D_RC_IN_RGB_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000
987#define NV30_3D_RC_IN_RGB_B_INPUT_E_TIMES_F 0x000f0000
988#define NV30_3D_RC_IN_RGB_B_COMPONENT_USAGE__MASK 0x00100000
989#define NV30_3D_RC_IN_RGB_B_COMPONENT_USAGE__SHIFT 20
990#define NV30_3D_RC_IN_RGB_B_COMPONENT_USAGE_RGB 0x00000000
991#define NV30_3D_RC_IN_RGB_B_COMPONENT_USAGE_ALPHA 0x00100000
992#define NV30_3D_RC_IN_RGB_B_MAPPING__MASK 0x00e00000
993#define NV30_3D_RC_IN_RGB_B_MAPPING__SHIFT 21
994#define NV30_3D_RC_IN_RGB_B_MAPPING_UNSIGNED_IDENTITY 0x00000000
995#define NV30_3D_RC_IN_RGB_B_MAPPING_UNSIGNED_INVERT 0x00200000
996#define NV30_3D_RC_IN_RGB_B_MAPPING_EXPAND_NORMAL 0x00400000
997#define NV30_3D_RC_IN_RGB_B_MAPPING_EXPAND_NEGATE 0x00600000
998#define NV30_3D_RC_IN_RGB_B_MAPPING_HALF_BIAS_NORMAL 0x00800000
999#define NV30_3D_RC_IN_RGB_B_MAPPING_HALF_BIAS_NEGATE 0x00a00000
1000#define NV30_3D_RC_IN_RGB_B_MAPPING_SIGNED_IDENTITY 0x00c00000
1001#define NV30_3D_RC_IN_RGB_B_MAPPING_SIGNED_NEGATE 0x00e00000
1002#define NV30_3D_RC_IN_RGB_A_INPUT__MASK 0x0f000000
1003#define NV30_3D_RC_IN_RGB_A_INPUT__SHIFT 24
1004#define NV30_3D_RC_IN_RGB_A_INPUT_ZERO 0x00000000
1005#define NV30_3D_RC_IN_RGB_A_INPUT_CONSTANT_COLOR0 0x01000000
1006#define NV30_3D_RC_IN_RGB_A_INPUT_CONSTANT_COLOR1 0x02000000
1007#define NV30_3D_RC_IN_RGB_A_INPUT_FOG 0x03000000
1008#define NV30_3D_RC_IN_RGB_A_INPUT_PRIMARY_COLOR 0x04000000
1009#define NV30_3D_RC_IN_RGB_A_INPUT_SECONDARY_COLOR 0x05000000
1010#define NV30_3D_RC_IN_RGB_A_INPUT_TEXTURE0 0x08000000
1011#define NV30_3D_RC_IN_RGB_A_INPUT_TEXTURE1 0x09000000
1012#define NV30_3D_RC_IN_RGB_A_INPUT_TEXTURE2 0x0a000000
1013#define NV30_3D_RC_IN_RGB_A_INPUT_TEXTURE3 0x0b000000
1014#define NV30_3D_RC_IN_RGB_A_INPUT_SPARE0 0x0c000000
1015#define NV30_3D_RC_IN_RGB_A_INPUT_SPARE1 0x0d000000
1016#define NV30_3D_RC_IN_RGB_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000
1017#define NV30_3D_RC_IN_RGB_A_INPUT_E_TIMES_F 0x0f000000
1018#define NV30_3D_RC_IN_RGB_A_COMPONENT_USAGE__MASK 0x10000000
1019#define NV30_3D_RC_IN_RGB_A_COMPONENT_USAGE__SHIFT 28
1020#define NV30_3D_RC_IN_RGB_A_COMPONENT_USAGE_RGB 0x00000000
1021#define NV30_3D_RC_IN_RGB_A_COMPONENT_USAGE_ALPHA 0x10000000
1022#define NV30_3D_RC_IN_RGB_A_MAPPING__MASK 0xe0000000
1023#define NV30_3D_RC_IN_RGB_A_MAPPING__SHIFT 29
1024#define NV30_3D_RC_IN_RGB_A_MAPPING_UNSIGNED_IDENTITY 0x00000000
1025#define NV30_3D_RC_IN_RGB_A_MAPPING_UNSIGNED_INVERT 0x20000000
1026#define NV30_3D_RC_IN_RGB_A_MAPPING_EXPAND_NORMAL 0x40000000
1027#define NV30_3D_RC_IN_RGB_A_MAPPING_EXPAND_NEGATE 0x60000000
1028#define NV30_3D_RC_IN_RGB_A_MAPPING_HALF_BIAS_NORMAL 0x80000000
1029#define NV30_3D_RC_IN_RGB_A_MAPPING_HALF_BIAS_NEGATE 0xa0000000
1030#define NV30_3D_RC_IN_RGB_A_MAPPING_SIGNED_IDENTITY 0xc0000000
1031#define NV30_3D_RC_IN_RGB_A_MAPPING_SIGNED_NEGATE 0xe0000000
1032
1033#define NV30_3D_RC_CONSTANT_COLOR0(i0) (0x00000908 + 0x20*(i0))
1034#define NV30_3D_RC_CONSTANT_COLOR0_B__MASK 0x000000ff
1035#define NV30_3D_RC_CONSTANT_COLOR0_B__SHIFT 0
1036#define NV30_3D_RC_CONSTANT_COLOR0_G__MASK 0x0000ff00
1037#define NV30_3D_RC_CONSTANT_COLOR0_G__SHIFT 8
1038#define NV30_3D_RC_CONSTANT_COLOR0_R__MASK 0x00ff0000
1039#define NV30_3D_RC_CONSTANT_COLOR0_R__SHIFT 16
1040#define NV30_3D_RC_CONSTANT_COLOR0_A__MASK 0xff000000
1041#define NV30_3D_RC_CONSTANT_COLOR0_A__SHIFT 24
1042
1043#define NV30_3D_RC_CONSTANT_COLOR1(i0) (0x0000090c + 0x20*(i0))
1044#define NV30_3D_RC_CONSTANT_COLOR1_B__MASK 0x000000ff
1045#define NV30_3D_RC_CONSTANT_COLOR1_B__SHIFT 0
1046#define NV30_3D_RC_CONSTANT_COLOR1_G__MASK 0x0000ff00
1047#define NV30_3D_RC_CONSTANT_COLOR1_G__SHIFT 8
1048#define NV30_3D_RC_CONSTANT_COLOR1_R__MASK 0x00ff0000
1049#define NV30_3D_RC_CONSTANT_COLOR1_R__SHIFT 16
1050#define NV30_3D_RC_CONSTANT_COLOR1_A__MASK 0xff000000
1051#define NV30_3D_RC_CONSTANT_COLOR1_A__SHIFT 24
1052
1053#define NV30_3D_RC_OUT_ALPHA(i0) (0x00000910 + 0x20*(i0))
1054#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT__MASK 0x0000000f
1055#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT__SHIFT 0
1056#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_ZERO 0x00000000
1057#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR0 0x00000001
1058#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR1 0x00000002
1059#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_FOG 0x00000003
1060#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_PRIMARY_COLOR 0x00000004
1061#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_SECONDARY_COLOR 0x00000005
1062#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE0 0x00000008
1063#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE1 0x00000009
1064#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE2 0x0000000a
1065#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE3 0x0000000b
1066#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_SPARE0 0x0000000c
1067#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_SPARE1 0x0000000d
1068#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e
1069#define NV30_3D_RC_OUT_ALPHA_CD_OUTPUT_E_TIMES_F 0x0000000f
1070#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT__MASK 0x000000f0
1071#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT__SHIFT 4
1072#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_ZERO 0x00000000
1073#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR0 0x00000010
1074#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR1 0x00000020
1075#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_FOG 0x00000030
1076#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_PRIMARY_COLOR 0x00000040
1077#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_SECONDARY_COLOR 0x00000050
1078#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE0 0x00000080
1079#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE1 0x00000090
1080#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE2 0x000000a0
1081#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE3 0x000000b0
1082#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_SPARE0 0x000000c0
1083#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_SPARE1 0x000000d0
1084#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000000e0
1085#define NV30_3D_RC_OUT_ALPHA_AB_OUTPUT_E_TIMES_F 0x000000f0
1086#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT__MASK 0x00000f00
1087#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT__SHIFT 8
1088#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_ZERO 0x00000000
1089#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR0 0x00000100
1090#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR1 0x00000200
1091#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_FOG 0x00000300
1092#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_PRIMARY_COLOR 0x00000400
1093#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_SECONDARY_COLOR 0x00000500
1094#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE0 0x00000800
1095#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE1 0x00000900
1096#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE2 0x00000a00
1097#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE3 0x00000b00
1098#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0 0x00000c00
1099#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_SPARE1 0x00000d00
1100#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00
1101#define NV30_3D_RC_OUT_ALPHA_SUM_OUTPUT_E_TIMES_F 0x00000f00
1102#define NV30_3D_RC_OUT_ALPHA_CD_DOT_PRODUCT 0x00001000
1103#define NV30_3D_RC_OUT_ALPHA_AB_DOT_PRODUCT 0x00002000
1104#define NV30_3D_RC_OUT_ALPHA_MUX_SUM 0x00004000
1105#define NV30_3D_RC_OUT_ALPHA_BIAS__MASK 0x00008000
1106#define NV30_3D_RC_OUT_ALPHA_BIAS__SHIFT 15
1107#define NV30_3D_RC_OUT_ALPHA_BIAS_NONE 0x00000000
1108#define NV30_3D_RC_OUT_ALPHA_BIAS_BIAS_BY_NEGATIVE_ONE_HALF 0x00008000
1109#define NV30_3D_RC_OUT_ALPHA_SCALE__MASK 0x00030000
1110#define NV30_3D_RC_OUT_ALPHA_SCALE__SHIFT 16
1111#define NV30_3D_RC_OUT_ALPHA_SCALE_NONE 0x00000000
1112#define NV30_3D_RC_OUT_ALPHA_SCALE_SCALE_BY_TWO 0x00010000
1113#define NV30_3D_RC_OUT_ALPHA_SCALE_SCALE_BY_FOUR 0x00020000
1114#define NV30_3D_RC_OUT_ALPHA_SCALE_SCALE_BY_ONE_HALF 0x00030000
1115
1116#define NV30_3D_RC_OUT_RGB(i0) (0x00000914 + 0x20*(i0))
1117#define NV30_3D_RC_OUT_RGB_CD_OUTPUT__MASK 0x0000000f
1118#define NV30_3D_RC_OUT_RGB_CD_OUTPUT__SHIFT 0
1119#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_ZERO 0x00000000
1120#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR0 0x00000001
1121#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR1 0x00000002
1122#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_FOG 0x00000003
1123#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_PRIMARY_COLOR 0x00000004
1124#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_SECONDARY_COLOR 0x00000005
1125#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_TEXTURE0 0x00000008
1126#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_TEXTURE1 0x00000009
1127#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_TEXTURE2 0x0000000a
1128#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_TEXTURE3 0x0000000b
1129#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_SPARE0 0x0000000c
1130#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_SPARE1 0x0000000d
1131#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e
1132#define NV30_3D_RC_OUT_RGB_CD_OUTPUT_E_TIMES_F 0x0000000f
1133#define NV30_3D_RC_OUT_RGB_AB_OUTPUT__MASK 0x000000f0
1134#define NV30_3D_RC_OUT_RGB_AB_OUTPUT__SHIFT 4
1135#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_ZERO 0x00000000
1136#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR0 0x00000010
1137#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR1 0x00000020
1138#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_FOG 0x00000030
1139#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_PRIMARY_COLOR 0x00000040
1140#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_SECONDARY_COLOR 0x00000050
1141#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_TEXTURE0 0x00000080
1142#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_TEXTURE1 0x00000090
1143#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_TEXTURE2 0x000000a0
1144#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_TEXTURE3 0x000000b0
1145#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_SPARE0 0x000000c0
1146#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_SPARE1 0x000000d0
1147#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000000e0
1148#define NV30_3D_RC_OUT_RGB_AB_OUTPUT_E_TIMES_F 0x000000f0
1149#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT__MASK 0x00000f00
1150#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT__SHIFT 8
1151#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_ZERO 0x00000000
1152#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR0 0x00000100
1153#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR1 0x00000200
1154#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_FOG 0x00000300
1155#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_PRIMARY_COLOR 0x00000400
1156#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_SECONDARY_COLOR 0x00000500
1157#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_TEXTURE0 0x00000800
1158#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_TEXTURE1 0x00000900
1159#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_TEXTURE2 0x00000a00
1160#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_TEXTURE3 0x00000b00
1161#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE0 0x00000c00
1162#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE1 0x00000d00
1163#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00
1164#define NV30_3D_RC_OUT_RGB_SUM_OUTPUT_E_TIMES_F 0x00000f00
1165#define NV30_3D_RC_OUT_RGB_CD_DOT_PRODUCT 0x00001000
1166#define NV30_3D_RC_OUT_RGB_AB_DOT_PRODUCT 0x00002000
1167#define NV30_3D_RC_OUT_RGB_MUX_SUM 0x00004000
1168#define NV30_3D_RC_OUT_RGB_BIAS__MASK 0x00008000
1169#define NV30_3D_RC_OUT_RGB_BIAS__SHIFT 15
1170#define NV30_3D_RC_OUT_RGB_BIAS_NONE 0x00000000
1171#define NV30_3D_RC_OUT_RGB_BIAS_BIAS_BY_NEGATIVE_ONE_HALF 0x00008000
1172#define NV30_3D_RC_OUT_RGB_SCALE__MASK 0x00030000
1173#define NV30_3D_RC_OUT_RGB_SCALE__SHIFT 16
1174#define NV30_3D_RC_OUT_RGB_SCALE_NONE 0x00000000
1175#define NV30_3D_RC_OUT_RGB_SCALE_SCALE_BY_TWO 0x00010000
1176#define NV30_3D_RC_OUT_RGB_SCALE_SCALE_BY_FOUR 0x00020000
1177#define NV30_3D_RC_OUT_RGB_SCALE_SCALE_BY_ONE_HALF 0x00030000
1178
1179#define NV30_3D_VIEWPORT_HORIZ 0x00000a00
1180#define NV30_3D_VIEWPORT_HORIZ_X__MASK 0x0000ffff
1181#define NV30_3D_VIEWPORT_HORIZ_X__SHIFT 0
1182#define NV30_3D_VIEWPORT_HORIZ_W__MASK 0xffff0000
1183#define NV30_3D_VIEWPORT_HORIZ_W__SHIFT 16
1184
1185#define NV30_3D_VIEWPORT_VERT 0x00000a04
1186#define NV30_3D_VIEWPORT_VERT_Y__MASK 0x0000ffff
1187#define NV30_3D_VIEWPORT_VERT_Y__SHIFT 0
1188#define NV30_3D_VIEWPORT_VERT_H__MASK 0xffff0000
1189#define NV30_3D_VIEWPORT_VERT_H__SHIFT 16
1190
1191#define NV30_3D_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION 0x00000a10
1192
1193
1194#define NV30_3D_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_R 0x00000a10
1195
1196#define NV30_3D_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_G 0x00000a14
1197
1198#define NV30_3D_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_B 0x00000a18
1199
1200#define NV30_3D_VIEWPORT_TRANSLATE 0x00000a20
1201
1202
1203#define NV30_3D_VIEWPORT_TRANSLATE_X 0x00000a20
1204
1205#define NV30_3D_VIEWPORT_TRANSLATE_Y 0x00000a24
1206
1207#define NV30_3D_VIEWPORT_TRANSLATE_Z 0x00000a28
1208
1209#define NV30_3D_VIEWPORT_TRANSLATE_W 0x00000a2c
1210
1211#define NV30_3D_VIEWPORT_SCALE 0x00000a30
1212
1213
1214#define NV30_3D_VIEWPORT_SCALE_X 0x00000a30
1215
1216#define NV30_3D_VIEWPORT_SCALE_Y 0x00000a34
1217
1218#define NV30_3D_VIEWPORT_SCALE_Z 0x00000a38
1219
1220#define NV30_3D_VIEWPORT_SCALE_W 0x00000a3c
1221
1222#define NV30_3D_POLYGON_OFFSET_POINT_ENABLE 0x00000a60
1223
1224#define NV30_3D_POLYGON_OFFSET_LINE_ENABLE 0x00000a64
1225
1226#define NV30_3D_POLYGON_OFFSET_FILL_ENABLE 0x00000a68
1227
1228#define NV30_3D_DEPTH_FUNC 0x00000a6c
1229#define NV30_3D_DEPTH_FUNC_NEVER 0x00000200
1230#define NV30_3D_DEPTH_FUNC_LESS 0x00000201
1231#define NV30_3D_DEPTH_FUNC_EQUAL 0x00000202
1232#define NV30_3D_DEPTH_FUNC_LEQUAL 0x00000203
1233#define NV30_3D_DEPTH_FUNC_GREATER 0x00000204
1234#define NV30_3D_DEPTH_FUNC_NOTEQUAL 0x00000205
1235#define NV30_3D_DEPTH_FUNC_GEQUAL 0x00000206
1236#define NV30_3D_DEPTH_FUNC_ALWAYS 0x00000207
1237
1238#define NV30_3D_DEPTH_WRITE_ENABLE 0x00000a70
1239
1240#define NV30_3D_DEPTH_TEST_ENABLE 0x00000a74
1241
1242#define NV30_3D_POLYGON_OFFSET_FACTOR 0x00000a78
1243
1244#define NV30_3D_POLYGON_OFFSET_UNITS 0x00000a7c
1245
1246#define NV30_3D_VTX_ATTR_3I_XY(i0) (0x00000a80 + 0x8*(i0))
1247#define NV30_3D_VTX_ATTR_3I_XY__ESIZE 0x00000008
1248#define NV30_3D_VTX_ATTR_3I_XY__LEN 0x00000010
1249#define NV30_3D_VTX_ATTR_3I_XY_X__MASK 0x0000ffff
1250#define NV30_3D_VTX_ATTR_3I_XY_X__SHIFT 0
1251#define NV30_3D_VTX_ATTR_3I_XY_Y__MASK 0xffff0000
1252#define NV30_3D_VTX_ATTR_3I_XY_Y__SHIFT 16
1253
1254#define NV30_3D_VTX_ATTR_3I_Z(i0) (0x00000a84 + 0x8*(i0))
1255#define NV30_3D_VTX_ATTR_3I_Z__ESIZE 0x00000008
1256#define NV30_3D_VTX_ATTR_3I_Z__LEN 0x00000010
1257#define NV30_3D_VTX_ATTR_3I_Z_Z__MASK 0x0000ffff
1258#define NV30_3D_VTX_ATTR_3I_Z_Z__SHIFT 0
1259
1260#define NV30_3D_TEX_FILTER_OPTIMIZATION(i0) (0x00000b00 + 0x4*(i0))
1261#define NV30_3D_TEX_FILTER_OPTIMIZATION__ESIZE 0x00000004
1262#define NV30_3D_TEX_FILTER_OPTIMIZATION__LEN 0x00000004
1263#define NV40_3D_TEX_FILTER_OPTIMIZATION_TRILINEAR__MASK 0x0000001f
1264#define NV40_3D_TEX_FILTER_OPTIMIZATION_TRILINEAR__SHIFT 0
1265#define NV40_3D_TEX_FILTER_OPTIMIZATION_TRILINEAR_OFF 0x00000000
1266#define NV40_3D_TEX_FILTER_OPTIMIZATION_TRILINEAR_HIGH_QUALITY 0x00000004
1267#define NV40_3D_TEX_FILTER_OPTIMIZATION_TRILINEAR_QUALITY 0x00000006
1268#define NV40_3D_TEX_FILTER_OPTIMIZATION_TRILINEAR_PERFORMANCE 0x00000008
1269#define NV40_3D_TEX_FILTER_OPTIMIZATION_TRILINEAR_HIGH_PERFORMANCE 0x00000018
1270#define NV40_3D_TEX_FILTER_OPTIMIZATION_ANISO_SAMPLE__MASK 0x000001c0
1271#define NV40_3D_TEX_FILTER_OPTIMIZATION_ANISO_SAMPLE__SHIFT 6
1272#define NV40_3D_TEX_FILTER_OPTIMIZATION_ANISO_SAMPLE_OFF 0x00000000
1273#define NV40_3D_TEX_FILTER_OPTIMIZATION_ANISO_SAMPLE_HIGH_QUALITY 0x000000c0
1274#define NV40_3D_TEX_FILTER_OPTIMIZATION_ANISO_SAMPLE_QUALITY 0x000001c0
1275#define NV40_3D_TEX_FILTER_OPTIMIZATION_ANISO_SAMPLE_PERFORMANCE 0x00000140
1276#define NV40_3D_TEX_FILTER_OPTIMIZATION_UNKNOWN__MASK 0x00007c00
1277#define NV40_3D_TEX_FILTER_OPTIMIZATION_UNKNOWN__SHIFT 10
1278#define NV40_3D_TEX_FILTER_OPTIMIZATION_UNKNOWN_OFF 0x00000000
1279#define NV40_3D_TEX_FILTER_OPTIMIZATION_UNKNOWN_PARTIAL 0x00002c00
1280#define NV40_3D_TEX_FILTER_OPTIMIZATION_UNKNOWN_FULL 0x00007c00
1281
1282#define NV40_3D_UNK0B40(i0) (0x00000b40 + 0x4*(i0))
1283#define NV40_3D_UNK0B40__ESIZE 0x00000004
1284#define NV40_3D_UNK0B40__LEN 0x00000008
1285
1286#define NV30_3D_VP_UPLOAD_INST(i0) (0x00000b80 + 0x4*(i0))
1287#define NV30_3D_VP_UPLOAD_INST__ESIZE 0x00000004
1288#define NV30_3D_VP_UPLOAD_INST__LEN 0x00000004
1289
1290
1291#define NV30_3D_TEX_CLIP_PLANE(i0) (0x00000e00 + 0x10*(i0))
1292
1293
1294#define NV30_3D_TEX_CLIP_PLANE_X(i0) (0x00000e00 + 0x10*(i0))
1295
1296#define NV30_3D_TEX_CLIP_PLANE_Y(i0) (0x00000e04 + 0x10*(i0))
1297
1298#define NV30_3D_TEX_CLIP_PLANE_Z(i0) (0x00000e08 + 0x10*(i0))
1299
1300#define NV30_3D_TEX_CLIP_PLANE_W(i0) (0x00000e0c + 0x10*(i0))
1301
1302#define NV30_3D_LIGHT 0x00001000
1303
1304
1305#define NV30_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT(i0) (0x00001000 + 0x40*(i0))
1306
1307
1308#define NV30_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_R(i0) (0x00001000 + 0x40*(i0))
1309
1310#define NV30_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_G(i0) (0x00001004 + 0x40*(i0))
1311
1312#define NV30_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_B(i0) (0x00001008 + 0x40*(i0))
1313
1314#define NV30_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE(i0) (0x0000100c + 0x40*(i0))
1315
1316
1317#define NV30_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_R(i0) (0x0000100c + 0x40*(i0))
1318
1319#define NV30_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_G(i0) (0x00001010 + 0x40*(i0))
1320
1321#define NV30_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_B(i0) (0x00001014 + 0x40*(i0))
1322
1323#define NV30_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR(i0) (0x00001018 + 0x40*(i0))
1324
1325
1326#define NV30_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_R(i0) (0x00001018 + 0x40*(i0))
1327
1328#define NV30_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_G(i0) (0x0000101c + 0x40*(i0))
1329
1330#define NV30_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_B(i0) (0x00001020 + 0x40*(i0))
1331
1332#define NV30_3D_LIGHT_UNK24(i0) (0x00001024 + 0x40*(i0))
1333
1334#define NV30_3D_LIGHT_HALF_VECTOR(i0) (0x00001028 + 0x40*(i0))
1335
1336
1337#define NV30_3D_LIGHT_HALF_VECTOR_X(i0) (0x00001028 + 0x40*(i0))
1338
1339#define NV30_3D_LIGHT_HALF_VECTOR_Y(i0) (0x0000102c + 0x40*(i0))
1340
1341#define NV30_3D_LIGHT_HALF_VECTOR_Z(i0) (0x00001030 + 0x40*(i0))
1342
1343#define NV30_3D_LIGHT_DIRECTION(i0) (0x00001034 + 0x40*(i0))
1344
1345
1346#define NV30_3D_LIGHT_DIRECTION_X(i0) (0x00001034 + 0x40*(i0))
1347
1348#define NV30_3D_LIGHT_DIRECTION_Y(i0) (0x00001038 + 0x40*(i0))
1349
1350#define NV30_3D_LIGHT_DIRECTION_Z(i0) (0x0000103c + 0x40*(i0))
1351
1352
1353#define NV30_3D_LIGHT_SPOT_CUTOFF_A(i0) (0x00001200 + 0x40*(i0))
1354
1355#define NV30_3D_LIGHT_SPOT_CUTOFF_B(i0) (0x00001204 + 0x40*(i0))
1356
1357#define NV30_3D_LIGHT_SPOT_CUTOFF_C(i0) (0x00001208 + 0x40*(i0))
1358
1359#define NV30_3D_LIGHT_SPOT_DIR(i0) (0x0000120c + 0x40*(i0))
1360
1361
1362#define NV30_3D_LIGHT_SPOT_DIR_X(i0) (0x0000120c + 0x40*(i0))
1363
1364#define NV30_3D_LIGHT_SPOT_DIR_Y(i0) (0x00001210 + 0x40*(i0))
1365
1366#define NV30_3D_LIGHT_SPOT_DIR_Z(i0) (0x00001214 + 0x40*(i0))
1367
1368#define NV30_3D_LIGHT_SPOT_CUTOFF_D(i0) (0x00001218 + 0x40*(i0))
1369
1370#define NV30_3D_LIGHT_POSITION(i0) (0x0000121c + 0x40*(i0))
1371
1372
1373#define NV30_3D_LIGHT_POSITION_X(i0) (0x0000121c + 0x40*(i0))
1374
1375#define NV30_3D_LIGHT_POSITION_Y(i0) (0x00001220 + 0x40*(i0))
1376
1377#define NV30_3D_LIGHT_POSITION_Z(i0) (0x00001224 + 0x40*(i0))
1378
1379#define NV30_3D_LIGHT_ATTENUATION(i0) (0x00001228 + 0x40*(i0))
1380
1381#define NV30_3D_LIGHT_ATTENUATION_CONSTANT(i0) (0x00001228 + 0x40*(i0))
1382
1383#define NV30_3D_LIGHT_ATTENUATION_LINEAR(i0) (0x0000122c + 0x40*(i0))
1384
1385#define NV30_3D_LIGHT_ATTENUATION_QUADRATIC(i0) (0x00001230 + 0x40*(i0))
1386
1387#define NV30_3D_FRONT_MATERIAL_SHININESS(i0) (0x00001400 + 0x4*(i0))
1388#define NV30_3D_FRONT_MATERIAL_SHININESS__ESIZE 0x00000004
1389#define NV30_3D_FRONT_MATERIAL_SHININESS__LEN 0x00000006
1390
1391#define NV30_3D_ENABLED_LIGHTS 0x00001420
1392
1393#define NV30_3D_VERTEX_TWO_SIDE_ENABLE 0x0000142c
1394
1395#define NV30_3D_FP_REG_CONTROL 0x00001450
1396#define NV30_3D_FP_REG_CONTROL_UNK0__MASK 0x0000ffff
1397#define NV30_3D_FP_REG_CONTROL_UNK0__SHIFT 0
1398#define NV30_3D_FP_REG_CONTROL_UNK1__MASK 0xffff0000
1399#define NV30_3D_FP_REG_CONTROL_UNK1__SHIFT 16
1400
1401#define NV30_3D_FLATSHADE_FIRST 0x00001454
1402
1403#define NV30_3D_EDGEFLAG 0x0000145c
1404#define NV30_3D_EDGEFLAG_ENABLE 0x00000001
1405
1406#define NV30_3D_VP_CLIP_PLANES_ENABLE 0x00001478
1407#define NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE0 0x00000002
1408#define NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE1 0x00000020
1409#define NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE2 0x00000200
1410#define NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE3 0x00002000
1411#define NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE4 0x00020000
1412#define NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE5 0x00200000
1413
1414#define NV30_3D_POLYGON_STIPPLE_ENABLE 0x0000147c
1415
1416#define NV30_3D_POLYGON_STIPPLE_PATTERN(i0) (0x00001480 + 0x4*(i0))
1417#define NV30_3D_POLYGON_STIPPLE_PATTERN__ESIZE 0x00000004
1418#define NV30_3D_POLYGON_STIPPLE_PATTERN__LEN 0x00000020
1419
1420#define NV30_3D_VTX_ATTR_3F(i0) (0x00001500 + 0x10*(i0))
1421#define NV30_3D_VTX_ATTR_3F__ESIZE 0x00000010
1422#define NV30_3D_VTX_ATTR_3F__LEN 0x00000010
1423
1424
1425#define NV30_3D_VTX_ATTR_3F_X(i0) (0x00001500 + 0x10*(i0))
1426
1427#define NV30_3D_VTX_ATTR_3F_Y(i0) (0x00001504 + 0x10*(i0))
1428
1429#define NV30_3D_VTX_ATTR_3F_Z(i0) (0x00001508 + 0x10*(i0))
1430
1431
1432#define NV30_3D_VP_CLIP_PLANE(i0, i1) (0x00001600 + 0x10*(i0) + 0x4*(i1))
1433#define NV30_3D_VP_CLIP_PLANE__ESIZE 0x00000004
1434#define NV30_3D_VP_CLIP_PLANE__LEN 0x00000004
1435
1436#define NV30_3D_VTXBUF(i0) (0x00001680 + 0x4*(i0))
1437#define NV30_3D_VTXBUF__ESIZE 0x00000004
1438#define NV30_3D_VTXBUF__LEN 0x00000010
1439#define NV30_3D_VTXBUF_OFFSET__MASK 0x0fffffff
1440#define NV30_3D_VTXBUF_OFFSET__SHIFT 0
1441#define NV30_3D_VTXBUF_DMA1 0x80000000
1442
1443#define NV40_3D_VTX_CACHE_INVALIDATE 0x00001714
1444
1445#define NV30_3D_VTXFMT(i0) (0x00001740 + 0x4*(i0))
1446#define NV30_3D_VTXFMT__ESIZE 0x00000004
1447#define NV30_3D_VTXFMT__LEN 0x00000010
1448#define NV30_3D_VTXFMT_TYPE__MASK 0x0000000f
1449#define NV30_3D_VTXFMT_TYPE__SHIFT 0
1450#define NV30_3D_VTXFMT_TYPE_B8G8R8A8_UNORM 0x00000000
1451#define NV30_3D_VTXFMT_TYPE_V16_SNORM 0x00000001
1452#define NV30_3D_VTXFMT_TYPE_V32_FLOAT 0x00000002
1453#define NV30_3D_VTXFMT_TYPE_V16_FLOAT 0x00000003
1454#define NV30_3D_VTXFMT_TYPE_U8_UNORM 0x00000004
1455#define NV30_3D_VTXFMT_TYPE_V16_SSCALED 0x00000005
1456#define NV30_3D_VTXFMT_TYPE_U8_USCALED 0x00000007
1457#define NV30_3D_VTXFMT_SIZE__MASK 0x000000f0
1458#define NV30_3D_VTXFMT_SIZE__SHIFT 4
1459#define NV30_3D_VTXFMT_STRIDE__MASK 0x0000ff00
1460#define NV30_3D_VTXFMT_STRIDE__SHIFT 8
1461
1462#define NV30_3D_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION 0x000017a0
1463
1464
1465#define NV30_3D_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_R 0x000017a0
1466
1467#define NV30_3D_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_G 0x000017a4
1468
1469#define NV30_3D_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_B 0x000017a8
1470
1471#define NV30_3D_COLOR_MATERIAL_BACK 0x000017b0
1472
1473
1474#define NV30_3D_COLOR_MATERIAL_BACK_R 0x000017b0
1475
1476#define NV30_3D_COLOR_MATERIAL_BACK_G 0x000017b4
1477
1478#define NV30_3D_COLOR_MATERIAL_BACK_B 0x000017b8
1479
1480#define NV30_3D_COLOR_MATERIAL_BACK_A 0x000017bc
1481
1482#define NV30_3D_QUERY_RESET 0x000017c8
1483
1484#define NV30_3D_QUERY_ENABLE 0x000017cc
1485
1486#define NV30_3D_QUERY_GET 0x00001800
1487#define NV30_3D_QUERY_GET_OFFSET__MASK 0x00ffffff
1488#define NV30_3D_QUERY_GET_OFFSET__SHIFT 0
1489#define NV30_3D_QUERY_GET_UNK24__MASK 0xff000000
1490#define NV30_3D_QUERY_GET_UNK24__SHIFT 24
1491
1492#define NV30_3D_VERTEX_BEGIN_END 0x00001808
1493#define NV30_3D_VERTEX_BEGIN_END_STOP 0x00000000
1494#define NV30_3D_VERTEX_BEGIN_END_POINTS 0x00000001
1495#define NV30_3D_VERTEX_BEGIN_END_LINES 0x00000002
1496#define NV30_3D_VERTEX_BEGIN_END_LINE_LOOP 0x00000003
1497#define NV30_3D_VERTEX_BEGIN_END_LINE_STRIP 0x00000004
1498#define NV30_3D_VERTEX_BEGIN_END_TRIANGLES 0x00000005
1499#define NV30_3D_VERTEX_BEGIN_END_TRIANGLE_STRIP 0x00000006
1500#define NV30_3D_VERTEX_BEGIN_END_TRIANGLE_FAN 0x00000007
1501#define NV30_3D_VERTEX_BEGIN_END_QUADS 0x00000008
1502#define NV30_3D_VERTEX_BEGIN_END_QUAD_STRIP 0x00000009
1503#define NV30_3D_VERTEX_BEGIN_END_POLYGON 0x0000000a
1504
1505#define NV30_3D_VB_ELEMENT_U16 0x0000180c
1506#define NV30_3D_VB_ELEMENT_U16_0__MASK 0x0000ffff
1507#define NV30_3D_VB_ELEMENT_U16_0__SHIFT 0
1508#define NV30_3D_VB_ELEMENT_U16_1__MASK 0xffff0000
1509#define NV30_3D_VB_ELEMENT_U16_1__SHIFT 16
1510
1511#define NV30_3D_VB_ELEMENT_U32 0x00001810
1512
1513#define NV30_3D_VB_VERTEX_BATCH 0x00001814
1514#define NV30_3D_VB_VERTEX_BATCH_OFFSET__MASK 0x00ffffff
1515#define NV30_3D_VB_VERTEX_BATCH_OFFSET__SHIFT 0
1516#define NV30_3D_VB_VERTEX_BATCH_COUNT__MASK 0xff000000
1517#define NV30_3D_VB_VERTEX_BATCH_COUNT__SHIFT 24
1518
1519#define NV30_3D_VERTEX_DATA 0x00001818
1520
1521#define NV30_3D_IDXBUF_OFFSET 0x0000181c
1522
1523#define NV30_3D_IDXBUF_FORMAT 0x00001820
1524#define NV30_3D_IDXBUF_FORMAT_DMA1 0x00000001
1525#define NV30_3D_IDXBUF_FORMAT_TYPE__MASK 0x000000f0
1526#define NV30_3D_IDXBUF_FORMAT_TYPE__SHIFT 4
1527#define NV30_3D_IDXBUF_FORMAT_TYPE_U32 0x00000000
1528#define NV30_3D_IDXBUF_FORMAT_TYPE_U16 0x00000010
1529
1530#define NV30_3D_VB_INDEX_BATCH 0x00001824
1531#define NV30_3D_VB_INDEX_BATCH_START__MASK 0x00ffffff
1532#define NV30_3D_VB_INDEX_BATCH_START__SHIFT 0
1533#define NV30_3D_VB_INDEX_BATCH_COUNT__MASK 0xff000000
1534#define NV30_3D_VB_INDEX_BATCH_COUNT__SHIFT 24
1535
1536#define NV30_3D_POLYGON_MODE_FRONT 0x00001828
1537#define NV30_3D_POLYGON_MODE_FRONT_POINT 0x00001b00
1538#define NV30_3D_POLYGON_MODE_FRONT_LINE 0x00001b01
1539#define NV30_3D_POLYGON_MODE_FRONT_FILL 0x00001b02
1540
1541#define NV30_3D_POLYGON_MODE_BACK 0x0000182c
1542#define NV30_3D_POLYGON_MODE_BACK_POINT 0x00001b00
1543#define NV30_3D_POLYGON_MODE_BACK_LINE 0x00001b01
1544#define NV30_3D_POLYGON_MODE_BACK_FILL 0x00001b02
1545
1546#define NV30_3D_CULL_FACE 0x00001830
1547#define NV30_3D_CULL_FACE_FRONT 0x00000404
1548#define NV30_3D_CULL_FACE_BACK 0x00000405
1549#define NV30_3D_CULL_FACE_FRONT_AND_BACK 0x00000408
1550
1551#define NV30_3D_FRONT_FACE 0x00001834
1552#define NV30_3D_FRONT_FACE_CW 0x00000900
1553#define NV30_3D_FRONT_FACE_CCW 0x00000901
1554
1555#define NV30_3D_POLYGON_SMOOTH_ENABLE 0x00001838
1556
1557#define NV30_3D_CULL_FACE_ENABLE 0x0000183c
1558
1559#define NV30_3D_TEX_PALETTE_OFFSET(i0) (0x00001840 + 0x4*(i0))
1560#define NV30_3D_TEX_PALETTE_OFFSET__ESIZE 0x00000004
1561#define NV30_3D_TEX_PALETTE_OFFSET__LEN 0x00000008
1562
1563#define NV40_3D_TEX_SIZE1(i0) (0x00001840 + 0x4*(i0))
1564#define NV40_3D_TEX_SIZE1__ESIZE 0x00000004
1565#define NV40_3D_TEX_SIZE1__LEN 0x00000008
1566#define NV40_3D_TEX_SIZE1_DEPTH__MASK 0xfff00000
1567#define NV40_3D_TEX_SIZE1_DEPTH__SHIFT 20
1568#define NV40_3D_TEX_SIZE1_PITCH__MASK 0x0000ffff
1569#define NV40_3D_TEX_SIZE1_PITCH__SHIFT 0
1570
1571#define NV30_3D_VTX_ATTR_2F(i0) (0x00001880 + 0x8*(i0))
1572#define NV30_3D_VTX_ATTR_2F__ESIZE 0x00000008
1573#define NV30_3D_VTX_ATTR_2F__LEN 0x00000010
1574
1575
1576#define NV30_3D_VTX_ATTR_2F_X(i0) (0x00001880 + 0x8*(i0))
1577
1578#define NV30_3D_VTX_ATTR_2F_Y(i0) (0x00001884 + 0x8*(i0))
1579
1580#define NV30_3D_VTX_ATTR_2I(i0) (0x00001900 + 0x4*(i0))
1581#define NV30_3D_VTX_ATTR_2I__ESIZE 0x00000004
1582#define NV30_3D_VTX_ATTR_2I__LEN 0x00000010
1583#define NV30_3D_VTX_ATTR_2I_X__MASK 0x0000ffff
1584#define NV30_3D_VTX_ATTR_2I_X__SHIFT 0
1585#define NV30_3D_VTX_ATTR_2I_Y__MASK 0xffff0000
1586#define NV30_3D_VTX_ATTR_2I_Y__SHIFT 16
1587
1588#define NV30_3D_VTX_ATTR_4UB(i0) (0x00001940 + 0x4*(i0))
1589#define NV30_3D_VTX_ATTR_4UB__ESIZE 0x00000004
1590#define NV30_3D_VTX_ATTR_4UB__LEN 0x00000010
1591#define NV30_3D_VTX_ATTR_4UB_X__MASK 0x000000ff
1592#define NV30_3D_VTX_ATTR_4UB_X__SHIFT 0
1593#define NV30_3D_VTX_ATTR_4UB_Y__MASK 0x0000ff00
1594#define NV30_3D_VTX_ATTR_4UB_Y__SHIFT 8
1595#define NV30_3D_VTX_ATTR_4UB_Z__MASK 0x00ff0000
1596#define NV30_3D_VTX_ATTR_4UB_Z__SHIFT 16
1597#define NV30_3D_VTX_ATTR_4UB_W__MASK 0xff000000
1598#define NV30_3D_VTX_ATTR_4UB_W__SHIFT 24
1599
1600#define NV30_3D_VTX_ATTR_4I(i0) (0x00001980 + 0x8*(i0))
1601#define NV30_3D_VTX_ATTR_4I__ESIZE 0x00000008
1602#define NV30_3D_VTX_ATTR_4I__LEN 0x00000010
1603
1604#define NV30_3D_VTX_ATTR_4I_XY(i0) (0x00001980 + 0x8*(i0))
1605#define NV30_3D_VTX_ATTR_4I_XY_X__MASK 0x0000ffff
1606#define NV30_3D_VTX_ATTR_4I_XY_X__SHIFT 0
1607#define NV30_3D_VTX_ATTR_4I_XY_Y__MASK 0xffff0000
1608#define NV30_3D_VTX_ATTR_4I_XY_Y__SHIFT 16
1609
1610#define NV30_3D_VTX_ATTR_4I_ZW(i0) (0x00001984 + 0x8*(i0))
1611#define NV30_3D_VTX_ATTR_4I_ZW_Z__MASK 0x0000ffff
1612#define NV30_3D_VTX_ATTR_4I_ZW_Z__SHIFT 0
1613#define NV30_3D_VTX_ATTR_4I_ZW_W__MASK 0xffff0000
1614#define NV30_3D_VTX_ATTR_4I_ZW_W__SHIFT 16
1615
1616#define NV30_3D_TEX_OFFSET(i0) (0x00001a00 + 0x20*(i0))
1617#define NV30_3D_TEX_OFFSET__ESIZE 0x00000020
1618#define NV30_3D_TEX_OFFSET__LEN 0x00000008
1619
1620#define NV30_3D_TEX_FORMAT(i0) (0x00001a04 + 0x20*(i0))
1621#define NV30_3D_TEX_FORMAT__ESIZE 0x00000020
1622#define NV30_3D_TEX_FORMAT__LEN 0x00000008
1623#define NV30_3D_TEX_FORMAT_DMA0 0x00000001
1624#define NV30_3D_TEX_FORMAT_DMA1 0x00000002
1625#define NV30_3D_TEX_FORMAT_CUBIC 0x00000004
1626#define NV30_3D_TEX_FORMAT_NO_BORDER 0x00000008
1627#define NV30_3D_TEX_FORMAT_DIMS__MASK 0x000000f0
1628#define NV30_3D_TEX_FORMAT_DIMS__SHIFT 4
1629#define NV30_3D_TEX_FORMAT_DIMS_1D 0x00000010
1630#define NV30_3D_TEX_FORMAT_DIMS_2D 0x00000020
1631#define NV30_3D_TEX_FORMAT_DIMS_3D 0x00000030
1632#define NV30_3D_TEX_FORMAT_FORMAT__MASK 0x0000ff00
1633#define NV30_3D_TEX_FORMAT_FORMAT__SHIFT 8
1634#define NV30_3D_TEX_FORMAT_FORMAT_L8 0x00000000
1635#define NV30_3D_TEX_FORMAT_FORMAT_I8 0x00000100
1636#define NV30_3D_TEX_FORMAT_FORMAT_A1R5G5B5 0x00000200
1637#define NV30_3D_TEX_FORMAT_FORMAT_A4R4G4B4 0x00000400
1638#define NV30_3D_TEX_FORMAT_FORMAT_R5G6B5 0x00000500
1639#define NV30_3D_TEX_FORMAT_FORMAT_A8R8G8B8 0x00000600
1640#define NV30_3D_TEX_FORMAT_FORMAT_X8R8G8B8 0x00000700
1641#define NV30_3D_TEX_FORMAT_FORMAT_INDEX8 0x00000b00
1642#define NV30_3D_TEX_FORMAT_FORMAT_DXT1 0x00000c00
1643#define NV30_3D_TEX_FORMAT_FORMAT_DXT3 0x00000e00
1644#define NV30_3D_TEX_FORMAT_FORMAT_DXT5 0x00000f00
1645#define NV30_3D_TEX_FORMAT_FORMAT_A1R5G5B5_RECT 0x00001000
1646#define NV30_3D_TEX_FORMAT_FORMAT_R5G6B5_RECT 0x00001100
1647#define NV30_3D_TEX_FORMAT_FORMAT_A8R8G8B8_RECT 0x00001200
1648#define NV30_3D_TEX_FORMAT_FORMAT_L8_RECT 0x00001300
1649#define NV30_3D_TEX_FORMAT_FORMAT_DSDT8_RECT 0x00001700
1650#define NV30_3D_TEX_FORMAT_FORMAT_A8L8 0x00001a00
1651#define NV30_3D_TEX_FORMAT_FORMAT_I8_RECT 0x00001b00
1652#define NV30_3D_TEX_FORMAT_FORMAT_A4R4G4B4_RECT 0x00001d00
1653#define NV30_3D_TEX_FORMAT_FORMAT_R8G8B8_RECT 0x00001e00
1654#define NV30_3D_TEX_FORMAT_FORMAT_A8L8_RECT 0x00002000
1655#define NV30_3D_TEX_FORMAT_FORMAT_Z24 0x00002a00
1656#define NV30_3D_TEX_FORMAT_FORMAT_Z24_RECT 0x00002b00
1657#define NV30_3D_TEX_FORMAT_FORMAT_Z16 0x00002c00
1658#define NV30_3D_TEX_FORMAT_FORMAT_Z16_RECT 0x00002d00
1659#define NV30_3D_TEX_FORMAT_FORMAT_DSDT8 0x00002800
1660#define NV30_3D_TEX_FORMAT_FORMAT_HILO16 0x00003300
1661#define NV30_3D_TEX_FORMAT_FORMAT_HILO16_RECT 0x00003600
1662#define NV30_3D_TEX_FORMAT_FORMAT_HILO8 0x00004400
1663#define NV30_3D_TEX_FORMAT_FORMAT_SIGNED_HILO8 0x00004500
1664#define NV30_3D_TEX_FORMAT_FORMAT_HILO8_RECT 0x00004600
1665#define NV30_3D_TEX_FORMAT_FORMAT_SIGNED_HILO8_RECT 0x00004700
1666#define NV30_3D_TEX_FORMAT_FORMAT_A16 0x00003200
1667#define NV30_3D_TEX_FORMAT_FORMAT_A16_RECT 0x00003500
1668#define NV30_3D_TEX_FORMAT_FORMAT_UNK3F 0x00003f00
1669#define NV30_3D_TEX_FORMAT_FORMAT_FLOAT_RGBA16_NV 0x00004a00
1670#define NV30_3D_TEX_FORMAT_FORMAT_FLOAT_RGBA32_NV 0x00004b00
1671#define NV30_3D_TEX_FORMAT_FORMAT_FLOAT_R32_NV 0x00004c00
1672#define NV40_3D_TEX_FORMAT_FORMAT__MASK 0x00001f00
1673#define NV40_3D_TEX_FORMAT_FORMAT__SHIFT 8
1674#define NV40_3D_TEX_FORMAT_FORMAT_L8 0x00000100
1675#define NV40_3D_TEX_FORMAT_FORMAT_A1R5G5B5 0x00000200
1676#define NV40_3D_TEX_FORMAT_FORMAT_A4R4G4B4 0x00000300
1677#define NV40_3D_TEX_FORMAT_FORMAT_R5G6B5 0x00000400
1678#define NV40_3D_TEX_FORMAT_FORMAT_A8R8G8B8 0x00000500
1679#define NV40_3D_TEX_FORMAT_FORMAT_DXT1 0x00000600
1680#define NV40_3D_TEX_FORMAT_FORMAT_DXT3 0x00000700
1681#define NV40_3D_TEX_FORMAT_FORMAT_DXT5 0x00000800
1682#define NV40_3D_TEX_FORMAT_FORMAT_A8L8 0x00000b00
1683#define NV40_3D_TEX_FORMAT_FORMAT_Z24 0x00001000
1684#define NV40_3D_TEX_FORMAT_FORMAT_Z16 0x00001200
1685#define NV40_3D_TEX_FORMAT_FORMAT_A16 0x00001400
1686#define NV40_3D_TEX_FORMAT_FORMAT_A16L16 0x00001500
1687#define NV40_3D_TEX_FORMAT_FORMAT_HILO8 0x00001800
1688#define NV40_3D_TEX_FORMAT_FORMAT_RGBA16F 0x00001a00
1689#define NV40_3D_TEX_FORMAT_FORMAT_RGBA32F 0x00001b00
1690#define NV40_3D_TEX_FORMAT_LINEAR 0x00002000
1691#define NV40_3D_TEX_FORMAT_RECT 0x00004000
1692#define NV40_3D_TEX_FORMAT_MIPMAP_COUNT__MASK 0x000f0000
1693#define NV40_3D_TEX_FORMAT_MIPMAP_COUNT__SHIFT 16
1694#define NV30_3D_TEX_FORMAT_MIPMAP 0x00080000
1695#define NV30_3D_TEX_FORMAT_BASE_SIZE_U__MASK 0x00f00000
1696#define NV30_3D_TEX_FORMAT_BASE_SIZE_U__SHIFT 20
1697#define NV30_3D_TEX_FORMAT_BASE_SIZE_V__MASK 0x0f000000
1698#define NV30_3D_TEX_FORMAT_BASE_SIZE_V__SHIFT 24
1699#define NV30_3D_TEX_FORMAT_BASE_SIZE_W__MASK 0xf0000000
1700#define NV30_3D_TEX_FORMAT_BASE_SIZE_W__SHIFT 28
1701
1702#define NV30_3D_TEX_WRAP(i0) (0x00001a08 + 0x20*(i0))
1703#define NV30_3D_TEX_WRAP__ESIZE 0x00000020
1704#define NV30_3D_TEX_WRAP__LEN 0x00000008
1705#define NV30_3D_TEX_WRAP_S__MASK 0x000000ff
1706#define NV30_3D_TEX_WRAP_S__SHIFT 0
1707#define NV30_3D_TEX_WRAP_S_REPEAT 0x00000001
1708#define NV30_3D_TEX_WRAP_S_MIRRORED_REPEAT 0x00000002
1709#define NV30_3D_TEX_WRAP_S_CLAMP_TO_EDGE 0x00000003
1710#define NV30_3D_TEX_WRAP_S_CLAMP_TO_BORDER 0x00000004
1711#define NV30_3D_TEX_WRAP_S_CLAMP 0x00000005
1712#define NV40_3D_TEX_WRAP_S_MIRROR_CLAMP_TO_EDGE 0x00000006
1713#define NV40_3D_TEX_WRAP_S_MIRROR_CLAMP_TO_BORDER 0x00000007
1714#define NV40_3D_TEX_WRAP_S_MIRROR_CLAMP 0x00000008
1715#define NV40_3D_TEX_WRAP_ANISO_MIP_FILTER_OPTIMIZATION__MASK 0x00000070
1716#define NV40_3D_TEX_WRAP_ANISO_MIP_FILTER_OPTIMIZATION__SHIFT 4
1717#define NV40_3D_TEX_WRAP_ANISO_MIP_FILTER_OPTIMIZATION_OFF 0x00000000
1718#define NV40_3D_TEX_WRAP_ANISO_MIP_FILTER_OPTIMIZATION_QUALITY 0x00000020
1719#define NV40_3D_TEX_WRAP_ANISO_MIP_FILTER_OPTIMIZATION_PERFORMANCE 0x00000030
1720#define NV40_3D_TEX_WRAP_ANISO_MIP_FILTER_OPTIMIZATION_HIGH_PERFORMANCE 0x00000070
1721#define NV30_3D_TEX_WRAP_T__MASK 0x00000f00
1722#define NV30_3D_TEX_WRAP_T__SHIFT 8
1723#define NV30_3D_TEX_WRAP_T_REPEAT 0x00000100
1724#define NV30_3D_TEX_WRAP_T_MIRRORED_REPEAT 0x00000200
1725#define NV30_3D_TEX_WRAP_T_CLAMP_TO_EDGE 0x00000300
1726#define NV30_3D_TEX_WRAP_T_CLAMP_TO_BORDER 0x00000400
1727#define NV30_3D_TEX_WRAP_T_CLAMP 0x00000500
1728#define NV40_3D_TEX_WRAP_T_MIRROR_CLAMP_TO_EDGE 0x00000600
1729#define NV40_3D_TEX_WRAP_T_MIRROR_CLAMP_TO_BORDER 0x00000700
1730#define NV40_3D_TEX_WRAP_T_MIRROR_CLAMP 0x00000800
1731#define NV30_3D_TEX_WRAP_EXPAND_NORMAL 0x0000f000
1732#define NV30_3D_TEX_WRAP_R__MASK 0x000f0000
1733#define NV30_3D_TEX_WRAP_R__SHIFT 16
1734#define NV30_3D_TEX_WRAP_R_REPEAT 0x00010000
1735#define NV30_3D_TEX_WRAP_R_MIRRORED_REPEAT 0x00020000
1736#define NV30_3D_TEX_WRAP_R_CLAMP_TO_EDGE 0x00030000
1737#define NV30_3D_TEX_WRAP_R_CLAMP_TO_BORDER 0x00040000
1738#define NV30_3D_TEX_WRAP_R_CLAMP 0x00050000
1739#define NV40_3D_TEX_WRAP_R_MIRROR_CLAMP_TO_EDGE 0x00060000
1740#define NV40_3D_TEX_WRAP_R_MIRROR_CLAMP_TO_BORDER 0x00070000
1741#define NV40_3D_TEX_WRAP_R_MIRROR_CLAMP 0x00080000
1742#define NV40_3D_TEX_WRAP_GAMMA_DECREASE_FILTER__MASK 0x00f00000
1743#define NV40_3D_TEX_WRAP_GAMMA_DECREASE_FILTER__SHIFT 20
1744#define NV40_3D_TEX_WRAP_GAMMA_DECREASE_FILTER_NONE 0x00000000
1745#define NV40_3D_TEX_WRAP_GAMMA_DECREASE_FILTER_RED 0x00100000
1746#define NV40_3D_TEX_WRAP_GAMMA_DECREASE_FILTER_GREEN 0x00200000
1747#define NV40_3D_TEX_WRAP_GAMMA_DECREASE_FILTER_BLUE 0x00400000
1748#define NV40_3D_TEX_WRAP_GAMMA_DECREASE_FILTER_ALL 0x00f00000
1749#define NV30_3D_TEX_WRAP_RCOMP__MASK 0xf0000000
1750#define NV30_3D_TEX_WRAP_RCOMP__SHIFT 28
1751#define NV30_3D_TEX_WRAP_RCOMP_NEVER 0x00000000
1752#define NV30_3D_TEX_WRAP_RCOMP_GREATER 0x10000000
1753#define NV30_3D_TEX_WRAP_RCOMP_EQUAL 0x20000000
1754#define NV30_3D_TEX_WRAP_RCOMP_GEQUAL 0x30000000
1755#define NV30_3D_TEX_WRAP_RCOMP_LESS 0x40000000
1756#define NV30_3D_TEX_WRAP_RCOMP_NOTEQUAL 0x50000000
1757#define NV30_3D_TEX_WRAP_RCOMP_LEQUAL 0x60000000
1758#define NV30_3D_TEX_WRAP_RCOMP_ALWAYS 0x70000000
1759
1760#define NV30_3D_TEX_ENABLE(i0) (0x00001a0c + 0x20*(i0))
1761#define NV30_3D_TEX_ENABLE__ESIZE 0x00000020
1762#define NV30_3D_TEX_ENABLE__LEN 0x00000008
1763#define NV30_3D_TEX_ENABLE_ANISO__MASK 0x00000030
1764#define NV30_3D_TEX_ENABLE_ANISO__SHIFT 4
1765#define NV30_3D_TEX_ENABLE_ANISO_NONE 0x00000000
1766#define NV30_3D_TEX_ENABLE_ANISO_2X 0x00000010
1767#define NV30_3D_TEX_ENABLE_ANISO_4X 0x00000020
1768#define NV30_3D_TEX_ENABLE_ANISO_8X 0x00000030
1769#define NV40_3D_TEX_ENABLE_ANISO__MASK 0x000000f0
1770#define NV40_3D_TEX_ENABLE_ANISO__SHIFT 4
1771#define NV40_3D_TEX_ENABLE_ANISO_NONE 0x00000000
1772#define NV40_3D_TEX_ENABLE_ANISO_2X 0x00000010
1773#define NV40_3D_TEX_ENABLE_ANISO_4X 0x00000020
1774#define NV40_3D_TEX_ENABLE_ANISO_6X 0x00000030
1775#define NV40_3D_TEX_ENABLE_ANISO_8X 0x00000040
1776#define NV40_3D_TEX_ENABLE_ANISO_10X 0x00000050
1777#define NV40_3D_TEX_ENABLE_ANISO_12X 0x00000060
1778#define NV40_3D_TEX_ENABLE_ANISO_16X 0x00000070
1779#define NV30_3D_TEX_ENABLE_MIPMAP_MAX_LOD__MASK 0x0003c000
1780#define NV30_3D_TEX_ENABLE_MIPMAP_MAX_LOD__SHIFT 14
1781#define NV40_3D_TEX_ENABLE_MIPMAP_MAX_LOD__MASK 0x00038000
1782#define NV40_3D_TEX_ENABLE_MIPMAP_MAX_LOD__SHIFT 15
1783#define NV30_3D_TEX_ENABLE_MIPMAP_MIN_LOD__MASK 0x3c000000
1784#define NV30_3D_TEX_ENABLE_MIPMAP_MIN_LOD__SHIFT 26
1785#define NV40_3D_TEX_ENABLE_MIPMAP_MIN_LOD__MASK 0x38000000
1786#define NV40_3D_TEX_ENABLE_MIPMAP_MIN_LOD__SHIFT 27
1787#define NV30_3D_TEX_ENABLE_ENABLE 0x40000000
1788#define NV40_3D_TEX_ENABLE_ENABLE 0x80000000
1789
1790#define NV30_3D_TEX_SWIZZLE(i0) (0x00001a10 + 0x20*(i0))
1791#define NV30_3D_TEX_SWIZZLE__ESIZE 0x00000020
1792#define NV30_3D_TEX_SWIZZLE__LEN 0x00000008
1793#define NV30_3D_TEX_SWIZZLE_S1_W__MASK 0x00000003
1794#define NV30_3D_TEX_SWIZZLE_S1_W__SHIFT 0
1795#define NV30_3D_TEX_SWIZZLE_S1_W_W 0x00000000
1796#define NV30_3D_TEX_SWIZZLE_S1_W_Z 0x00000001
1797#define NV30_3D_TEX_SWIZZLE_S1_W_Y 0x00000002
1798#define NV30_3D_TEX_SWIZZLE_S1_W_X 0x00000003
1799#define NV30_3D_TEX_SWIZZLE_S1_Z__MASK 0x0000000c
1800#define NV30_3D_TEX_SWIZZLE_S1_Z__SHIFT 2
1801#define NV30_3D_TEX_SWIZZLE_S1_Z_W 0x00000000
1802#define NV30_3D_TEX_SWIZZLE_S1_Z_Z 0x00000004
1803#define NV30_3D_TEX_SWIZZLE_S1_Z_Y 0x00000008
1804#define NV30_3D_TEX_SWIZZLE_S1_Z_X 0x0000000c
1805#define NV30_3D_TEX_SWIZZLE_S1_Y__MASK 0x00000030
1806#define NV30_3D_TEX_SWIZZLE_S1_Y__SHIFT 4
1807#define NV30_3D_TEX_SWIZZLE_S1_Y_W 0x00000000
1808#define NV30_3D_TEX_SWIZZLE_S1_Y_Z 0x00000010
1809#define NV30_3D_TEX_SWIZZLE_S1_Y_Y 0x00000020
1810#define NV30_3D_TEX_SWIZZLE_S1_Y_X 0x00000030
1811#define NV30_3D_TEX_SWIZZLE_S1_X__MASK 0x000000c0
1812#define NV30_3D_TEX_SWIZZLE_S1_X__SHIFT 6
1813#define NV30_3D_TEX_SWIZZLE_S1_X_W 0x00000000
1814#define NV30_3D_TEX_SWIZZLE_S1_X_Z 0x00000040
1815#define NV30_3D_TEX_SWIZZLE_S1_X_Y 0x00000080
1816#define NV30_3D_TEX_SWIZZLE_S1_X_X 0x000000c0
1817#define NV30_3D_TEX_SWIZZLE_S0_W__MASK 0x00000300
1818#define NV30_3D_TEX_SWIZZLE_S0_W__SHIFT 8
1819#define NV30_3D_TEX_SWIZZLE_S0_W_ZERO 0x00000000
1820#define NV30_3D_TEX_SWIZZLE_S0_W_ONE 0x00000100
1821#define NV30_3D_TEX_SWIZZLE_S0_W_S1 0x00000200
1822#define NV30_3D_TEX_SWIZZLE_S0_Z__MASK 0x00000c00
1823#define NV30_3D_TEX_SWIZZLE_S0_Z__SHIFT 10
1824#define NV30_3D_TEX_SWIZZLE_S0_Z_ZERO 0x00000000
1825#define NV30_3D_TEX_SWIZZLE_S0_Z_ONE 0x00000400
1826#define NV30_3D_TEX_SWIZZLE_S0_Z_S1 0x00000800
1827#define NV30_3D_TEX_SWIZZLE_S0_Y__MASK 0x00003000
1828#define NV30_3D_TEX_SWIZZLE_S0_Y__SHIFT 12
1829#define NV30_3D_TEX_SWIZZLE_S0_Y_ZERO 0x00000000
1830#define NV30_3D_TEX_SWIZZLE_S0_Y_ONE 0x00001000
1831#define NV30_3D_TEX_SWIZZLE_S0_Y_S1 0x00002000
1832#define NV30_3D_TEX_SWIZZLE_S0_X__MASK 0x0000c000
1833#define NV30_3D_TEX_SWIZZLE_S0_X__SHIFT 14
1834#define NV30_3D_TEX_SWIZZLE_S0_X_ZERO 0x00000000
1835#define NV30_3D_TEX_SWIZZLE_S0_X_ONE 0x00004000
1836#define NV30_3D_TEX_SWIZZLE_S0_X_S1 0x00008000
1837#define NV30_3D_TEX_SWIZZLE_RECT_PITCH__MASK 0xffff0000
1838#define NV30_3D_TEX_SWIZZLE_RECT_PITCH__SHIFT 16
1839
1840#define NV30_3D_TEX_FILTER(i0) (0x00001a14 + 0x20*(i0))
1841#define NV30_3D_TEX_FILTER__ESIZE 0x00000020
1842#define NV30_3D_TEX_FILTER__LEN 0x00000008
1843#define NV30_3D_TEX_FILTER_LOD_BIAS__MASK 0x00000f00
1844#define NV30_3D_TEX_FILTER_LOD_BIAS__SHIFT 8
1845#define NV30_3D_TEX_FILTER_MIN__MASK 0x000f0000
1846#define NV30_3D_TEX_FILTER_MIN__SHIFT 16
1847#define NV30_3D_TEX_FILTER_MIN_NEAREST 0x00010000
1848#define NV30_3D_TEX_FILTER_MIN_LINEAR 0x00020000
1849#define NV30_3D_TEX_FILTER_MIN_NEAREST_MIPMAP_NEAREST 0x00030000
1850#define NV30_3D_TEX_FILTER_MIN_LINEAR_MIPMAP_NEAREST 0x00040000
1851#define NV30_3D_TEX_FILTER_MIN_NEAREST_MIPMAP_LINEAR 0x00050000
1852#define NV30_3D_TEX_FILTER_MIN_LINEAR_MIPMAP_LINEAR 0x00060000
1853#define NV30_3D_TEX_FILTER_MAG__MASK 0x0f000000
1854#define NV30_3D_TEX_FILTER_MAG__SHIFT 24
1855#define NV30_3D_TEX_FILTER_MAG_NEAREST 0x01000000
1856#define NV30_3D_TEX_FILTER_MAG_LINEAR 0x02000000
1857#define NV30_3D_TEX_FILTER_SIGNED_BLUE 0x10000000
1858#define NV30_3D_TEX_FILTER_SIGNED_GREEN 0x20000000
1859#define NV30_3D_TEX_FILTER_SIGNED_RED 0x40000000
1860#define NV30_3D_TEX_FILTER_SIGNED_ALPHA 0x80000000
1861
1862#define NV30_3D_TEX_NPOT_SIZE(i0) (0x00001a18 + 0x20*(i0))
1863#define NV30_3D_TEX_NPOT_SIZE__ESIZE 0x00000020
1864#define NV30_3D_TEX_NPOT_SIZE__LEN 0x00000008
1865#define NV30_3D_TEX_NPOT_SIZE_H__MASK 0x0000ffff
1866#define NV30_3D_TEX_NPOT_SIZE_H__SHIFT 0
1867#define NV30_3D_TEX_NPOT_SIZE_W__MASK 0xffff0000
1868#define NV30_3D_TEX_NPOT_SIZE_W__SHIFT 16
1869
1870#define NV30_3D_TEX_BORDER_COLOR(i0) (0x00001a1c + 0x20*(i0))
1871#define NV30_3D_TEX_BORDER_COLOR__ESIZE 0x00000020
1872#define NV30_3D_TEX_BORDER_COLOR__LEN 0x00000008
1873#define NV30_3D_TEX_BORDER_COLOR_B__MASK 0x000000ff
1874#define NV30_3D_TEX_BORDER_COLOR_B__SHIFT 0
1875#define NV30_3D_TEX_BORDER_COLOR_G__MASK 0x0000ff00
1876#define NV30_3D_TEX_BORDER_COLOR_G__SHIFT 8
1877#define NV30_3D_TEX_BORDER_COLOR_R__MASK 0x00ff0000
1878#define NV30_3D_TEX_BORDER_COLOR_R__SHIFT 16
1879#define NV30_3D_TEX_BORDER_COLOR_A__MASK 0xff000000
1880#define NV30_3D_TEX_BORDER_COLOR_A__SHIFT 24
1881
1882#define NV30_3D_VTX_ATTR_4F(i0) (0x00001c00 + 0x10*(i0))
1883#define NV30_3D_VTX_ATTR_4F__ESIZE 0x00000010
1884#define NV30_3D_VTX_ATTR_4F__LEN 0x00000010
1885
1886
1887#define NV30_3D_VTX_ATTR_4F_X(i0) (0x00001c00 + 0x10*(i0))
1888
1889#define NV30_3D_VTX_ATTR_4F_Y(i0) (0x00001c04 + 0x10*(i0))
1890
1891#define NV30_3D_VTX_ATTR_4F_Z(i0) (0x00001c08 + 0x10*(i0))
1892
1893#define NV30_3D_VTX_ATTR_4F_W(i0) (0x00001c0c + 0x10*(i0))
1894
1895#define NV30_3D_FP_CONTROL 0x00001d60
1896#define NV30_3D_FP_CONTROL_USED_REGS_MINUS1_DIV2__MASK 0x0000000f
1897#define NV30_3D_FP_CONTROL_USED_REGS_MINUS1_DIV2__SHIFT 0
1898#define NV30_3D_FP_CONTROL_USES_KIL 0x00000080
1899#define NV40_3D_FP_CONTROL_KIL 0x00000080
1900#define NV40_3D_FP_CONTROL_TEMP_COUNT__MASK 0xff000000
1901#define NV40_3D_FP_CONTROL_TEMP_COUNT__SHIFT 24
1902
1903#define NV30_3D_DEPTH_CONTROL 0x00001d78
1904#define NV30_3D_DEPTH_CONTROL_CLAMP 0x000000f0
1905
1906#define NV30_3D_MULTISAMPLE_CONTROL 0x00001d7c
1907#define NV30_3D_MULTISAMPLE_CONTROL_ENABLE 0x00000001
1908#define NV30_3D_MULTISAMPLE_CONTROL_SAMPLE_ALPHA_TO_COVERAGE 0x00000010
1909#define NV30_3D_MULTISAMPLE_CONTROL_SAMPLE_ALPHA_TO_ONE 0x00000100
1910#define NV30_3D_MULTISAMPLE_CONTROL_SAMPLE_COVERAGE__MASK 0xffff0000
1911#define NV30_3D_MULTISAMPLE_CONTROL_SAMPLE_COVERAGE__SHIFT 16
1912
1913#define NV30_3D_COORD_CONVENTIONS 0x00001d88
1914#define NV30_3D_COORD_CONVENTIONS_HEIGHT__MASK 0x00000fff
1915#define NV30_3D_COORD_CONVENTIONS_HEIGHT__SHIFT 0
1916#define NV30_3D_COORD_CONVENTIONS_ORIGIN__MASK 0x00001000
1917#define NV30_3D_COORD_CONVENTIONS_ORIGIN__SHIFT 12
1918#define NV30_3D_COORD_CONVENTIONS_ORIGIN_NORMAL 0x00000000
1919#define NV30_3D_COORD_CONVENTIONS_ORIGIN_INVERTED 0x00001000
1920#define NV30_3D_COORD_CONVENTIONS_CENTER__MASK 0x00010000
1921#define NV30_3D_COORD_CONVENTIONS_CENTER__SHIFT 16
1922#define NV30_3D_COORD_CONVENTIONS_CENTER_HALF_INTEGER 0x00000000
1923#define NV30_3D_COORD_CONVENTIONS_CENTER_INTEGER 0x00010000
1924
1925#define NV30_3D_CLEAR_DEPTH_VALUE 0x00001d8c
1926
1927#define NV30_3D_CLEAR_COLOR_VALUE 0x00001d90
1928#define NV30_3D_CLEAR_COLOR_VALUE_B__MASK 0x000000ff
1929#define NV30_3D_CLEAR_COLOR_VALUE_B__SHIFT 0
1930#define NV30_3D_CLEAR_COLOR_VALUE_G__MASK 0x0000ff00
1931#define NV30_3D_CLEAR_COLOR_VALUE_G__SHIFT 8
1932#define NV30_3D_CLEAR_COLOR_VALUE_R__MASK 0x00ff0000
1933#define NV30_3D_CLEAR_COLOR_VALUE_R__SHIFT 16
1934#define NV30_3D_CLEAR_COLOR_VALUE_A__MASK 0xff000000
1935#define NV30_3D_CLEAR_COLOR_VALUE_A__SHIFT 24
1936
1937#define NV30_3D_CLEAR_BUFFERS 0x00001d94
1938#define NV30_3D_CLEAR_BUFFERS_DEPTH 0x00000001
1939#define NV30_3D_CLEAR_BUFFERS_STENCIL 0x00000002
1940#define NV30_3D_CLEAR_BUFFERS_COLOR_R 0x00000010
1941#define NV30_3D_CLEAR_BUFFERS_COLOR_G 0x00000020
1942#define NV30_3D_CLEAR_BUFFERS_COLOR_B 0x00000040
1943#define NV30_3D_CLEAR_BUFFERS_COLOR_A 0x00000080
1944
1945#define NV30_3D_DO_VERTICES 0x00001dac
1946
1947#define NV30_3D_LINE_STIPPLE_ENABLE 0x00001db4
1948
1949#define NV30_3D_LINE_STIPPLE_PATTERN 0x00001db8
1950#define NV30_3D_LINE_STIPPLE_PATTERN_FACTOR__MASK 0x0000ffff
1951#define NV30_3D_LINE_STIPPLE_PATTERN_FACTOR__SHIFT 0
1952#define NV30_3D_LINE_STIPPLE_PATTERN_PATTERN__MASK 0xffff0000
1953#define NV30_3D_LINE_STIPPLE_PATTERN_PATTERN__SHIFT 16
1954
1955#define NV30_3D_BACK_MATERIAL_SHININESS(i0) (0x00001e20 + 0x4*(i0))
1956#define NV30_3D_BACK_MATERIAL_SHININESS__ESIZE 0x00000004
1957#define NV30_3D_BACK_MATERIAL_SHININESS__LEN 0x00000006
1958
1959#define NV30_3D_VTX_ATTR_1F(i0) (0x00001e40 + 0x4*(i0))
1960#define NV30_3D_VTX_ATTR_1F__ESIZE 0x00000004
1961#define NV30_3D_VTX_ATTR_1F__LEN 0x00000010
1962
1963#define NV30_3D_ENGINE 0x00001e94
1964#define NV30_3D_ENGINE_FP 0x00000001
1965#define NV30_3D_ENGINE_VP 0x00000002
1966#define NV30_3D_ENGINE_FIXED 0x00000004
1967
1968#define NV30_3D_VP_UPLOAD_FROM_ID 0x00001e9c
1969
1970#define NV30_3D_VP_START_FROM_ID 0x00001ea0
1971
1972#define NV30_3D_POINT_PARAMETERS(i0) (0x00001ec0 + 0x4*(i0))
1973#define NV30_3D_POINT_PARAMETERS__ESIZE 0x00000004
1974#define NV30_3D_POINT_PARAMETERS__LEN 0x00000008
1975
1976#define NV30_3D_POINT_SIZE 0x00001ee0
1977
1978#define NV30_3D_POINT_PARAMETERS_ENABLE 0x00001ee4
1979
1980#define NV30_3D_POINT_SPRITE 0x00001ee8
1981#define NV30_3D_POINT_SPRITE_ENABLE 0x00000001
1982#define NV30_3D_POINT_SPRITE_R_MODE__MASK 0x00000006
1983#define NV30_3D_POINT_SPRITE_R_MODE__SHIFT 1
1984#define NV30_3D_POINT_SPRITE_R_MODE_ZERO 0x00000000
1985#define NV30_3D_POINT_SPRITE_R_MODE_R 0x00000002
1986#define NV30_3D_POINT_SPRITE_R_MODE_S 0x00000004
1987#define NV30_3D_POINT_SPRITE_COORD_REPLACE_0 0x00000100
1988#define NV30_3D_POINT_SPRITE_COORD_REPLACE_1 0x00000200
1989#define NV30_3D_POINT_SPRITE_COORD_REPLACE_2 0x00000400
1990#define NV30_3D_POINT_SPRITE_COORD_REPLACE_3 0x00000800
1991#define NV30_3D_POINT_SPRITE_COORD_REPLACE_4 0x00001000
1992#define NV30_3D_POINT_SPRITE_COORD_REPLACE_5 0x00002000
1993#define NV30_3D_POINT_SPRITE_COORD_REPLACE_6 0x00004000
1994#define NV30_3D_POINT_SPRITE_COORD_REPLACE_7 0x00008000
1995
1996#define NV30_3D_VP_UPLOAD_CONST_ID 0x00001efc
1997
1998#define NV30_3D_VP_UPLOAD_CONST(i0) (0x00001f00 + 0x10*(i0))
1999#define NV30_3D_VP_UPLOAD_CONST__ESIZE 0x00000010
2000#define NV30_3D_VP_UPLOAD_CONST__LEN 0x00000004
2001
2002
2003#define NV30_3D_VP_UPLOAD_CONST_X(i0) (0x00001f00 + 0x10*(i0))
2004
2005#define NV30_3D_VP_UPLOAD_CONST_Y(i0) (0x00001f04 + 0x10*(i0))
2006
2007#define NV30_3D_VP_UPLOAD_CONST_Z(i0) (0x00001f08 + 0x10*(i0))
2008
2009#define NV30_3D_VP_UPLOAD_CONST_W(i0) (0x00001f0c + 0x10*(i0))
2010
2011#define NV30_3D_UNK1F80(i0) (0x00001f80 + 0x4*(i0))
2012#define NV30_3D_UNK1F80__ESIZE 0x00000004
2013#define NV30_3D_UNK1F80__LEN 0x00000010
2014
2015#define NV40_3D_TEX_CACHE_CTL 0x00001fd8
2016
2017#define NV40_3D_VP_ATTRIB_EN 0x00001ff0
2018
2019#define NV40_3D_VP_RESULT_EN 0x00001ff4
2020
2021
2022#endif /* NV30_40_3D_XML */
diff --git a/src/gallium/drivers/nvfx/nv30_fragtex.c b/src/gallium/drivers/nvfx/nv30_fragtex.c
deleted file mode 100644
index dd454b56e47..00000000000
--- a/src/gallium/drivers/nvfx/nv30_fragtex.c
+++ /dev/null
@@ -1,117 +0,0 @@
1#include "util/u_format.h"
2
3#include "nvfx_context.h"
4#include "nvfx_tex.h"
5#include "nvfx_resource.h"
6
7void
8nv30_sampler_state_init(struct pipe_context *pipe,
9 struct nvfx_sampler_state *ps,
10 const struct pipe_sampler_state *cso)
11{
12 if (cso->max_anisotropy >= 2)
13 {
14 if (cso->max_anisotropy >= 8)
15 ps->en |= NV30_3D_TEX_ENABLE_ANISO_8X;
16 else if (cso->max_anisotropy >= 4)
17 ps->en |= NV30_3D_TEX_ENABLE_ANISO_4X;
18 else if (cso->max_anisotropy >= 2)
19 ps->en |= NV30_3D_TEX_ENABLE_ANISO_2X;
20 }
21
22 ps->filt |= (int)(cso->lod_bias * 256.0) & 0x1fff;
23
24 ps->max_lod = (int)CLAMP(cso->max_lod, 0.0, 15.0);
25 ps->min_lod = (int)CLAMP(cso->min_lod, 0.0, 15.0);
26
27 ps->en |= NV30_3D_TEX_ENABLE_ENABLE;
28}
29
30void
31nv30_sampler_view_init(struct pipe_context *pipe,
32 struct nvfx_sampler_view *sv)
33{
34 struct pipe_resource* pt = sv->base.texture;
35 struct nvfx_texture_format *tf = &nvfx_texture_formats[sv->base.format];
36 unsigned txf;
37 unsigned level = pt->target == PIPE_TEXTURE_CUBE ? 0 : sv->base.u.tex.first_level;
38
39 assert(tf->fmt[0] >= 0);
40
41 txf = sv->u.init_fmt;
42 txf |= (level != sv->base.u.tex.last_level ? NV30_3D_TEX_FORMAT_MIPMAP : 0);
43 txf |= util_logbase2(u_minify(pt->width0, level)) << NV30_3D_TEX_FORMAT_BASE_SIZE_U__SHIFT;
44 txf |= util_logbase2(u_minify(pt->height0, level)) << NV30_3D_TEX_FORMAT_BASE_SIZE_V__SHIFT;
45 txf |= util_logbase2(u_minify(pt->depth0, level)) << NV30_3D_TEX_FORMAT_BASE_SIZE_W__SHIFT;
46 txf |= 0x10000;
47
48 sv->u.nv30.fmt[0] = tf->fmt[0] | txf;
49 sv->u.nv30.fmt[1] = tf->fmt[1] | txf;
50 sv->u.nv30.fmt[2] = tf->fmt[2] | txf;
51 sv->u.nv30.fmt[3] = tf->fmt[3] | txf;
52
53 sv->swizzle |= (nvfx_subresource_pitch(pt, 0) << NV30_3D_TEX_SWIZZLE_RECT_PITCH__SHIFT);
54
55 if(pt->height0 <= 1 || util_format_is_compressed(sv->base.format))
56 sv->u.nv30.rect = -1;
57 else
58 sv->u.nv30.rect = !!(pt->flags & NOUVEAU_RESOURCE_FLAG_LINEAR);
59
60 sv->lod_offset = sv->base.u.tex.first_level - level;
61 sv->max_lod_limit = sv->base.u.tex.last_level - level;
62}
63
64void
65nv30_fragtex_set(struct nvfx_context *nvfx, int unit)
66{
67 struct nvfx_sampler_state *ps = nvfx->tex_sampler[unit];
68 struct nvfx_sampler_view* sv = (struct nvfx_sampler_view*)nvfx->fragment_sampler_views[unit];
69 struct nouveau_bo *bo = ((struct nvfx_miptree *)sv->base.texture)->base.bo;
70 struct nouveau_channel* chan = nvfx->screen->base.channel;
71 struct nouveau_grobj *eng3d = nvfx->screen->eng3d;
72 unsigned txf;
73 unsigned tex_flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD;
74 unsigned use_rect;
75 unsigned max_lod = MIN2(ps->max_lod + sv->lod_offset, sv->max_lod_limit);
76 unsigned min_lod = MIN2(ps->min_lod + sv->lod_offset, max_lod) ;
77
78 if(sv->u.nv30.rect < 0)
79 {
80 /* in the case of compressed or 1D textures, we can get away with this,
81 * since the layout is the same
82 */
83 use_rect = ps->fmt;
84 }
85 else
86 {
87 static boolean warned = FALSE;
88 if( !!ps->fmt != sv->u.nv30.rect && !warned) {
89 warned = TRUE;
90 fprintf(stderr,
91 "Unimplemented: coordinate normalization mismatch. Possible reasons:\n"
92 "1. ARB_texture_non_power_of_two is being used despite the fact it isn't supported\n"
93 "2. The state tracker is not using the appropriate coordinate normalization\n"
94 "3. The state tracker is not supported\n");
95 }
96
97 use_rect = sv->u.nv30.rect;
98 }
99
100 txf = sv->u.nv30.fmt[ps->compare + (use_rect ? 2 : 0)];
101
102 MARK_RING(chan, 9, 2);
103 BEGIN_RING(chan, eng3d, NV30_3D_TEX_OFFSET(unit), 8);
104 OUT_RELOC(chan, bo, sv->offset, tex_flags | NOUVEAU_BO_LOW, 0, 0);
105 OUT_RELOC(chan, bo, txf,
106 tex_flags | NOUVEAU_BO_OR,
107 NV30_3D_TEX_FORMAT_DMA0, NV30_3D_TEX_FORMAT_DMA1);
108 OUT_RING(chan, (ps->wrap & sv->wrap_mask) | sv->wrap);
109 OUT_RING(chan, ps->en | (min_lod << NV30_3D_TEX_ENABLE_MIPMAP_MIN_LOD__SHIFT) | (max_lod << NV30_3D_TEX_ENABLE_MIPMAP_MAX_LOD__SHIFT));
110 OUT_RING(chan, sv->swizzle);
111 OUT_RING(chan, ps->filt | sv->filt);
112 OUT_RING(chan, sv->npot_size);
113 OUT_RING(chan, ps->bcol);
114
115 nvfx->hw_txf[unit] = txf;
116 nvfx->hw_samplers |= (1 << unit);
117}
diff --git a/src/gallium/drivers/nvfx/nv30_vertprog.h b/src/gallium/drivers/nvfx/nv30_vertprog.h
deleted file mode 100644
index e8c16b0341a..00000000000
--- a/src/gallium/drivers/nvfx/nv30_vertprog.h
+++ /dev/null
@@ -1,176 +0,0 @@
1#ifndef __NV30_SHADER_H__
2#define __NV30_SHADER_H__
3
4/* Vertex programs instruction set
5 *
6 * 128bit opcodes, split into 4 32-bit ones for ease of use.
7 *
8 * Non-native instructions
9 * ABS - MOV + NV40_VP_INST0_DEST_ABS
10 * POW - EX2 + MUL + LG2
11 * SUB - ADD, second source negated
12 * SWZ - MOV
13 * XPD -
14 *
15 * Register access
16 * - Only one INPUT can be accessed per-instruction (move extras into TEMPs)
17 * - Only one CONST can be accessed per-instruction (move extras into TEMPs)
18 *
19 * Relative Addressing
20 * According to the value returned for
21 * MAX_PROGRAM_NATIVE_ADDRESS_REGISTERS_ARB
22 *
23 * there are only two address registers available. The destination in the
24 * ARL instruction is set to TEMP <n> (The temp isn't actually written).
25 *
26 * When using vanilla ARB_v_p, the proprietary driver will squish both the
27 * available ADDRESS regs into the first hardware reg in the X and Y
28 * components.
29 *
30 * To use an address reg as an index into consts, the CONST_SRC is set to
31 * (const_base + offset) and INDEX_CONST is set.
32 *
33 * To access the second address reg use ADDR_REG_SELECT_1. A particular
34 * component of the address regs is selected with ADDR_SWZ.
35 *
36 * Only one address register can be accessed per instruction.
37 *
38 * Conditional execution (see NV_vertex_program{2,3} for details) Conditional
39 * execution of an instruction is enabled by setting COND_TEST_ENABLE, and
40 * selecting the condition which will allow the test to pass with
41 * COND_{FL,LT,...}. It is possible to swizzle the values in the condition
42 * register, which allows for testing against an individual component.
43 *
44 * Branching:
45 *
46 * The BRA/CAL instructions seem to follow a slightly different opcode
47 * layout. The destination instruction ID (IADDR) overlaps a source field.
48 * Instruction ID's seem to be numbered based on the UPLOAD_FROM_ID FIFO
49 * command, and is incremented automatically on each UPLOAD_INST FIFO
50 * command.
51 *
52 * Conditional branching is achieved by using the condition tests described
53 * above. There doesn't appear to be dedicated looping instructions, but
54 * this can be done using a temp reg + conditional branching.
55 *
56 * Subroutines may be uploaded before the main program itself, but the first
57 * executed instruction is determined by the PROGRAM_START_ID FIFO command.
58 *
59 */
60
61/* DWORD 0 */
62
63/* guess that this is the same as nv40 */
64#define NV30_VP_INST_INDEX_INPUT (1 << 27)
65
66#define NV30_VP_INST_ADDR_REG_SELECT_1 (1 << 24)
67#define NV30_VP_INST_SRC2_ABS (1 << 23) /* guess */
68#define NV30_VP_INST_SRC1_ABS (1 << 22) /* guess */
69#define NV30_VP_INST_SRC0_ABS (1 << 21) /* guess */
70#define NV30_VP_INST_VEC_RESULT (1 << 20)
71#define NV30_VP_INST_DEST_TEMP_ID_SHIFT 16
72#define NV30_VP_INST_DEST_TEMP_ID_MASK (0x0F << 16)
73#define NV30_VP_INST_COND_UPDATE_ENABLE (1<<15)
74#define NV30_VP_INST_VEC_DEST_TEMP_MASK (0x1F << 16)
75#define NV30_VP_INST_COND_TEST_ENABLE (1<<14)
76#define NV30_VP_INST_COND_SHIFT 11
77#define NV30_VP_INST_COND_MASK (0x07 << 11)
78#define NV30_VP_INST_COND_SWZ_X_SHIFT 9
79#define NV30_VP_INST_COND_SWZ_X_MASK (0x03 << 9)
80#define NV30_VP_INST_COND_SWZ_Y_SHIFT 7
81#define NV30_VP_INST_COND_SWZ_Y_MASK (0x03 << 7)
82#define NV30_VP_INST_COND_SWZ_Z_SHIFT 5
83#define NV30_VP_INST_COND_SWZ_Z_MASK (0x03 << 5)
84#define NV30_VP_INST_COND_SWZ_W_SHIFT 3
85#define NV30_VP_INST_COND_SWZ_W_MASK (0x03 << 3)
86#define NV30_VP_INST_COND_SWZ_ALL_SHIFT 3
87#define NV30_VP_INST_COND_SWZ_ALL_MASK (0xFF << 3)
88#define NV30_VP_INST_ADDR_SWZ_SHIFT 1
89#define NV30_VP_INST_ADDR_SWZ_MASK (0x03 << 1)
90#define NV30_VP_INST_SCA_OPCODEH_SHIFT 0
91#define NV30_VP_INST_SCA_OPCODEH_MASK (0x01 << 0)
92
93/* DWORD 1 */
94#define NV30_VP_INST_SCA_OPCODEL_SHIFT 28
95#define NV30_VP_INST_SCA_OPCODEL_MASK (0x0F << 28)
96#define NV30_VP_INST_VEC_OPCODE_SHIFT 23
97#define NV30_VP_INST_VEC_OPCODE_MASK (0x1F << 23)
98#define NV30_VP_INST_CONST_SRC_SHIFT 14
99#define NV30_VP_INST_CONST_SRC_MASK (0xFF << 14)
100#define NV30_VP_INST_INPUT_SRC_SHIFT 9 /*NV20*/
101#define NV30_VP_INST_INPUT_SRC_MASK (0x0F << 9) /*NV20*/
102#define NV30_VP_INST_SRC0H_SHIFT 0 /*NV20*/
103#define NV30_VP_INST_SRC0H_MASK (0x1FF << 0) /*NV20*/
104
105/* Please note: the IADDR fields overlap other fields because they are used
106 * only for branch instructions. See Branching: label above
107 *
108 * DWORD 2
109 */
110#define NV30_VP_INST_SRC0L_SHIFT 26 /*NV20*/
111#define NV30_VP_INST_SRC0L_MASK (0x3F <<26) /* NV30_VP_SRC0_LOW_MASK << 26 */
112#define NV30_VP_INST_SRC1_SHIFT 11 /*NV20*/
113#define NV30_VP_INST_SRC1_MASK (0x7FFF<<11) /*NV20*/
114#define NV30_VP_INST_SRC2H_SHIFT 0 /*NV20*/
115#define NV30_VP_INST_SRC2H_MASK (0x7FF << 0) /* NV30_VP_SRC2_HIGH_MASK >> 4*/
116#define NV30_VP_INST_IADDR_SHIFT 2
117#define NV30_VP_INST_IADDR_MASK (0x1FF << 2) /* NV30_VP_SRC2_LOW_MASK << 28 */
118
119/* DWORD 3 */
120#define NV30_VP_INST_SRC2L_SHIFT 28 /*NV20*/
121#define NV30_VP_INST_SRC2L_MASK (0x0F <<28) /*NV20*/
122#define NV30_VP_INST_STEMP_WRITEMASK_SHIFT 24
123#define NV30_VP_INST_STEMP_WRITEMASK_MASK (0x0F << 24)
124#define NV30_VP_INST_VTEMP_WRITEMASK_SHIFT 20
125#define NV30_VP_INST_VTEMP_WRITEMASK_MASK (0x0F << 20)
126#define NV30_VP_INST_SDEST_WRITEMASK_SHIFT 16
127#define NV30_VP_INST_SDEST_WRITEMASK_MASK (0x0F << 16)
128#define NV30_VP_INST_VDEST_WRITEMASK_SHIFT 12 /*NV20*/
129#define NV30_VP_INST_VDEST_WRITEMASK_MASK (0x0F << 12) /*NV20*/
130#define NV30_VP_INST_DEST_SHIFT 2
131#define NV30_VP_INST_DEST_MASK (0x1F << 2)
132# define NV30_VP_INST_DEST_POS 0
133# define NV30_VP_INST_DEST_BFC0 1
134# define NV30_VP_INST_DEST_BFC1 2
135# define NV30_VP_INST_DEST_COL0 3
136# define NV30_VP_INST_DEST_COL1 4
137# define NV30_VP_INST_DEST_FOGC 5
138# define NV30_VP_INST_DEST_PSZ 6
139# define NV30_VP_INST_DEST_TC(n) (8+(n))
140# define NV30_VP_INST_DEST_CLP(n) (17 + (n))
141
142/* guess that this is the same as nv40 */
143#define NV30_VP_INST_INDEX_CONST (1 << 1)
144
145/* Useful to split the source selection regs into their pieces */
146#define NV30_VP_SRC0_HIGH_SHIFT 6
147#define NV30_VP_SRC0_HIGH_MASK 0x00007FC0
148#define NV30_VP_SRC0_LOW_MASK 0x0000003F
149#define NV30_VP_SRC2_HIGH_SHIFT 4
150#define NV30_VP_SRC2_HIGH_MASK 0x00007FF0
151#define NV30_VP_SRC2_LOW_MASK 0x0000000F
152
153
154/* Source-register definition - matches NV20 exactly */
155#define NV30_VP_SRC_NEGATE (1<<14)
156#define NV30_VP_SRC_SWZ_X_SHIFT 12
157#define NV30_VP_SRC_REG_SWZ_X_MASK (0x03 <<12)
158#define NV30_VP_SRC_SWZ_Y_SHIFT 10
159#define NV30_VP_SRC_REG_SWZ_Y_MASK (0x03 <<10)
160#define NV30_VP_SRC_SWZ_Z_SHIFT 8
161#define NV30_VP_SRC_REG_SWZ_Z_MASK (0x03 << 8)
162#define NV30_VP_SRC_SWZ_W_SHIFT 6
163#define NV30_VP_SRC_REG_SWZ_W_MASK (0x03 << 6)
164#define NV30_VP_SRC_REG_SWZ_ALL_SHIFT 6
165#define NV30_VP_SRC_REG_SWZ_ALL_MASK (0xFF << 6)
166#define NV30_VP_SRC_TEMP_SRC_SHIFT 2
167#define NV30_VP_SRC_REG_TEMP_ID_MASK (0x0F << 0)
168#define NV30_VP_SRC_REG_TYPE_SHIFT 0
169#define NV30_VP_SRC_REG_TYPE_MASK (0x03 << 0)
170#define NV30_VP_SRC_REG_TYPE_TEMP 1
171#define NV30_VP_SRC_REG_TYPE_INPUT 2
172#define NV30_VP_SRC_REG_TYPE_CONST 3 /* guess */
173
174#include "nvfx_shader.h"
175
176#endif
diff --git a/src/gallium/drivers/nvfx/nv40_fragtex.c b/src/gallium/drivers/nvfx/nv40_fragtex.c
deleted file mode 100644
index a2da4457324..00000000000
--- a/src/gallium/drivers/nvfx/nv40_fragtex.c
+++ /dev/null
@@ -1,104 +0,0 @@
1#include "util/u_format.h"
2#include "nvfx_context.h"
3#include "nvfx_tex.h"
4#include "nvfx_resource.h"
5
6void
7nv40_sampler_state_init(struct pipe_context *pipe,
8 struct nvfx_sampler_state *ps,
9 const struct pipe_sampler_state *cso)
10{
11 if (cso->max_anisotropy >= 2) {
12 /* no idea, binary driver sets it, works without it.. meh.. */
13 ps->wrap |= (1 << 5);
14
15 if (cso->max_anisotropy >= 16)
16 ps->en |= NV40_3D_TEX_ENABLE_ANISO_16X;
17 else if (cso->max_anisotropy >= 12)
18 ps->en |= NV40_3D_TEX_ENABLE_ANISO_12X;
19 else if (cso->max_anisotropy >= 10)
20 ps->en |= NV40_3D_TEX_ENABLE_ANISO_10X;
21 else if (cso->max_anisotropy >= 8)
22 ps->en |= NV40_3D_TEX_ENABLE_ANISO_8X;
23 else if (cso->max_anisotropy >= 6)
24 ps->en |= NV40_3D_TEX_ENABLE_ANISO_6X;
25 else if (cso->max_anisotropy >= 4)
26 ps->en |= NV40_3D_TEX_ENABLE_ANISO_4X;
27 else
28 ps->en |= NV40_3D_TEX_ENABLE_ANISO_2X;
29 }
30
31 ps->filt |= (int)(cso->lod_bias * 256.0) & 0x1fff;
32
33 ps->max_lod = (int)(CLAMP(cso->max_lod, 0.0, 15.0 + (255.0 / 256.0)) * 256.0);
34 ps->min_lod = (int)(CLAMP(cso->min_lod, 0.0, 15.0 + (255.0 / 256.0)) * 256.0);
35
36 ps->en |= NV40_3D_TEX_ENABLE_ENABLE;
37}
38
39void
40nv40_sampler_view_init(struct pipe_context *pipe,
41 struct nvfx_sampler_view *sv)
42{
43 struct pipe_resource* pt = sv->base.texture;
44 struct nvfx_miptree* mt = (struct nvfx_miptree*)pt;
45 struct nvfx_texture_format *tf = &nvfx_texture_formats[sv->base.format];
46 unsigned txf;
47 unsigned level = pt->target == PIPE_TEXTURE_CUBE ? 0 : sv->base.u.tex.first_level;
48 assert(tf->fmt[4] >= 0);
49
50 txf = sv->u.init_fmt;
51 txf |= 0x8000;
52 if(pt->target == PIPE_TEXTURE_CUBE)
53 txf |= ((pt->last_level + 1) << NV40_3D_TEX_FORMAT_MIPMAP_COUNT__SHIFT);
54 else
55 txf |= (((sv->base.u.tex.last_level - sv->base.u.tex.first_level) + 1) << NV40_3D_TEX_FORMAT_MIPMAP_COUNT__SHIFT);
56
57 if (!mt->linear_pitch)
58 sv->u.nv40.npot_size2 = 0;
59 else {
60 sv->u.nv40.npot_size2 = mt->linear_pitch;
61 txf |= NV40_3D_TEX_FORMAT_LINEAR;
62 }
63
64 sv->u.nv40.fmt[0] = tf->fmt[4] | txf;
65 sv->u.nv40.fmt[1] = tf->fmt[5] | txf;
66
67 sv->u.nv40.npot_size2 |= (u_minify(pt->depth0, level) << NV40_3D_TEX_SIZE1_DEPTH__SHIFT);
68
69 sv->lod_offset = (sv->base.u.tex.first_level - level) * 256;
70 sv->max_lod_limit = (sv->base.u.tex.last_level - level) * 256;
71}
72
73void
74nv40_fragtex_set(struct nvfx_context *nvfx, int unit)
75{
76 struct nouveau_channel* chan = nvfx->screen->base.channel;
77 struct nouveau_grobj *eng3d = nvfx->screen->eng3d;
78 struct nvfx_sampler_state *ps = nvfx->tex_sampler[unit];
79 struct nvfx_sampler_view* sv = (struct nvfx_sampler_view*)nvfx->fragment_sampler_views[unit];
80 struct nouveau_bo *bo = ((struct nvfx_miptree *)sv->base.texture)->base.bo;
81 unsigned tex_flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD;
82 unsigned txf;
83 unsigned max_lod = MIN2(ps->max_lod + sv->lod_offset, sv->max_lod_limit);
84 unsigned min_lod = MIN2(ps->min_lod + sv->lod_offset, max_lod);
85
86 txf = sv->u.nv40.fmt[ps->compare] | ps->fmt;
87
88 MARK_RING(chan, 11, 2);
89 BEGIN_RING(chan, eng3d, NV30_3D_TEX_OFFSET(unit), 8);
90 OUT_RELOC(chan, bo, sv->offset, tex_flags | NOUVEAU_BO_LOW, 0, 0);
91 OUT_RELOC(chan, bo, txf, tex_flags | NOUVEAU_BO_OR,
92 NV30_3D_TEX_FORMAT_DMA0, NV30_3D_TEX_FORMAT_DMA1);
93 OUT_RING(chan, (ps->wrap & sv->wrap_mask) | sv->wrap);
94 OUT_RING(chan, ps->en | (min_lod << 19) | (max_lod << 7));
95 OUT_RING(chan, sv->swizzle);
96 OUT_RING(chan, ps->filt | sv->filt);
97 OUT_RING(chan, sv->npot_size);
98 OUT_RING(chan, ps->bcol);
99 BEGIN_RING(chan, eng3d, NV40_3D_TEX_SIZE1(unit), 1);
100 OUT_RING(chan, sv->u.nv40.npot_size2);
101
102 nvfx->hw_txf[unit] = txf;
103 nvfx->hw_samplers |= (1 << unit);
104}
diff --git a/src/gallium/drivers/nvfx/nv40_vertprog.h b/src/gallium/drivers/nvfx/nv40_vertprog.h
deleted file mode 100644
index c1f2208f513..00000000000
--- a/src/gallium/drivers/nvfx/nv40_vertprog.h
+++ /dev/null
@@ -1,178 +0,0 @@
1#ifndef __NV40_SHADER_H__
2#define __NV40_SHADER_H__
3
4/* Vertex programs instruction set
5 *
6 * The NV40 instruction set is very similar to NV30. Most fields are in
7 * a slightly different position in the instruction however.
8 *
9 * Merged instructions
10 * In some cases it is possible to put two instructions into one opcode
11 * slot. The rules for when this is OK is not entirely clear to me yet.
12 *
13 * There are separate writemasks and dest temp register fields for each
14 * grouping of instructions. There is however only one field with the
15 * ID of a result register. Writing to temp/result regs is selected by
16 * setting VEC_RESULT/SCA_RESULT.
17 *
18 * Temporary registers
19 * The source/dest temp register fields have been extended by 1 bit, to
20 * give a total of 32 temporary registers.
21 *
22 * Relative Addressing
23 * NV40 can use an address register to index into vertex attribute regs.
24 * This is done by putting the offset value into INPUT_SRC and setting
25 * the INDEX_INPUT flag.
26 *
27 * Conditional execution (see NV_vertex_program{2,3} for details)
28 * There is a second condition code register on NV40, it's use is enabled
29 * by setting the COND_REG_SELECT_1 flag.
30 *
31 * Texture lookup
32 * TODO
33 */
34
35/* ---- OPCODE BITS 127:96 / data DWORD 0 --- */
36#define NV40_VP_INST_VEC_RESULT (1 << 30)
37/* uncertain.. */
38#define NV40_VP_INST_COND_UPDATE_ENABLE ((1 << 14)|1<<29)
39/* use address reg as index into attribs */
40#define NV40_VP_INST_INDEX_INPUT (1 << 27)
41#define NV40_VP_INST_SATURATE (1 << 26)
42#define NV40_VP_INST_COND_REG_SELECT_1 (1 << 25)
43#define NV40_VP_INST_ADDR_REG_SELECT_1 (1 << 24)
44#define NV40_VP_INST_SRC2_ABS (1 << 23)
45#define NV40_VP_INST_SRC1_ABS (1 << 22)
46#define NV40_VP_INST_SRC0_ABS (1 << 21)
47#define NV40_VP_INST_VEC_DEST_TEMP_SHIFT 15
48#define NV40_VP_INST_VEC_DEST_TEMP_MASK (0x3F << 15)
49#define NV40_VP_INST_COND_TEST_ENABLE (1 << 13)
50#define NV40_VP_INST_COND_SHIFT 10
51#define NV40_VP_INST_COND_MASK (0x7 << 10)
52#define NV40_VP_INST_COND_SWZ_X_SHIFT 8
53#define NV40_VP_INST_COND_SWZ_X_MASK (3 << 8)
54#define NV40_VP_INST_COND_SWZ_Y_SHIFT 6
55#define NV40_VP_INST_COND_SWZ_Y_MASK (3 << 6)
56#define NV40_VP_INST_COND_SWZ_Z_SHIFT 4
57#define NV40_VP_INST_COND_SWZ_Z_MASK (3 << 4)
58#define NV40_VP_INST_COND_SWZ_W_SHIFT 2
59#define NV40_VP_INST_COND_SWZ_W_MASK (3 << 2)
60#define NV40_VP_INST_COND_SWZ_ALL_SHIFT 2
61#define NV40_VP_INST_COND_SWZ_ALL_MASK (0xFF << 2)
62#define NV40_VP_INST_ADDR_SWZ_SHIFT 0
63#define NV40_VP_INST_ADDR_SWZ_MASK (0x03 << 0)
64#define NV40_VP_INST0_KNOWN ( \
65 NV40_VP_INST_INDEX_INPUT | \
66 NV40_VP_INST_COND_REG_SELECT_1 | \
67 NV40_VP_INST_ADDR_REG_SELECT_1 | \
68 NV40_VP_INST_SRC2_ABS | \
69 NV40_VP_INST_SRC1_ABS | \
70 NV40_VP_INST_SRC0_ABS | \
71 NV40_VP_INST_VEC_DEST_TEMP_MASK | \
72 NV40_VP_INST_COND_TEST_ENABLE | \
73 NV40_VP_INST_COND_MASK | \
74 NV40_VP_INST_COND_SWZ_ALL_MASK | \
75 NV40_VP_INST_ADDR_SWZ_MASK)
76
77/* ---- OPCODE BITS 95:64 / data DWORD 1 --- */
78#define NV40_VP_INST_VEC_OPCODE_SHIFT 22
79#define NV40_VP_INST_VEC_OPCODE_MASK (0x1F << 22)
80#define NV40_VP_INST_SCA_OPCODE_SHIFT 27
81#define NV40_VP_INST_SCA_OPCODE_MASK (0x1F << 27)
82#define NV40_VP_INST_CONST_SRC_SHIFT 12
83#define NV40_VP_INST_CONST_SRC_MASK (0xFF << 12)
84#define NV40_VP_INST_INPUT_SRC_SHIFT 8
85#define NV40_VP_INST_INPUT_SRC_MASK (0x0F << 8)
86#define NV40_VP_INST_SRC0H_SHIFT 0
87#define NV40_VP_INST_SRC0H_MASK (0xFF << 0)
88#define NV40_VP_INST1_KNOWN ( \
89 NV40_VP_INST_VEC_OPCODE_MASK | \
90 NV40_VP_INST_SCA_OPCODE_MASK | \
91 NV40_VP_INST_CONST_SRC_MASK | \
92 NV40_VP_INST_INPUT_SRC_MASK | \
93 NV40_VP_INST_SRC0H_MASK \
94 )
95
96/* ---- OPCODE BITS 63:32 / data DWORD 2 --- */
97#define NV40_VP_INST_SRC0L_SHIFT 23
98#define NV40_VP_INST_SRC0L_MASK (0x1FF << 23)
99#define NV40_VP_INST_SRC1_SHIFT 6
100#define NV40_VP_INST_SRC1_MASK (0x1FFFF << 6)
101#define NV40_VP_INST_SRC2H_SHIFT 0
102#define NV40_VP_INST_SRC2H_MASK (0x3F << 0)
103#define NV40_VP_INST_IADDRH_SHIFT 0
104#define NV40_VP_INST_IADDRH_MASK (0x3F << 0)
105
106/* ---- OPCODE BITS 31:0 / data DWORD 3 --- */
107#define NV40_VP_INST_IADDRL_SHIFT 29
108#define NV40_VP_INST_IADDRL_MASK (7 << 29)
109#define NV40_VP_INST_SRC2L_SHIFT 21
110#define NV40_VP_INST_SRC2L_MASK (0x7FF << 21)
111#define NV40_VP_INST_SCA_WRITEMASK_SHIFT 17
112#define NV40_VP_INST_SCA_WRITEMASK_MASK (0xF << 17)
113# define NV40_VP_INST_SCA_WRITEMASK_X (1 << 20)
114# define NV40_VP_INST_SCA_WRITEMASK_Y (1 << 19)
115# define NV40_VP_INST_SCA_WRITEMASK_Z (1 << 18)
116# define NV40_VP_INST_SCA_WRITEMASK_W (1 << 17)
117#define NV40_VP_INST_VEC_WRITEMASK_SHIFT 13
118#define NV40_VP_INST_VEC_WRITEMASK_MASK (0xF << 13)
119# define NV40_VP_INST_VEC_WRITEMASK_X (1 << 16)
120# define NV40_VP_INST_VEC_WRITEMASK_Y (1 << 15)
121# define NV40_VP_INST_VEC_WRITEMASK_Z (1 << 14)
122# define NV40_VP_INST_VEC_WRITEMASK_W (1 << 13)
123#define NV40_VP_INST_SCA_RESULT (1 << 12)
124#define NV40_VP_INST_SCA_DEST_TEMP_SHIFT 7
125#define NV40_VP_INST_SCA_DEST_TEMP_MASK (0x1F << 7)
126#define NV40_VP_INST_DEST_SHIFT 2
127#define NV40_VP_INST_DEST_MASK (31 << 2)
128# define NV40_VP_INST_DEST_POS 0
129# define NV40_VP_INST_DEST_COL0 1
130# define NV40_VP_INST_DEST_COL1 2
131# define NV40_VP_INST_DEST_BFC0 3
132# define NV40_VP_INST_DEST_BFC1 4
133# define NV40_VP_INST_DEST_FOGC 5
134# define NV40_VP_INST_DEST_PSZ 6
135# define NV40_VP_INST_DEST_TC0 7
136# define NV40_VP_INST_DEST_TC(n) (7+n)
137# define NV40_VP_INST_DEST_TEMP 0x1F
138#define NV40_VP_INST_INDEX_CONST (1 << 1)
139#define NV40_VP_INST3_KNOWN ( \
140 NV40_VP_INST_SRC2L_MASK |\
141 NV40_VP_INST_SCA_WRITEMASK_MASK |\
142 NV40_VP_INST_VEC_WRITEMASK_MASK |\
143 NV40_VP_INST_SCA_DEST_TEMP_MASK |\
144 NV40_VP_INST_DEST_MASK |\
145 NV40_VP_INST_INDEX_CONST)
146
147/* Useful to split the source selection regs into their pieces */
148#define NV40_VP_SRC0_HIGH_SHIFT 9
149#define NV40_VP_SRC0_HIGH_MASK 0x0001FE00
150#define NV40_VP_SRC0_LOW_MASK 0x000001FF
151#define NV40_VP_SRC2_HIGH_SHIFT 11
152#define NV40_VP_SRC2_HIGH_MASK 0x0001F800
153#define NV40_VP_SRC2_LOW_MASK 0x000007FF
154
155/* Source selection - these are the bits you fill NV40_VP_INST_SRCn with */
156#define NV40_VP_SRC_NEGATE (1 << 16)
157#define NV40_VP_SRC_SWZ_X_SHIFT 14
158#define NV40_VP_SRC_SWZ_X_MASK (3 << 14)
159#define NV40_VP_SRC_SWZ_Y_SHIFT 12
160#define NV40_VP_SRC_SWZ_Y_MASK (3 << 12)
161#define NV40_VP_SRC_SWZ_Z_SHIFT 10
162#define NV40_VP_SRC_SWZ_Z_MASK (3 << 10)
163#define NV40_VP_SRC_SWZ_W_SHIFT 8
164#define NV40_VP_SRC_SWZ_W_MASK (3 << 8)
165#define NV40_VP_SRC_SWZ_ALL_SHIFT 8
166#define NV40_VP_SRC_SWZ_ALL_MASK (0xFF << 8)
167#define NV40_VP_SRC_TEMP_SRC_SHIFT 2
168#define NV40_VP_SRC_TEMP_SRC_MASK (0x1F << 2)
169#define NV40_VP_SRC_REG_TYPE_SHIFT 0
170#define NV40_VP_SRC_REG_TYPE_MASK (3 << 0)
171# define NV40_VP_SRC_REG_TYPE_UNK0 0
172# define NV40_VP_SRC_REG_TYPE_TEMP 1
173# define NV40_VP_SRC_REG_TYPE_INPUT 2
174# define NV40_VP_SRC_REG_TYPE_CONST 3
175
176#include "nvfx_shader.h"
177
178#endif
diff --git a/src/gallium/drivers/nvfx/nvfx_buffer.c b/src/gallium/drivers/nvfx/nvfx_buffer.c
deleted file mode 100644
index 76b7f4507c4..00000000000
--- a/src/gallium/drivers/nvfx/nvfx_buffer.c
+++ /dev/null
@@ -1,98 +0,0 @@
1
2#include "util/u_inlines.h"
3#include "util/u_memory.h"
4#include "util/u_math.h"
5
6#include "nouveau/nouveau_screen.h"
7#include "nouveau/nouveau_winsys.h"
8#include "nvfx_resource.h"
9#include "nvfx_screen.h"
10
11void nvfx_buffer_destroy(struct pipe_screen *pscreen,
12 struct pipe_resource *presource)
13{
14 struct nvfx_buffer *buffer = nvfx_buffer(presource);
15
16 if(!(buffer->base.base.flags & NVFX_RESOURCE_FLAG_USER))
17 align_free(buffer->data);
18 nouveau_screen_bo_release(pscreen, buffer->base.bo);
19 FREE(buffer);
20}
21
22struct pipe_resource *
23nvfx_buffer_create(struct pipe_screen *pscreen,
24 const struct pipe_resource *template)
25{
26 struct nvfx_screen* screen = nvfx_screen(pscreen);
27 struct nvfx_buffer* buffer;
28
29 buffer = CALLOC_STRUCT(nvfx_buffer);
30 if (!buffer)
31 return NULL;
32
33 buffer->base.base = *template;
34 buffer->base.base.flags |= NOUVEAU_RESOURCE_FLAG_LINEAR;
35 pipe_reference_init(&buffer->base.base.reference, 1);
36 buffer->base.base.screen = pscreen;
37 buffer->size = util_format_get_stride(template->format, template->width0);
38 buffer->bytes_to_draw_until_static = buffer->size * screen->static_reuse_threshold;
39 buffer->data = align_malloc(buffer->size, 16);
40
41 return &buffer->base.base;
42}
43
44
45struct pipe_resource *
46nvfx_user_buffer_create(struct pipe_screen *pscreen,
47 void *ptr,
48 unsigned bytes,
49 unsigned usage)
50{
51 struct nvfx_screen* screen = nvfx_screen(pscreen);
52 struct nvfx_buffer* buffer;
53
54 buffer = CALLOC_STRUCT(nvfx_buffer);
55 if (!buffer)
56 return NULL;
57
58 pipe_reference_init(&buffer->base.base.reference, 1);
59 buffer->base.base.flags =
60 NOUVEAU_RESOURCE_FLAG_LINEAR | NVFX_RESOURCE_FLAG_USER;
61 buffer->base.base.screen = pscreen;
62 buffer->base.base.format = PIPE_FORMAT_R8_UNORM;
63 buffer->base.base.usage = PIPE_USAGE_IMMUTABLE;
64 buffer->base.base.bind = usage;
65 buffer->base.base.width0 = bytes;
66 buffer->base.base.height0 = 1;
67 buffer->base.base.depth0 = 1;
68 buffer->base.base.array_size = 1;
69 buffer->data = ptr;
70 buffer->size = bytes;
71 buffer->bytes_to_draw_until_static = bytes * screen->static_reuse_threshold;
72 buffer->dirty_end = bytes;
73
74 return &buffer->base.base;
75}
76
77void nvfx_buffer_upload(struct nvfx_buffer* buffer)
78{
79 unsigned dirty = buffer->dirty_end - buffer->dirty_begin;
80 if(!buffer->base.bo)
81 {
82 buffer->base.bo = nouveau_screen_bo_new(buffer->base.base.screen,
83 16,
84 buffer->base.base.usage,
85 buffer->base.base.bind,
86 buffer->base.base.width0);
87 }
88
89 if(dirty)
90 {
91 // TODO: may want to use a temporary in some cases
92 nouveau_bo_map(buffer->base.bo, NOUVEAU_BO_WR
93 | (buffer->dirty_unsynchronized ? NOUVEAU_BO_NOSYNC : 0));
94 memcpy((uint8_t*)buffer->base.bo->map + buffer->dirty_begin, buffer->data + buffer->dirty_begin, dirty);
95 nouveau_bo_unmap(buffer->base.bo);
96 buffer->dirty_begin = buffer->dirty_end = 0;
97 }
98}
diff --git a/src/gallium/drivers/nvfx/nvfx_clear.c b/src/gallium/drivers/nvfx/nvfx_clear.c
deleted file mode 100644
index 46f23e38260..00000000000
--- a/src/gallium/drivers/nvfx/nvfx_clear.c
+++ /dev/null
@@ -1,14 +0,0 @@
1#include "pipe/p_context.h"
2#include "pipe/p_defines.h"
3#include "pipe/p_state.h"
4#include "util/u_clear.h"
5
6#include "nvfx_context.h"
7
8void
9nvfx_clear(struct pipe_context *pipe, unsigned buffers,
10 const union pipe_color_union *color, double depth, unsigned stencil)
11{
12 util_clear(pipe, &nvfx_context(pipe)->framebuffer, buffers, color, depth,
13 stencil);
14}
diff --git a/src/gallium/drivers/nvfx/nvfx_context.c b/src/gallium/drivers/nvfx/nvfx_context.c
deleted file mode 100644
index 36209cb1792..00000000000
--- a/src/gallium/drivers/nvfx/nvfx_context.c
+++ /dev/null
@@ -1,124 +0,0 @@
1#include "draw/draw_context.h"
2#include "pipe/p_defines.h"
3#include "util/u_framebuffer.h"
4#include "vl/vl_decoder.h"
5#include "vl/vl_video_buffer.h"
6
7#include "nvfx_context.h"
8#include "nvfx_screen.h"
9#include "nvfx_resource.h"
10
11static void
12nvfx_flush(struct pipe_context *pipe,
13 struct pipe_fence_handle **fence)
14{
15 struct nvfx_context *nvfx = nvfx_context(pipe);
16 struct nvfx_screen *screen = nvfx->screen;
17 struct nouveau_channel *chan = screen->base.channel;
18 /*struct nouveau_grobj *eng3d = screen->eng3d;*/
19
20 /* XXX: we need to actually be intelligent here */
21 /* XXX This flag wasn't set by the state tracker anyway. */
22 /*if (flags & PIPE_FLUSH_TEXTURE_CACHE) {
23 BEGIN_RING(chan, eng3d, 0x1fd8, 1);
24 OUT_RING(chan, 2);
25 BEGIN_RING(chan, eng3d, 0x1fd8, 1);
26 OUT_RING(chan, 1);
27 }*/
28
29 if (fence) {
30 /* horrific hack to make glFinish() work in the absence of
31 * having proper fences in nvfx. a pending rewrite will
32 * fix this properly, but may be a while off.
33 */
34 MARK_RING(chan, 1, 1);
35 OUT_RELOC(chan, screen->fence, 0, NOUVEAU_BO_WR |
36 NOUVEAU_BO_DUMMY, 0, 0);
37 FIRE_RING(chan);
38 nouveau_bo_map(screen->fence, NOUVEAU_BO_RDWR);
39 nouveau_bo_unmap(screen->fence);
40 *fence = NULL;
41 } else {
42 FIRE_RING(chan);
43 }
44}
45
46static void
47nvfx_destroy(struct pipe_context *pipe)
48{
49 struct nvfx_context *nvfx = nvfx_context(pipe);
50
51 if(nvfx->dummy_fs)
52 pipe->delete_fs_state(pipe, nvfx->dummy_fs);
53
54 for(unsigned i = 0; i < nvfx->vtxbuf_nr; ++i)
55 pipe_resource_reference(&nvfx->vtxbuf[i].buffer, 0);
56 pipe_resource_reference(&nvfx->idxbuf.buffer, 0);
57 util_unreference_framebuffer_state(&nvfx->framebuffer);
58 for(unsigned i = 0; i < PIPE_MAX_SAMPLERS; ++i)
59 pipe_sampler_view_reference(&nvfx->fragment_sampler_views[i], 0);
60
61 if (nvfx->draw)
62 draw_destroy(nvfx->draw);
63
64 if(nvfx->screen->cur_ctx == nvfx)
65 nvfx->screen->cur_ctx = NULL;
66
67 FREE(nvfx);
68}
69
70struct pipe_context *
71nvfx_create(struct pipe_screen *pscreen, void *priv)
72{
73 struct nvfx_screen *screen = nvfx_screen(pscreen);
74 struct nvfx_context *nvfx;
75
76 nvfx = CALLOC(1, sizeof(struct nvfx_context));
77 if (!nvfx)
78 return NULL;
79 nvfx->screen = screen;
80
81 nvfx->pipe.screen = pscreen;
82 nvfx->pipe.priv = priv;
83 nvfx->pipe.destroy = nvfx_destroy;
84 nvfx->pipe.draw_vbo = nvfx_draw_vbo;
85 nvfx->pipe.clear = nvfx_clear;
86 nvfx->pipe.flush = nvfx_flush;
87
88 nvfx->is_nv4x = screen->is_nv4x;
89 nvfx->use_nv4x = screen->use_nv4x;
90 /* TODO: it seems that nv30 might have fixed function clipping usable with vertex programs
91 * However, my code for that doesn't work, so use vp clipping for all cards, which works.
92 */
93 nvfx->use_vp_clipping = TRUE;
94
95 nvfx_init_query_functions(nvfx);
96 nvfx_init_surface_functions(nvfx);
97 nvfx_init_state_functions(nvfx);
98 nvfx_init_sampling_functions(nvfx);
99 nvfx_init_vbo_functions(nvfx);
100 nvfx_init_fragprog_functions(nvfx);
101 nvfx_init_vertprog_functions(nvfx);
102 nvfx_init_resource_functions(&nvfx->pipe);
103 nvfx_init_transfer_functions(&nvfx->pipe);
104
105 /* Create, configure, and install fallback swtnl path */
106 nvfx->draw = draw_create(&nvfx->pipe);
107 draw_wide_point_threshold(nvfx->draw, 9999999.0);
108 draw_wide_line_threshold(nvfx->draw, 9999999.0);
109 draw_enable_line_stipple(nvfx->draw, FALSE);
110 draw_enable_point_sprites(nvfx->draw, FALSE);
111 draw_set_rasterize_stage(nvfx->draw, nvfx_draw_render_stage(nvfx));
112
113 /* set these to that we init them on first validation */
114 nvfx->state.scissor_enabled = ~0;
115 nvfx->hw_pointsprite_control = -1;
116 nvfx->hw_vp_output = -1;
117 nvfx->use_vertex_buffers = -1;
118 nvfx->relocs_needed = NVFX_RELOCATE_ALL;
119
120 LIST_INITHEAD(&nvfx->render_cache);
121 nvfx_context_init_vdec(nvfx);
122
123 return &nvfx->pipe;
124}
diff --git a/src/gallium/drivers/nvfx/nvfx_context.h b/src/gallium/drivers/nvfx/nvfx_context.h
deleted file mode 100644
index 019be6cf4c5..00000000000
--- a/src/gallium/drivers/nvfx/nvfx_context.h
+++ /dev/null
@@ -1,375 +0,0 @@
1#ifndef __NVFX_CONTEXT_H__
2#define __NVFX_CONTEXT_H__
3
4#include <stdio.h>
5
6#include "pipe/p_context.h"
7#include "pipe/p_defines.h"
8#include "pipe/p_state.h"
9#include "pipe/p_compiler.h"
10
11#include "util/u_memory.h"
12#include "util/u_math.h"
13#include "util/u_inlines.h"
14#include "util/u_double_list.h"
15
16#include "draw/draw_vertex.h"
17#include "util/u_blitter.h"
18
19#include "nouveau/nouveau_winsys.h"
20#include "nouveau/nouveau_gldefs.h"
21#include "nouveau/nouveau_resource.h"
22#include "nv30-40_3d.xml.h"
23#include "nvfx_state.h"
24
25#define NOUVEAU_ERR(fmt, args...) \
26 fprintf(stderr, "%s:%d - "fmt, __func__, __LINE__, ##args);
27#define NOUVEAU_MSG(fmt, args...) \
28 fprintf(stderr, "nouveau: "fmt, ##args);
29
30#include "nvfx_screen.h"
31
32#define NVFX_NEW_BLEND (1 << 0)
33#define NVFX_NEW_RAST (1 << 1)
34#define NVFX_NEW_ZSA (1 << 2)
35#define NVFX_NEW_SAMPLER (1 << 3)
36#define NVFX_NEW_FB (1 << 4)
37#define NVFX_NEW_STIPPLE (1 << 5)
38#define NVFX_NEW_SCISSOR (1 << 6)
39#define NVFX_NEW_VIEWPORT (1 << 7)
40#define NVFX_NEW_BCOL (1 << 8)
41#define NVFX_NEW_VERTPROG (1 << 9)
42#define NVFX_NEW_FRAGPROG (1 << 10)
43#define NVFX_NEW_ARRAYS (1 << 11)
44#define NVFX_NEW_UCP (1 << 12)
45#define NVFX_NEW_SR (1 << 13)
46#define NVFX_NEW_VERTCONST (1 << 14)
47#define NVFX_NEW_FRAGCONST (1 << 15)
48#define NVFX_NEW_INDEX (1 << 16)
49#define NVFX_NEW_SPRITE (1 << 17)
50
51#define NVFX_RELOCATE_FRAMEBUFFER (1 << 0)
52#define NVFX_RELOCATE_FRAGTEX (1 << 1)
53#define NVFX_RELOCATE_FRAGPROG (1 << 2)
54#define NVFX_RELOCATE_VTXBUF (1 << 3)
55#define NVFX_RELOCATE_IDXBUF (1 << 4)
56#define NVFX_RELOCATE_ALL 0x1f
57
58struct nvfx_rasterizer_state {
59 struct pipe_rasterizer_state pipe;
60 unsigned sb_len;
61 uint32_t sb[34];
62};
63
64struct nvfx_zsa_state {
65 struct pipe_depth_stencil_alpha_state pipe;
66 unsigned sb_len;
67 uint32_t sb[24];
68};
69
70struct nvfx_blend_state {
71 struct pipe_blend_state pipe;
72 unsigned sb_len;
73 uint32_t sb[13];
74};
75
76
77struct nvfx_state {
78 unsigned scissor_enabled;
79 unsigned fp_samplers;
80 unsigned render_temps;
81};
82
83struct nvfx_per_vertex_element {
84 unsigned idx;
85 unsigned vertex_buffer_index;
86 unsigned src_offset;
87};
88
89struct nvfx_low_frequency_element {
90 unsigned idx;
91 unsigned vertex_buffer_index;
92 unsigned src_offset;
93 void (*fetch_rgba_float)(float *dst, const uint8_t *src, unsigned i, unsigned j);
94 unsigned ncomp;
95};
96
97struct nvfx_per_instance_element {
98 struct nvfx_low_frequency_element base;
99 unsigned instance_divisor;
100};
101
102struct nvfx_per_vertex_buffer_info
103{
104 unsigned vertex_buffer_index;
105 unsigned per_vertex_size;
106};
107
108struct nvfx_vtxelt_state {
109 struct pipe_vertex_element pipe[16];
110 unsigned num_elements;
111 unsigned vtxfmt[16];
112
113 unsigned num_per_vertex_buffer_infos;
114 struct nvfx_per_vertex_buffer_info per_vertex_buffer_info[16];
115
116 unsigned num_per_vertex;
117 struct nvfx_per_vertex_element per_vertex[16];
118
119 unsigned num_per_instance;
120 struct nvfx_per_instance_element per_instance[16];
121
122 unsigned num_constant;
123 struct nvfx_low_frequency_element constant[16];
124
125 boolean needs_translate;
126 struct translate* translate;
127
128 unsigned vertex_length;
129 unsigned max_vertices_per_packet;
130};
131
132struct nvfx_render_target {
133 struct nouveau_bo* bo;
134 unsigned offset;
135 unsigned pitch;
136};
137
138struct nvfx_context {
139 struct pipe_context pipe;
140
141 struct nvfx_screen *screen;
142
143 unsigned is_nv4x; /* either 0 or ~0 */
144 unsigned use_nv4x; /* either 0 or ~0 */
145 boolean use_vp_clipping;
146
147 struct draw_context *draw;
148 /* one is for user-requested operations, the other is for temporary copying inside them */
149 struct blitter_context* blitter[2];
150 unsigned blitters_in_use;
151 struct list_head render_cache;
152
153 /* HW state derived from pipe states */
154 struct nvfx_state state;
155
156 enum {
157 HW, SWTNL, SWRAST
158 } render_mode;
159 unsigned fallback_swtnl;
160
161 /* Context state */
162 unsigned dirty, draw_dirty;
163 struct pipe_scissor_state scissor;
164 unsigned stipple[32];
165 struct pipe_clip_state clip;
166 struct nvfx_pipe_vertex_program *vertprog;
167 struct nvfx_pipe_fragment_program *fragprog;
168 struct pipe_resource *constbuf[PIPE_SHADER_TYPES];
169 unsigned constbuf_nr[PIPE_SHADER_TYPES];
170 struct nvfx_rasterizer_state *rasterizer;
171 struct nvfx_zsa_state *zsa;
172 struct nvfx_blend_state *blend;
173 struct pipe_blend_color blend_colour;
174 struct pipe_stencil_ref stencil_ref;
175 struct pipe_viewport_state viewport;
176 struct pipe_framebuffer_state framebuffer;
177 struct pipe_index_buffer idxbuf;
178 struct nvfx_sampler_state *tex_sampler[PIPE_MAX_SAMPLERS];
179 struct pipe_sampler_view *fragment_sampler_views[PIPE_MAX_SAMPLERS];
180 struct nvfx_pipe_fragment_program* dummy_fs;
181 struct pipe_query* query;
182
183 unsigned nr_samplers;
184 unsigned nr_textures;
185 unsigned dirty_samplers;
186 struct pipe_vertex_buffer vtxbuf[PIPE_MAX_ATTRIBS];
187 unsigned vtxbuf_nr;
188 struct nvfx_vtxelt_state *vtxelt;
189 int base_vertex;
190 boolean use_index_buffer;
191 /* -1 = hardware input setup is outdated
192 * 0 = hardware input setup is for inline vertices
193 * 1 = hardware input setup is for hardware vertices
194 */
195 int use_vertex_buffers;
196
197 unsigned hw_vtxelt_nr;
198 unsigned hw_samplers;
199 uint32_t hw_txf[16];
200 struct nvfx_render_target hw_rt[4];
201 struct nvfx_render_target hw_zeta;
202 int hw_pointsprite_control;
203 int hw_vp_output;
204 struct nvfx_fragment_program* hw_fragprog;
205 struct nvfx_vertex_program* hw_vertprog;
206
207 unsigned relocs_needed;
208};
209
210static INLINE struct nvfx_context *
211nvfx_context(struct pipe_context *pipe)
212{
213 return (struct nvfx_context *)pipe;
214}
215
216extern struct nvfx_state_entry nvfx_state_blend;
217extern struct nvfx_state_entry nvfx_state_blend_colour;
218extern struct nvfx_state_entry nvfx_state_fragprog;
219extern struct nvfx_state_entry nvfx_state_fragtex;
220extern struct nvfx_state_entry nvfx_state_framebuffer;
221extern struct nvfx_state_entry nvfx_state_rasterizer;
222extern struct nvfx_state_entry nvfx_state_scissor;
223extern struct nvfx_state_entry nvfx_state_sr;
224extern struct nvfx_state_entry nvfx_state_stipple;
225extern struct nvfx_state_entry nvfx_state_vbo;
226extern struct nvfx_state_entry nvfx_state_vertprog;
227extern struct nvfx_state_entry nvfx_state_viewport;
228extern struct nvfx_state_entry nvfx_state_vtxfmt;
229extern struct nvfx_state_entry nvfx_state_zsa;
230
231extern void nvfx_init_query_functions(struct nvfx_context *nvfx);
232extern void nvfx_init_surface_functions(struct nvfx_context *nvfx);
233
234/* nvfx_context.c */
235struct pipe_context *
236nvfx_create(struct pipe_screen *pscreen, void *priv);
237
238/* nvfx_clear.c */
239extern void nvfx_clear(struct pipe_context *pipe, unsigned buffers,
240 const union pipe_color_union *color,
241 double depth, unsigned stencil);
242
243/* nvfx_draw.c */
244extern struct draw_stage *nvfx_draw_render_stage(struct nvfx_context *nvfx);
245extern void nvfx_draw_vbo_swtnl(struct pipe_context *pipe, const struct pipe_draw_info* info);
246extern void nvfx_vtxfmt_validate(struct nvfx_context *nvfx);
247
248/* nvfx_fb.c */
249extern int nvfx_framebuffer_prepare(struct nvfx_context *nvfx);
250extern void nvfx_framebuffer_validate(struct nvfx_context *nvfx);
251void
252nvfx_framebuffer_relocate(struct nvfx_context *nvfx);
253
254/* nvfx_fragprog.c */
255extern void nvfx_fragprog_destroy(struct nvfx_context *,
256 struct nvfx_fragment_program *);
257extern void nvfx_fragprog_validate(struct nvfx_context *nvfx);
258extern void nvfx_fragprog_relocate(struct nvfx_context *nvfx);
259extern void nvfx_init_fragprog_functions(struct nvfx_context *nvfx);
260
261/* nvfx_fragtex.c */
262extern void nvfx_init_sampling_functions(struct nvfx_context *nvfx);
263extern void nvfx_fragtex_validate(struct nvfx_context *nvfx);
264extern void nvfx_fragtex_relocate(struct nvfx_context *nvfx);
265
266struct nvfx_sampler_view;
267
268/* nv30_fragtex.c */
269extern void
270nv30_sampler_state_init(struct pipe_context *pipe,
271 struct nvfx_sampler_state *ps,
272 const struct pipe_sampler_state *cso);
273extern void
274nv30_sampler_view_init(struct pipe_context *pipe,
275 struct nvfx_sampler_view *sv);
276extern void nv30_fragtex_set(struct nvfx_context *nvfx, int unit);
277
278/* nv40_fragtex.c */
279extern void
280nv40_sampler_state_init(struct pipe_context *pipe,
281 struct nvfx_sampler_state *ps,
282 const struct pipe_sampler_state *cso);
283extern void
284nv40_sampler_view_init(struct pipe_context *pipe,
285 struct nvfx_sampler_view *sv);
286extern void nv40_fragtex_set(struct nvfx_context *nvfx, int unit);
287
288/* nvfx_state.c */
289extern void nvfx_init_state_functions(struct nvfx_context *nvfx);
290extern void nvfx_state_scissor_validate(struct nvfx_context *nvfx);
291extern void nvfx_state_stipple_validate(struct nvfx_context *nvfx);
292extern void nvfx_state_blend_validate(struct nvfx_context *nvfx);
293extern void nvfx_state_blend_colour_validate(struct nvfx_context *nvfx);
294extern void nvfx_state_viewport_validate(struct nvfx_context *nvfx);
295extern void nvfx_state_rasterizer_validate(struct nvfx_context *nvfx);
296extern void nvfx_state_sr_validate(struct nvfx_context *nvfx);
297extern void nvfx_state_zsa_validate(struct nvfx_context *nvfx);
298
299/* nvfx_state_emit.c */
300extern void nvfx_state_relocate(struct nvfx_context *nvfx, unsigned relocs);
301extern boolean nvfx_state_validate(struct nvfx_context *nvfx);
302extern boolean nvfx_state_validate_swtnl(struct nvfx_context *nvfx);
303
304static inline void
305nvfx_state_emit(struct nvfx_context *nvfx)
306{
307 unsigned relocs = NVFX_RELOCATE_FRAMEBUFFER | NVFX_RELOCATE_FRAGTEX | NVFX_RELOCATE_FRAGPROG;
308 if (nvfx->render_mode == HW)
309 {
310 relocs |= NVFX_RELOCATE_VTXBUF;
311 if(nvfx->use_index_buffer)
312 relocs |= NVFX_RELOCATE_IDXBUF;
313 }
314
315 relocs &= nvfx->relocs_needed;
316 if(relocs)
317 nvfx_state_relocate(nvfx, relocs);
318}
319
320/* nvfx_transfer.c */
321extern void nvfx_init_transfer_functions(struct pipe_context *pipe);
322
323/* nvfx_vbo.c */
324extern boolean nvfx_vbo_validate(struct nvfx_context *nvfx);
325extern void nvfx_vbo_swtnl_validate(struct nvfx_context *nvfx);
326extern void nvfx_vbo_relocate(struct nvfx_context *nvfx);
327extern void nvfx_idxbuf_validate(struct nvfx_context* nvfx);
328extern void nvfx_idxbuf_relocate(struct nvfx_context* nvfx);
329extern void nvfx_draw_vbo(struct pipe_context *pipe,
330 const struct pipe_draw_info *info);
331extern void nvfx_init_vbo_functions(struct nvfx_context *nvfx);
332extern unsigned nvfx_vertex_formats[];
333
334/* nvfx_vertprog.c */
335extern boolean nvfx_vertprog_validate(struct nvfx_context *nvfx);
336extern void nvfx_vertprog_destroy(struct nvfx_context *,
337 struct nvfx_vertex_program *);
338extern void nvfx_init_vertprog_functions(struct nvfx_context *nvfx);
339
340/* nvfx_push.c */
341extern void nvfx_push_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info);
342
343extern void nvfx_context_init_vdec(struct nvfx_context *);
344
345static inline void nvfx_emit_vtx_attr(struct nouveau_channel* chan,
346 struct nouveau_grobj *eng3d, unsigned attrib, const float* v,
347 unsigned ncomp)
348{
349 switch (ncomp) {
350 case 4:
351 BEGIN_RING(chan, eng3d, NV30_3D_VTX_ATTR_4F_X(attrib), 4);
352 OUT_RING(chan, fui(v[0]));
353 OUT_RING(chan, fui(v[1]));
354 OUT_RING(chan, fui(v[2]));
355 OUT_RING(chan, fui(v[3]));
356 break;
357 case 3:
358 BEGIN_RING(chan, eng3d, NV30_3D_VTX_ATTR_3F_X(attrib), 3);
359 OUT_RING(chan, fui(v[0]));
360 OUT_RING(chan, fui(v[1]));
361 OUT_RING(chan, fui(v[2]));
362 break;
363 case 2:
364 BEGIN_RING(chan, eng3d, NV30_3D_VTX_ATTR_2F_X(attrib), 2);
365 OUT_RING(chan, fui(v[0]));
366 OUT_RING(chan, fui(v[1]));
367 break;
368 case 1:
369 BEGIN_RING(chan, eng3d, NV30_3D_VTX_ATTR_1F(attrib), 1);
370 OUT_RING(chan, fui(v[0]));
371 break;
372 }
373}
374
375#endif
diff --git a/src/gallium/drivers/nvfx/nvfx_draw.c b/src/gallium/drivers/nvfx/nvfx_draw.c
deleted file mode 100644
index 81f1ec485d3..00000000000
--- a/src/gallium/drivers/nvfx/nvfx_draw.c
+++ /dev/null
@@ -1,191 +0,0 @@
1#include "pipe/p_shader_tokens.h"
2#include "util/u_inlines.h"
3
4#include "util/u_pack_color.h"
5
6#include "draw/draw_context.h"
7#include "draw/draw_vertex.h"
8#include "draw/draw_pipe.h"
9
10#include "nvfx_context.h"
11#include "nvfx_resource.h"
12
13struct nvfx_render_stage {
14 struct draw_stage stage;
15 struct nvfx_context *nvfx;
16 unsigned prim;
17};
18
19static INLINE struct nvfx_render_stage *
20nvfx_render_stage(struct draw_stage *stage)
21{
22 return (struct nvfx_render_stage *)stage;
23}
24
25static void
26nvfx_render_flush(struct draw_stage *stage, unsigned flags)
27{
28 struct nvfx_render_stage *rs = nvfx_render_stage(stage);
29 struct nvfx_context *nvfx = rs->nvfx;
30 struct nouveau_channel *chan = nvfx->screen->base.channel;
31 struct nouveau_grobj *eng3d = nvfx->screen->eng3d;
32
33 if (rs->prim != NV30_3D_VERTEX_BEGIN_END_STOP) {
34 BEGIN_RING(chan, eng3d, NV30_3D_VERTEX_BEGIN_END, 1);
35 OUT_RING(chan, NV30_3D_VERTEX_BEGIN_END_STOP);
36 rs->prim = NV30_3D_VERTEX_BEGIN_END_STOP;
37 }
38}
39
40static INLINE void
41nvfx_render_prim(struct draw_stage *stage, struct prim_header *prim,
42 unsigned mode, unsigned count)
43{
44 struct nvfx_render_stage *rs = nvfx_render_stage(stage);
45 struct nvfx_context *nvfx = rs->nvfx;
46
47 struct nvfx_screen *screen = nvfx->screen;
48 struct nouveau_channel *chan = screen->base.channel;
49 struct nouveau_grobj *eng3d = screen->eng3d;
50 boolean no_elements = nvfx->vertprog->draw_no_elements;
51 unsigned num_attribs = nvfx->vertprog->draw_elements;
52
53 /* we need to account the flush as well here even if it is done afterthis
54 * function
55 */
56 if (AVAIL_RING(chan) < ((1 + count * num_attribs * 4) + 6 + 64)) {
57 nvfx_render_flush(stage, 0);
58 FIRE_RING(chan);
59 nvfx_state_emit(nvfx);
60
61 assert(AVAIL_RING(chan) >= ((1 + count * num_attribs * 4) + 6 + 64));
62 }
63
64 /* Switch primitive modes if necessary */
65 if (rs->prim != mode) {
66 if (rs->prim != NV30_3D_VERTEX_BEGIN_END_STOP) {
67 BEGIN_RING(chan, eng3d, NV30_3D_VERTEX_BEGIN_END, 1);
68 OUT_RING(chan, NV30_3D_VERTEX_BEGIN_END_STOP);
69 }
70
71 /* XXX: any command a lot of times seems to (mostly) fix corruption that would otherwise happen */
72 /* this seems to cause issues on nv3x, and also be unneeded there */
73 if(nvfx->is_nv4x)
74 {
75 int i;
76 for(i = 0; i < 32; ++i)
77 {
78 BEGIN_RING(chan, eng3d, 0x1dac, 1);
79 OUT_RING(chan, 0);
80 }
81 }
82
83 BEGIN_RING(chan, eng3d, NV30_3D_VERTEX_BEGIN_END, 1);
84 OUT_RING (chan, mode);
85 rs->prim = mode;
86 }
87
88 if(no_elements) {
89 BEGIN_RING_NI(chan, eng3d, NV30_3D_VERTEX_DATA, 4);
90 OUT_RING(chan, 0);
91 OUT_RING(chan, 0);
92 OUT_RING(chan, 0);
93 OUT_RING(chan, 0);
94 } else {
95 BEGIN_RING_NI(chan, eng3d, NV30_3D_VERTEX_DATA, num_attribs * 4 * count);
96 for (unsigned i = 0; i < count; ++i)
97 {
98 struct vertex_header* v = prim->v[i];
99 /* TODO: disable divide where it's causing the problem, and remove this hack */
100 OUT_RING(chan, fui(v->data[0][0] / v->data[0][3]));
101 OUT_RING(chan, fui(v->data[0][1] / v->data[0][3]));
102 OUT_RING(chan, fui(v->data[0][2] / v->data[0][3]));
103 OUT_RING(chan, fui(1.0f / v->data[0][3]));
104 OUT_RINGp(chan, &v->data[1][0], 4 * (num_attribs - 1));
105 }
106 }
107}
108
109static void
110nvfx_render_point(struct draw_stage *draw, struct prim_header *prim)
111{
112 nvfx_render_prim(draw, prim, NV30_3D_VERTEX_BEGIN_END_POINTS, 1);
113}
114
115static void
116nvfx_render_line(struct draw_stage *draw, struct prim_header *prim)
117{
118 nvfx_render_prim(draw, prim, NV30_3D_VERTEX_BEGIN_END_LINES, 2);
119}
120
121static void
122nvfx_render_tri(struct draw_stage *draw, struct prim_header *prim)
123{
124 nvfx_render_prim(draw, prim, NV30_3D_VERTEX_BEGIN_END_TRIANGLES, 3);
125}
126
127static void
128nvfx_render_reset_stipple_counter(struct draw_stage *draw)
129{
130 /* this doesn't really seem to work, but it matters rather little */
131 nvfx_render_flush(draw, 0);
132}
133
134static void
135nvfx_render_destroy(struct draw_stage *draw)
136{
137 FREE(draw);
138}
139
140struct draw_stage *
141nvfx_draw_render_stage(struct nvfx_context *nvfx)
142{
143 struct nvfx_render_stage *render = CALLOC_STRUCT(nvfx_render_stage);
144
145 render->nvfx = nvfx;
146 render->stage.draw = nvfx->draw;
147 render->stage.point = nvfx_render_point;
148 render->stage.line = nvfx_render_line;
149 render->stage.tri = nvfx_render_tri;
150 render->stage.flush = nvfx_render_flush;
151 render->stage.reset_stipple_counter = nvfx_render_reset_stipple_counter;
152 render->stage.destroy = nvfx_render_destroy;
153
154 return &render->stage;
155}
156
157void
158nvfx_draw_vbo_swtnl(struct pipe_context *pipe, const struct pipe_draw_info* info)
159{
160 struct nvfx_context *nvfx = nvfx_context(pipe);
161 unsigned i;
162 void *map;
163
164 if (!nvfx_state_validate_swtnl(nvfx))
165 return;
166
167 nvfx_state_emit(nvfx);
168
169 /* these must be passed without adding the offsets */
170 for (i = 0; i < nvfx->vtxbuf_nr; i++) {
171 map = nvfx_buffer(nvfx->vtxbuf[i].buffer)->data;
172 draw_set_mapped_vertex_buffer(nvfx->draw, i, map);
173 }
174
175 map = NULL;
176 if (info->indexed && nvfx->idxbuf.buffer)
177 map = nvfx_buffer(nvfx->idxbuf.buffer)->data;
178 draw_set_mapped_index_buffer(nvfx->draw, map);
179
180 if (nvfx->constbuf[PIPE_SHADER_VERTEX]) {
181 const unsigned nr = nvfx->constbuf_nr[PIPE_SHADER_VERTEX];
182
183 map = nvfx_buffer(nvfx->constbuf[PIPE_SHADER_VERTEX])->data;
184 draw_set_mapped_constant_buffer(nvfx->draw, PIPE_SHADER_VERTEX, 0,
185 map, nr);
186 }
187
188 draw_vbo(nvfx->draw, info);
189
190 draw_flush(nvfx->draw);
191}
diff --git a/src/gallium/drivers/nvfx/nvfx_fragprog.c b/src/gallium/drivers/nvfx/nvfx_fragprog.c
deleted file mode 100644
index 0babcbb9978..00000000000
--- a/src/gallium/drivers/nvfx/nvfx_fragprog.c
+++ /dev/null
@@ -1,1624 +0,0 @@
1#include <float.h>
2#include "pipe/p_context.h"
3#include "pipe/p_defines.h"
4#include "pipe/p_state.h"
5#include "util/u_inlines.h"
6#include "util/u_debug.h"
7
8#include "pipe/p_shader_tokens.h"
9#include "tgsi/tgsi_parse.h"
10#include "tgsi/tgsi_util.h"
11#include "tgsi/tgsi_dump.h"
12#include "tgsi/tgsi_ureg.h"
13
14#include "nvfx_context.h"
15#include "nvfx_shader.h"
16#include "nvfx_resource.h"
17
18struct nvfx_fpc {
19 struct nvfx_pipe_fragment_program* pfp;
20 struct nvfx_fragment_program *fp;
21
22 unsigned max_temps;
23 unsigned long long r_temps;
24 unsigned long long r_temps_discard;
25 struct nvfx_reg r_result[PIPE_MAX_SHADER_OUTPUTS];
26 struct nvfx_reg *r_temp;
27 unsigned sprite_coord_temp;
28
29 int num_regs;
30
31 unsigned inst_offset;
32 unsigned have_const;
33
34 struct util_dynarray imm_data;
35
36 struct nvfx_reg* r_imm;
37 unsigned nr_imm;
38
39 unsigned char generic_to_slot[256]; /* semantic idx for each input semantic */
40
41 struct util_dynarray if_stack;
42 //struct util_dynarray loop_stack;
43 struct util_dynarray label_relocs;
44};
45
46static INLINE struct nvfx_reg
47temp(struct nvfx_fpc *fpc)
48{
49 int idx = __builtin_ctzll(~fpc->r_temps);
50
51 if (idx >= fpc->max_temps) {
52 NOUVEAU_ERR("out of temps!!\n");
53 assert(0);
54 return nvfx_reg(NVFXSR_TEMP, 0);
55 }
56
57 fpc->r_temps |= (1ULL << idx);
58 fpc->r_temps_discard |= (1ULL << idx);
59 return nvfx_reg(NVFXSR_TEMP, idx);
60}
61
62static INLINE void
63release_temps(struct nvfx_fpc *fpc)
64{
65 fpc->r_temps &= ~fpc->r_temps_discard;
66 fpc->r_temps_discard = 0ULL;
67}
68
69static inline struct nvfx_reg
70nvfx_fp_imm(struct nvfx_fpc *fpc, float a, float b, float c, float d)
71{
72 float v[4] = {a, b, c, d};
73 int idx = fpc->imm_data.size >> 4;
74
75 memcpy(util_dynarray_grow(&fpc->imm_data, sizeof(float) * 4), v, 4 * sizeof(float));
76 return nvfx_reg(NVFXSR_IMM, idx);
77}
78
79static void
80grow_insns(struct nvfx_fpc *fpc, int size)
81{
82 struct nvfx_fragment_program *fp = fpc->fp;
83
84 fp->insn_len += size;
85 fp->insn = realloc(fp->insn, sizeof(uint32_t) * fp->insn_len);
86}
87
88static void
89emit_src(struct nvfx_fpc *fpc, int pos, struct nvfx_src src)
90{
91 struct nvfx_fragment_program *fp = fpc->fp;
92 uint32_t *hw = &fp->insn[fpc->inst_offset];
93 uint32_t sr = 0;
94
95 switch (src.reg.type) {
96 case NVFXSR_INPUT:
97 sr |= (NVFX_FP_REG_TYPE_INPUT << NVFX_FP_REG_TYPE_SHIFT);
98 hw[0] |= (src.reg.index << NVFX_FP_OP_INPUT_SRC_SHIFT);
99 break;
100 case NVFXSR_OUTPUT:
101 sr |= NVFX_FP_REG_SRC_HALF;
102 /* fall-through */
103 case NVFXSR_TEMP:
104 sr |= (NVFX_FP_REG_TYPE_TEMP << NVFX_FP_REG_TYPE_SHIFT);
105 sr |= (src.reg.index << NVFX_FP_REG_SRC_SHIFT);
106 break;
107 case NVFXSR_RELOCATED:
108 sr |= (NVFX_FP_REG_TYPE_TEMP << NVFX_FP_REG_TYPE_SHIFT);
109 sr |= (fpc->sprite_coord_temp << NVFX_FP_REG_SRC_SHIFT);
110 //printf("adding relocation at %x for %x\n", fpc->inst_offset, src.index);
111 util_dynarray_append(&fpc->fp->slot_relocations[src.reg.index], unsigned, fpc->inst_offset + pos + 1);
112 break;
113 case NVFXSR_IMM:
114 if (!fpc->have_const) {
115 grow_insns(fpc, 4);
116 hw = &fp->insn[fpc->inst_offset];
117 fpc->have_const = 1;
118 }
119
120 memcpy(&fp->insn[fpc->inst_offset + 4],
121 (float*)fpc->imm_data.data + src.reg.index * 4,
122 sizeof(uint32_t) * 4);
123
124 sr |= (NVFX_FP_REG_TYPE_CONST << NVFX_FP_REG_TYPE_SHIFT);
125 break;
126 case NVFXSR_CONST:
127 if (!fpc->have_const) {
128 grow_insns(fpc, 4);
129 hw = &fp->insn[fpc->inst_offset];
130 fpc->have_const = 1;
131 }
132
133 {
134 struct nvfx_fragment_program_data *fpd;
135
136 fp->consts = realloc(fp->consts, ++fp->nr_consts *
137 sizeof(*fpd));
138 fpd = &fp->consts[fp->nr_consts - 1];
139 fpd->offset = fpc->inst_offset + 4;
140 fpd->index = src.reg.index;
141 memset(&fp->insn[fpd->offset], 0, sizeof(uint32_t) * 4);
142 }
143
144 sr |= (NVFX_FP_REG_TYPE_CONST << NVFX_FP_REG_TYPE_SHIFT);
145 break;
146 case NVFXSR_NONE:
147 sr |= (NVFX_FP_REG_TYPE_INPUT << NVFX_FP_REG_TYPE_SHIFT);
148 break;
149 default:
150 assert(0);
151 }
152
153 if (src.negate)
154 sr |= NVFX_FP_REG_NEGATE;
155
156 if (src.abs)
157 hw[1] |= (1 << (29 + pos));
158
159 sr |= ((src.swz[0] << NVFX_FP_REG_SWZ_X_SHIFT) |
160 (src.swz[1] << NVFX_FP_REG_SWZ_Y_SHIFT) |
161 (src.swz[2] << NVFX_FP_REG_SWZ_Z_SHIFT) |
162 (src.swz[3] << NVFX_FP_REG_SWZ_W_SHIFT));
163
164 hw[pos + 1] |= sr;
165}
166
167static void
168emit_dst(struct nvfx_fpc *fpc, struct nvfx_reg dst)
169{
170 struct nvfx_fragment_program *fp = fpc->fp;
171 uint32_t *hw = &fp->insn[fpc->inst_offset];
172
173 switch (dst.type) {
174 case NVFXSR_TEMP:
175 if (fpc->num_regs < (dst.index + 1))
176 fpc->num_regs = dst.index + 1;
177 break;
178 case NVFXSR_OUTPUT:
179 if (dst.index == 1) {
180 fp->fp_control |= 0xe;
181 } else {
182 hw[0] |= NVFX_FP_OP_OUT_REG_HALF;
183 }
184 break;
185 case NVFXSR_NONE:
186 hw[0] |= (1 << 30);
187 break;
188 default:
189 assert(0);
190 }
191
192 hw[0] |= (dst.index << NVFX_FP_OP_OUT_REG_SHIFT);
193}
194
195static void
196nvfx_fp_emit(struct nvfx_fpc *fpc, struct nvfx_insn insn)
197{
198 struct nvfx_fragment_program *fp = fpc->fp;
199 uint32_t *hw;
200
201 fpc->inst_offset = fp->insn_len;
202 fpc->have_const = 0;
203 grow_insns(fpc, 4);
204 hw = &fp->insn[fpc->inst_offset];
205 memset(hw, 0, sizeof(uint32_t) * 4);
206
207 if (insn.op == NVFX_FP_OP_OPCODE_KIL)
208 fp->fp_control |= NV30_3D_FP_CONTROL_USES_KIL;
209 hw[0] |= (insn.op << NVFX_FP_OP_OPCODE_SHIFT);
210 hw[0] |= (insn.mask << NVFX_FP_OP_OUTMASK_SHIFT);
211 hw[2] |= (insn.scale << NVFX_FP_OP_DST_SCALE_SHIFT);
212
213 if (insn.sat)
214 hw[0] |= NVFX_FP_OP_OUT_SAT;
215
216 if (insn.cc_update)
217 hw[0] |= NVFX_FP_OP_COND_WRITE_ENABLE;
218 hw[1] |= (insn.cc_test << NVFX_FP_OP_COND_SHIFT);
219 hw[1] |= ((insn.cc_swz[0] << NVFX_FP_OP_COND_SWZ_X_SHIFT) |
220 (insn.cc_swz[1] << NVFX_FP_OP_COND_SWZ_Y_SHIFT) |
221 (insn.cc_swz[2] << NVFX_FP_OP_COND_SWZ_Z_SHIFT) |
222 (insn.cc_swz[3] << NVFX_FP_OP_COND_SWZ_W_SHIFT));
223
224 if(insn.unit >= 0)
225 {
226 hw[0] |= (insn.unit << NVFX_FP_OP_TEX_UNIT_SHIFT);
227 fp->samplers |= (1 << insn.unit);
228 }
229
230 emit_dst(fpc, insn.dst);
231 emit_src(fpc, 0, insn.src[0]);
232 emit_src(fpc, 1, insn.src[1]);
233 emit_src(fpc, 2, insn.src[2]);
234}
235
236#define arith(s,o,d,m,s0,s1,s2) \
237 nvfx_insn((s), NVFX_FP_OP_OPCODE_##o, -1, \
238 (d), (m), (s0), (s1), (s2))
239
240#define tex(s,o,u,d,m,s0,s1,s2) \
241 nvfx_insn((s), NVFX_FP_OP_OPCODE_##o, (u), \
242 (d), (m), (s0), none, none)
243
244/* IF src.x != 0, as TGSI specifies */
245static void
246nv40_fp_if(struct nvfx_fpc *fpc, struct nvfx_src src)
247{
248 const struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0));
249 struct nvfx_insn insn = arith(0, MOV, none.reg, NVFX_FP_MASK_X, src, none, none);
250 uint32_t *hw;
251 insn.cc_update = 1;
252 nvfx_fp_emit(fpc, insn);
253
254 fpc->inst_offset = fpc->fp->insn_len;
255 grow_insns(fpc, 4);
256 hw = &fpc->fp->insn[fpc->inst_offset];
257 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
258 hw[0] = (NV40_FP_OP_BRA_OPCODE_IF << NVFX_FP_OP_OPCODE_SHIFT) |
259 NV40_FP_OP_OUT_NONE |
260 (NVFX_FP_PRECISION_FP16 << NVFX_FP_OP_PRECISION_SHIFT);
261 /* Use .xxxx swizzle so that we check only src[0].x*/
262 hw[1] = (0 << NVFX_FP_OP_COND_SWZ_X_SHIFT) |
263 (0 << NVFX_FP_OP_COND_SWZ_Y_SHIFT) |
264 (0 << NVFX_FP_OP_COND_SWZ_Z_SHIFT) |
265 (0 << NVFX_FP_OP_COND_SWZ_W_SHIFT) |
266 (NVFX_FP_OP_COND_NE << NVFX_FP_OP_COND_SHIFT);
267 hw[2] = 0; /* | NV40_FP_OP_OPCODE_IS_BRANCH | else_offset */
268 hw[3] = 0; /* | endif_offset */
269 util_dynarray_append(&fpc->if_stack, unsigned, fpc->inst_offset);
270}
271
272/* IF src.x != 0, as TGSI specifies */
273static void
274nv40_fp_cal(struct nvfx_fpc *fpc, unsigned target)
275{
276 struct nvfx_relocation reloc;
277 uint32_t *hw;
278 fpc->inst_offset = fpc->fp->insn_len;
279 grow_insns(fpc, 4);
280 hw = &fpc->fp->insn[fpc->inst_offset];
281 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
282 hw[0] = (NV40_FP_OP_BRA_OPCODE_CAL << NVFX_FP_OP_OPCODE_SHIFT);
283 /* Use .xxxx swizzle so that we check only src[0].x*/
284 hw[1] = (NVFX_SWZ_IDENTITY << NVFX_FP_OP_COND_SWZ_ALL_SHIFT) |
285 (NVFX_FP_OP_COND_TR << NVFX_FP_OP_COND_SHIFT);
286 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH; /* | call_offset */
287 hw[3] = 0;
288 reloc.target = target;
289 reloc.location = fpc->inst_offset + 2;
290 util_dynarray_append(&fpc->label_relocs, struct nvfx_relocation, reloc);
291}
292
293static void
294nv40_fp_ret(struct nvfx_fpc *fpc)
295{
296 uint32_t *hw;
297 fpc->inst_offset = fpc->fp->insn_len;
298 grow_insns(fpc, 4);
299 hw = &fpc->fp->insn[fpc->inst_offset];
300 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
301 hw[0] = (NV40_FP_OP_BRA_OPCODE_RET << NVFX_FP_OP_OPCODE_SHIFT);
302 /* Use .xxxx swizzle so that we check only src[0].x*/
303 hw[1] = (NVFX_SWZ_IDENTITY << NVFX_FP_OP_COND_SWZ_ALL_SHIFT) |
304 (NVFX_FP_OP_COND_TR << NVFX_FP_OP_COND_SHIFT);
305 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH; /* | call_offset */
306 hw[3] = 0;
307}
308
309static void
310nv40_fp_rep(struct nvfx_fpc *fpc, unsigned count, unsigned target)
311{
312 struct nvfx_relocation reloc;
313 uint32_t *hw;
314 fpc->inst_offset = fpc->fp->insn_len;
315 grow_insns(fpc, 4);
316 hw = &fpc->fp->insn[fpc->inst_offset];
317 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
318 hw[0] = (NV40_FP_OP_BRA_OPCODE_REP << NVFX_FP_OP_OPCODE_SHIFT) |
319 NV40_FP_OP_OUT_NONE |
320 (NVFX_FP_PRECISION_FP16 << NVFX_FP_OP_PRECISION_SHIFT);
321 /* Use .xxxx swizzle so that we check only src[0].x*/
322 hw[1] = (NVFX_SWZ_IDENTITY << NVFX_FP_OP_COND_SWZ_ALL_SHIFT) |
323 (NVFX_FP_OP_COND_TR << NVFX_FP_OP_COND_SHIFT);
324 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH |
325 (count << NV40_FP_OP_REP_COUNT1_SHIFT) |
326 (count << NV40_FP_OP_REP_COUNT2_SHIFT) |
327 (count << NV40_FP_OP_REP_COUNT3_SHIFT);
328 hw[3] = 0; /* | end_offset */
329 reloc.target = target;
330 reloc.location = fpc->inst_offset + 3;
331 util_dynarray_append(&fpc->label_relocs, struct nvfx_relocation, reloc);
332 //util_dynarray_append(&fpc->loop_stack, unsigned, target);
333}
334
335/* warning: this only works forward, and probably only if not inside any IF */
336static void
337nv40_fp_bra(struct nvfx_fpc *fpc, unsigned target)
338{
339 struct nvfx_relocation reloc;
340 uint32_t *hw;
341 fpc->inst_offset = fpc->fp->insn_len;
342 grow_insns(fpc, 4);
343 hw = &fpc->fp->insn[fpc->inst_offset];
344 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
345 hw[0] = (NV40_FP_OP_BRA_OPCODE_IF << NVFX_FP_OP_OPCODE_SHIFT) |
346 NV40_FP_OP_OUT_NONE |
347 (NVFX_FP_PRECISION_FP16 << NVFX_FP_OP_PRECISION_SHIFT);
348 /* Use .xxxx swizzle so that we check only src[0].x*/
349 hw[1] = (NVFX_SWZ_IDENTITY << NVFX_FP_OP_COND_SWZ_X_SHIFT) |
350 (NVFX_FP_OP_COND_FL << NVFX_FP_OP_COND_SHIFT);
351 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH; /* | else_offset */
352 hw[3] = 0; /* | endif_offset */
353 reloc.target = target;
354 reloc.location = fpc->inst_offset + 2;
355 util_dynarray_append(&fpc->label_relocs, struct nvfx_relocation, reloc);
356 reloc.target = target;
357 reloc.location = fpc->inst_offset + 3;
358 util_dynarray_append(&fpc->label_relocs, struct nvfx_relocation, reloc);
359}
360
361static void
362nv40_fp_brk(struct nvfx_fpc *fpc)
363{
364 uint32_t *hw;
365 fpc->inst_offset = fpc->fp->insn_len;
366 grow_insns(fpc, 4);
367 hw = &fpc->fp->insn[fpc->inst_offset];
368 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
369 hw[0] = (NV40_FP_OP_BRA_OPCODE_BRK << NVFX_FP_OP_OPCODE_SHIFT) |
370 NV40_FP_OP_OUT_NONE;
371 /* Use .xxxx swizzle so that we check only src[0].x*/
372 hw[1] = (NVFX_SWZ_IDENTITY << NVFX_FP_OP_COND_SWZ_X_SHIFT) |
373 (NVFX_FP_OP_COND_TR << NVFX_FP_OP_COND_SHIFT);
374 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH;
375 hw[3] = 0;
376}
377
378static INLINE struct nvfx_src
379tgsi_src(struct nvfx_fpc *fpc, const struct tgsi_full_src_register *fsrc)
380{
381 struct nvfx_src src;
382
383 switch (fsrc->Register.File) {
384 case TGSI_FILE_INPUT:
385 if(fpc->pfp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_POSITION) {
386 assert(fpc->pfp->info.input_semantic_index[fsrc->Register.Index] == 0);
387 src.reg = nvfx_reg(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_POSITION);
388 } else if(fpc->pfp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_COLOR) {
389 if(fpc->pfp->info.input_semantic_index[fsrc->Register.Index] == 0)
390 src.reg = nvfx_reg(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_COL0);
391 else if(fpc->pfp->info.input_semantic_index[fsrc->Register.Index] == 1)
392 src.reg = nvfx_reg(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_COL1);
393 else
394 assert(0);
395 } else if(fpc->pfp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_FOG) {
396 assert(fpc->pfp->info.input_semantic_index[fsrc->Register.Index] == 0);
397 src.reg = nvfx_reg(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_FOGC);
398 } else if(fpc->pfp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_FACE) {
399 /* TODO: check this has the correct values */
400 /* XXX: what do we do for nv30 here (assuming it lacks facing)?! */
401 assert(fpc->pfp->info.input_semantic_index[fsrc->Register.Index] == 0);
402 src.reg = nvfx_reg(NVFXSR_INPUT, NV40_FP_OP_INPUT_SRC_FACING);
403 } else {
404 assert(fpc->pfp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_GENERIC);
405 src.reg = nvfx_reg(NVFXSR_RELOCATED, fpc->generic_to_slot[fpc->pfp->info.input_semantic_index[fsrc->Register.Index]]);
406 }
407 break;
408 case TGSI_FILE_CONSTANT:
409 src.reg = nvfx_reg(NVFXSR_CONST, fsrc->Register.Index);
410 break;
411 case TGSI_FILE_IMMEDIATE:
412 assert(fsrc->Register.Index < fpc->nr_imm);
413 src.reg = fpc->r_imm[fsrc->Register.Index];
414 break;
415 case TGSI_FILE_TEMPORARY:
416 src.reg = fpc->r_temp[fsrc->Register.Index];
417 break;
418 /* NV40 fragprog result regs are just temps, so this is simple */
419 case TGSI_FILE_OUTPUT:
420 src.reg = fpc->r_result[fsrc->Register.Index];
421 break;
422 default:
423 NOUVEAU_ERR("bad src file\n");
424 src.reg.index = 0;
425 src.reg.type = 0;
426 break;
427 }
428
429 src.abs = fsrc->Register.Absolute;
430 src.negate = fsrc->Register.Negate;
431 src.swz[0] = fsrc->Register.SwizzleX;
432 src.swz[1] = fsrc->Register.SwizzleY;
433 src.swz[2] = fsrc->Register.SwizzleZ;
434 src.swz[3] = fsrc->Register.SwizzleW;
435 src.indirect = 0;
436 src.indirect_reg = 0;
437 src.indirect_swz = 0;
438 return src;
439}
440
441static INLINE struct nvfx_reg
442tgsi_dst(struct nvfx_fpc *fpc, const struct tgsi_full_dst_register *fdst) {
443 switch (fdst->Register.File) {
444 case TGSI_FILE_OUTPUT:
445 return fpc->r_result[fdst->Register.Index];
446 case TGSI_FILE_TEMPORARY:
447 return fpc->r_temp[fdst->Register.Index];
448 case TGSI_FILE_NULL:
449 return nvfx_reg(NVFXSR_NONE, 0);
450 default:
451 NOUVEAU_ERR("bad dst file %d\n", fdst->Register.File);
452 return nvfx_reg(NVFXSR_NONE, 0);
453 }
454}
455
456static INLINE int
457tgsi_mask(uint tgsi)
458{
459 int mask = 0;
460
461 if (tgsi & TGSI_WRITEMASK_X) mask |= NVFX_FP_MASK_X;
462 if (tgsi & TGSI_WRITEMASK_Y) mask |= NVFX_FP_MASK_Y;
463 if (tgsi & TGSI_WRITEMASK_Z) mask |= NVFX_FP_MASK_Z;
464 if (tgsi & TGSI_WRITEMASK_W) mask |= NVFX_FP_MASK_W;
465 return mask;
466}
467
468static boolean
469nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
470 const struct tgsi_full_instruction *finst)
471{
472 const struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0));
473 struct nvfx_insn insn;
474 struct nvfx_src src[3], tmp;
475 struct nvfx_reg dst;
476 int mask, sat, unit = 0;
477 int ai = -1, ci = -1, ii = -1;
478 int i;
479
480 if (finst->Instruction.Opcode == TGSI_OPCODE_END)
481 return TRUE;
482
483 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
484 const struct tgsi_full_src_register *fsrc;
485
486 fsrc = &finst->Src[i];
487 if (fsrc->Register.File == TGSI_FILE_TEMPORARY) {
488 src[i] = tgsi_src(fpc, fsrc);
489 }
490 }
491
492 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
493 const struct tgsi_full_src_register *fsrc;
494
495 fsrc = &finst->Src[i];
496
497 switch (fsrc->Register.File) {
498 case TGSI_FILE_INPUT:
499 if(fpc->pfp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_FOG && (0
500 || fsrc->Register.SwizzleX == PIPE_SWIZZLE_ALPHA
501 || fsrc->Register.SwizzleY == PIPE_SWIZZLE_ALPHA
502 || fsrc->Register.SwizzleZ == PIPE_SWIZZLE_ALPHA
503 || fsrc->Register.SwizzleW == PIPE_SWIZZLE_ALPHA
504 )) {
505 /* hardware puts 0 in fogcoord.w, but GL/Gallium want 1 there */
506 struct nvfx_src addend = nvfx_src(nvfx_fp_imm(fpc, 0, 0, 0, 1));
507 addend.swz[0] = fsrc->Register.SwizzleX;
508 addend.swz[1] = fsrc->Register.SwizzleY;
509 addend.swz[2] = fsrc->Register.SwizzleZ;
510 addend.swz[3] = fsrc->Register.SwizzleW;
511 src[i] = nvfx_src(temp(fpc));
512 nvfx_fp_emit(fpc, arith(0, ADD, src[i].reg, NVFX_FP_MASK_ALL, tgsi_src(fpc, fsrc), addend, none));
513 } else if (ai == -1 || ai == fsrc->Register.Index) {
514 ai = fsrc->Register.Index;
515 src[i] = tgsi_src(fpc, fsrc);
516 } else {
517 src[i] = nvfx_src(temp(fpc));
518 nvfx_fp_emit(fpc, arith(0, MOV, src[i].reg, NVFX_FP_MASK_ALL, tgsi_src(fpc, fsrc), none, none));
519 }
520 break;
521 case TGSI_FILE_CONSTANT:
522 if ((ci == -1 && ii == -1) ||
523 ci == fsrc->Register.Index) {
524 ci = fsrc->Register.Index;
525 src[i] = tgsi_src(fpc, fsrc);
526 } else {
527 src[i] = nvfx_src(temp(fpc));
528 nvfx_fp_emit(fpc, arith(0, MOV, src[i].reg, NVFX_FP_MASK_ALL, tgsi_src(fpc, fsrc), none, none));
529 }
530 break;
531 case TGSI_FILE_IMMEDIATE:
532 if ((ci == -1 && ii == -1) ||
533 ii == fsrc->Register.Index) {
534 ii = fsrc->Register.Index;
535 src[i] = tgsi_src(fpc, fsrc);
536 } else {
537 src[i] = nvfx_src(temp(fpc));
538 nvfx_fp_emit(fpc, arith(0, MOV, src[i].reg, NVFX_FP_MASK_ALL, tgsi_src(fpc, fsrc), none, none));
539 }
540 break;
541 case TGSI_FILE_TEMPORARY:
542 /* handled above */
543 break;
544 case TGSI_FILE_SAMPLER:
545 unit = fsrc->Register.Index;
546 break;
547 case TGSI_FILE_OUTPUT:
548 break;
549 default:
550 NOUVEAU_ERR("bad src file\n");
551 return FALSE;
552 }
553 }
554
555 dst = tgsi_dst(fpc, &finst->Dst[0]);
556 mask = tgsi_mask(finst->Dst[0].Register.WriteMask);
557 sat = (finst->Instruction.Saturate == TGSI_SAT_ZERO_ONE);
558
559 switch (finst->Instruction.Opcode) {
560 case TGSI_OPCODE_ABS:
561 nvfx_fp_emit(fpc, arith(sat, MOV, dst, mask, abs(src[0]), none, none));
562 break;
563 case TGSI_OPCODE_ADD:
564 nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, src[0], src[1], none));
565 break;
566 case TGSI_OPCODE_CMP:
567 insn = arith(0, MOV, none.reg, mask, src[0], none, none);
568 insn.cc_update = 1;
569 nvfx_fp_emit(fpc, insn);
570
571 insn = arith(sat, MOV, dst, mask, src[2], none, none);
572 insn.cc_test = NVFX_COND_GE;
573 nvfx_fp_emit(fpc, insn);
574
575 insn = arith(sat, MOV, dst, mask, src[1], none, none);
576 insn.cc_test = NVFX_COND_LT;
577 nvfx_fp_emit(fpc, insn);
578 break;
579 case TGSI_OPCODE_COS:
580 nvfx_fp_emit(fpc, arith(sat, COS, dst, mask, src[0], none, none));
581 break;
582 case TGSI_OPCODE_DDX:
583 if (mask & (NVFX_FP_MASK_Z | NVFX_FP_MASK_W)) {
584 tmp = nvfx_src(temp(fpc));
585 nvfx_fp_emit(fpc, arith(sat, DDX, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, swz(src[0], Z, W, Z, W), none, none));
586 nvfx_fp_emit(fpc, arith(0, MOV, tmp.reg, NVFX_FP_MASK_Z | NVFX_FP_MASK_W, swz(tmp, X, Y, X, Y), none, none));
587 nvfx_fp_emit(fpc, arith(sat, DDX, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, src[0], none, none));
588 nvfx_fp_emit(fpc, arith(0, MOV, dst, mask, tmp, none, none));
589 } else {
590 nvfx_fp_emit(fpc, arith(sat, DDX, dst, mask, src[0], none, none));
591 }
592 break;
593 case TGSI_OPCODE_DDY:
594 if (mask & (NVFX_FP_MASK_Z | NVFX_FP_MASK_W)) {
595 tmp = nvfx_src(temp(fpc));
596 nvfx_fp_emit(fpc, arith(sat, DDY, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, swz(src[0], Z, W, Z, W), none, none));
597 nvfx_fp_emit(fpc, arith(0, MOV, tmp.reg, NVFX_FP_MASK_Z | NVFX_FP_MASK_W, swz(tmp, X, Y, X, Y), none, none));
598 nvfx_fp_emit(fpc, arith(sat, DDY, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, src[0], none, none));
599 nvfx_fp_emit(fpc, arith(0, MOV, dst, mask, tmp, none, none));
600 } else {
601 nvfx_fp_emit(fpc, arith(sat, DDY, dst, mask, src[0], none, none));
602 }
603 break;
604 case TGSI_OPCODE_DP2:
605 tmp = nvfx_src(temp(fpc));
606 nvfx_fp_emit(fpc, arith(0, MUL, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, src[0], src[1], none));
607 nvfx_fp_emit(fpc, arith(0, ADD, dst, mask, swz(tmp, X, X, X, X), swz(tmp, Y, Y, Y, Y), none));
608 break;
609 case TGSI_OPCODE_DP3:
610 nvfx_fp_emit(fpc, arith(sat, DP3, dst, mask, src[0], src[1], none));
611 break;
612 case TGSI_OPCODE_DP4:
613 nvfx_fp_emit(fpc, arith(sat, DP4, dst, mask, src[0], src[1], none));
614 break;
615 case TGSI_OPCODE_DPH:
616 tmp = nvfx_src(temp(fpc));
617 nvfx_fp_emit(fpc, arith(0, DP3, tmp.reg, NVFX_FP_MASK_X, src[0], src[1], none));
618 nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, swz(tmp, X, X, X, X), swz(src[1], W, W, W, W), none));
619 break;
620 case TGSI_OPCODE_DST:
621 nvfx_fp_emit(fpc, arith(sat, DST, dst, mask, src[0], src[1], none));
622 break;
623 case TGSI_OPCODE_EX2:
624 nvfx_fp_emit(fpc, arith(sat, EX2, dst, mask, src[0], none, none));
625 break;
626 case TGSI_OPCODE_FLR:
627 nvfx_fp_emit(fpc, arith(sat, FLR, dst, mask, src[0], none, none));
628 break;
629 case TGSI_OPCODE_FRC:
630 nvfx_fp_emit(fpc, arith(sat, FRC, dst, mask, src[0], none, none));
631 break;
632 case TGSI_OPCODE_KILP:
633 nvfx_fp_emit(fpc, arith(0, KIL, none.reg, 0, none, none, none));
634 break;
635 case TGSI_OPCODE_KIL:
636 insn = arith(0, MOV, none.reg, NVFX_FP_MASK_ALL, src[0], none, none);
637 insn.cc_update = 1;
638 nvfx_fp_emit(fpc, insn);
639
640 insn = arith(0, KIL, none.reg, 0, none, none, none);
641 insn.cc_test = NVFX_COND_LT;
642 nvfx_fp_emit(fpc, insn);
643 break;
644 case TGSI_OPCODE_LG2:
645 nvfx_fp_emit(fpc, arith(sat, LG2, dst, mask, src[0], none, none));
646 break;
647 case TGSI_OPCODE_LIT:
648 if(!nvfx->is_nv4x)
649 nvfx_fp_emit(fpc, arith(sat, LIT_NV30, dst, mask, src[0], src[1], src[2]));
650 else {
651 /* we use FLT_MIN, so that log2 never gives -infinity, and thus multiplication by
652 * specular 0 always gives 0, so that ex2 gives 1, to satisfy the 0^0 = 1 requirement
653 *
654 * NOTE: if we start using half precision, we might need an fp16 FLT_MIN here instead
655 */
656 struct nvfx_src maxs = nvfx_src(nvfx_fp_imm(fpc, 0, FLT_MIN, 0, 0));
657 tmp = nvfx_src(temp(fpc));
658 if (ci>= 0 || ii >= 0) {
659 nvfx_fp_emit(fpc, arith(0, MOV, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, maxs, none, none));
660 maxs = tmp;
661 }
662 nvfx_fp_emit(fpc, arith(0, MAX, tmp.reg, NVFX_FP_MASK_Y | NVFX_FP_MASK_W, swz(src[0], X, X, X, Y), swz(maxs, X, X, Y, Y), none));
663 nvfx_fp_emit(fpc, arith(0, LG2, tmp.reg, NVFX_FP_MASK_W, swz(tmp, W, W, W, W), none, none));
664 nvfx_fp_emit(fpc, arith(0, MUL, tmp.reg, NVFX_FP_MASK_W, swz(tmp, W, W, W, W), swz(src[0], W, W, W, W), none));
665 nvfx_fp_emit(fpc, arith(sat, LITEX2_NV40, dst, mask, swz(tmp, Y, Y, W, W), none, none));
666 }
667 break;
668 case TGSI_OPCODE_LRP:
669 if(!nvfx->is_nv4x)
670 nvfx_fp_emit(fpc, arith(sat, LRP_NV30, dst, mask, src[0], src[1], src[2]));
671 else {
672 tmp = nvfx_src(temp(fpc));
673 nvfx_fp_emit(fpc, arith(0, MAD, tmp.reg, mask, neg(src[0]), src[2], src[2]));
674 nvfx_fp_emit(fpc, arith(sat, MAD, dst, mask, src[0], src[1], tmp));
675 }
676 break;
677 case TGSI_OPCODE_MAD:
678 nvfx_fp_emit(fpc, arith(sat, MAD, dst, mask, src[0], src[1], src[2]));
679 break;
680 case TGSI_OPCODE_MAX:
681 nvfx_fp_emit(fpc, arith(sat, MAX, dst, mask, src[0], src[1], none));
682 break;
683 case TGSI_OPCODE_MIN:
684 nvfx_fp_emit(fpc, arith(sat, MIN, dst, mask, src[0], src[1], none));
685 break;
686 case TGSI_OPCODE_MOV:
687 nvfx_fp_emit(fpc, arith(sat, MOV, dst, mask, src[0], none, none));
688 break;
689 case TGSI_OPCODE_MUL:
690 nvfx_fp_emit(fpc, arith(sat, MUL, dst, mask, src[0], src[1], none));
691 break;
692 case TGSI_OPCODE_NOP:
693 break;
694 case TGSI_OPCODE_POW:
695 if(!nvfx->is_nv4x)
696 nvfx_fp_emit(fpc, arith(sat, POW_NV30, dst, mask, src[0], src[1], none));
697 else {
698 tmp = nvfx_src(temp(fpc));
699 nvfx_fp_emit(fpc, arith(0, LG2, tmp.reg, NVFX_FP_MASK_X, swz(src[0], X, X, X, X), none, none));
700 nvfx_fp_emit(fpc, arith(0, MUL, tmp.reg, NVFX_FP_MASK_X, swz(tmp, X, X, X, X), swz(src[1], X, X, X, X), none));
701 nvfx_fp_emit(fpc, arith(sat, EX2, dst, mask, swz(tmp, X, X, X, X), none, none));
702 }
703 break;
704 case TGSI_OPCODE_RCP:
705 nvfx_fp_emit(fpc, arith(sat, RCP, dst, mask, src[0], none, none));
706 break;
707 case TGSI_OPCODE_RFL:
708 if(!nvfx->is_nv4x)
709 nvfx_fp_emit(fpc, arith(0, RFL_NV30, dst, mask, src[0], src[1], none));
710 else {
711 tmp = nvfx_src(temp(fpc));
712 nvfx_fp_emit(fpc, arith(0, DP3, tmp.reg, NVFX_FP_MASK_X, src[0], src[0], none));
713 nvfx_fp_emit(fpc, arith(0, DP3, tmp.reg, NVFX_FP_MASK_Y, src[0], src[1], none));
714 insn = arith(0, DIV, tmp.reg, NVFX_FP_MASK_Z, swz(tmp, Y, Y, Y, Y), swz(tmp, X, X, X, X), none);
715 insn.scale = NVFX_FP_OP_DST_SCALE_2X;
716 nvfx_fp_emit(fpc, insn);
717 nvfx_fp_emit(fpc, arith(sat, MAD, dst, mask, swz(tmp, Z, Z, Z, Z), src[0], neg(src[1])));
718 }
719 break;
720 case TGSI_OPCODE_RSQ:
721 if(!nvfx->is_nv4x)
722 nvfx_fp_emit(fpc, arith(sat, RSQ_NV30, dst, mask, abs(swz(src[0], X, X, X, X)), none, none));
723 else {
724 tmp = nvfx_src(temp(fpc));
725 insn = arith(0, LG2, tmp.reg, NVFX_FP_MASK_X, abs(swz(src[0], X, X, X, X)), none, none);
726 insn.scale = NVFX_FP_OP_DST_SCALE_INV_2X;
727 nvfx_fp_emit(fpc, insn);
728 nvfx_fp_emit(fpc, arith(sat, EX2, dst, mask, neg(swz(tmp, X, X, X, X)), none, none));
729 }
730 break;
731 case TGSI_OPCODE_SCS:
732 /* avoid overwriting the source */
733 if(src[0].swz[NVFX_SWZ_X] != NVFX_SWZ_X)
734 {
735 if (mask & NVFX_FP_MASK_X)
736 nvfx_fp_emit(fpc, arith(sat, COS, dst, NVFX_FP_MASK_X, swz(src[0], X, X, X, X), none, none));
737 if (mask & NVFX_FP_MASK_Y)
738 nvfx_fp_emit(fpc, arith(sat, SIN, dst, NVFX_FP_MASK_Y, swz(src[0], X, X, X, X), none, none));
739 }
740 else
741 {
742 if (mask & NVFX_FP_MASK_Y)
743 nvfx_fp_emit(fpc, arith(sat, SIN, dst, NVFX_FP_MASK_Y, swz(src[0], X, X, X, X), none, none));
744 if (mask & NVFX_FP_MASK_X)
745 nvfx_fp_emit(fpc, arith(sat, COS, dst, NVFX_FP_MASK_X, swz(src[0], X, X, X, X), none, none));
746 }
747 break;
748 case TGSI_OPCODE_SEQ:
749 nvfx_fp_emit(fpc, arith(sat, SEQ, dst, mask, src[0], src[1], none));
750 break;
751 case TGSI_OPCODE_SFL:
752 nvfx_fp_emit(fpc, arith(sat, SFL, dst, mask, src[0], src[1], none));
753 break;
754 case TGSI_OPCODE_SGE:
755 nvfx_fp_emit(fpc, arith(sat, SGE, dst, mask, src[0], src[1], none));
756 break;
757 case TGSI_OPCODE_SGT:
758 nvfx_fp_emit(fpc, arith(sat, SGT, dst, mask, src[0], src[1], none));
759 break;
760 case TGSI_OPCODE_SIN:
761 nvfx_fp_emit(fpc, arith(sat, SIN, dst, mask, src[0], none, none));
762 break;
763 case TGSI_OPCODE_SLE:
764 nvfx_fp_emit(fpc, arith(sat, SLE, dst, mask, src[0], src[1], none));
765 break;
766 case TGSI_OPCODE_SLT:
767 nvfx_fp_emit(fpc, arith(sat, SLT, dst, mask, src[0], src[1], none));
768 break;
769 case TGSI_OPCODE_SNE:
770 nvfx_fp_emit(fpc, arith(sat, SNE, dst, mask, src[0], src[1], none));
771 break;
772 case TGSI_OPCODE_SSG:
773 {
774 struct nvfx_src minones = swz(nvfx_src(nvfx_fp_imm(fpc, -1, -1, -1, -1)), X, X, X, X);
775
776 insn = arith(sat, MOV, dst, mask, src[0], none, none);
777 insn.cc_update = 1;
778 nvfx_fp_emit(fpc, insn);
779
780 insn = arith(0, STR, dst, mask, none, none, none);
781 insn.cc_test = NVFX_COND_GT;
782 nvfx_fp_emit(fpc, insn);
783
784 if(!sat) {
785 insn = arith(0, MOV, dst, mask, minones, none, none);
786 insn.cc_test = NVFX_COND_LT;
787 nvfx_fp_emit(fpc, insn);
788 }
789 break;
790 }
791 case TGSI_OPCODE_STR:
792 nvfx_fp_emit(fpc, arith(sat, STR, dst, mask, src[0], src[1], none));
793 break;
794 case TGSI_OPCODE_SUB:
795 nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, src[0], neg(src[1]), none));
796 break;
797 case TGSI_OPCODE_TEX:
798 nvfx_fp_emit(fpc, tex(sat, TEX, unit, dst, mask, src[0], none, none));
799 break;
800 case TGSI_OPCODE_TRUNC:
801 tmp = nvfx_src(temp(fpc));
802 insn = arith(0, MOV, none.reg, mask, src[0], none, none);
803 insn.cc_update = 1;
804 nvfx_fp_emit(fpc, insn);
805
806 nvfx_fp_emit(fpc, arith(0, FLR, tmp.reg, mask, abs(src[0]), none, none));
807 nvfx_fp_emit(fpc, arith(sat, MOV, dst, mask, tmp, none, none));
808
809 insn = arith(sat, MOV, dst, mask, neg(tmp), none, none);
810 insn.cc_test = NVFX_COND_LT;
811 nvfx_fp_emit(fpc, insn);
812 break;
813 case TGSI_OPCODE_TXB:
814 nvfx_fp_emit(fpc, tex(sat, TXB, unit, dst, mask, src[0], none, none));
815 break;
816 case TGSI_OPCODE_TXL:
817 if(nvfx->is_nv4x)
818 nvfx_fp_emit(fpc, tex(sat, TXL_NV40, unit, dst, mask, src[0], none, none));
819 else /* unsupported on nv30, use TEX and hope they like it */
820 nvfx_fp_emit(fpc, tex(sat, TEX, unit, dst, mask, src[0], none, none));
821 break;
822 case TGSI_OPCODE_TXP:
823 nvfx_fp_emit(fpc, tex(sat, TXP, unit, dst, mask, src[0], none, none));
824 break;
825 case TGSI_OPCODE_XPD:
826 tmp = nvfx_src(temp(fpc));
827 nvfx_fp_emit(fpc, arith(0, MUL, tmp.reg, mask, swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none));
828 nvfx_fp_emit(fpc, arith(sat, MAD, dst, (mask & ~NVFX_FP_MASK_W), swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y), neg(tmp)));
829 break;
830
831 case TGSI_OPCODE_IF:
832 // MOVRC0 R31 (TR0.xyzw), R<src>:
833 // IF (NE.xxxx) ELSE <else> END <end>
834 if(!nvfx->use_nv4x)
835 goto nv3x_cflow;
836 nv40_fp_if(fpc, src[0]);
837 break;
838
839 case TGSI_OPCODE_ELSE:
840 {
841 uint32_t *hw;
842 if(!nvfx->use_nv4x)
843 goto nv3x_cflow;
844 assert(util_dynarray_contains(&fpc->if_stack, unsigned));
845 hw = &fpc->fp->insn[util_dynarray_top(&fpc->if_stack, unsigned)];
846 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH | fpc->fp->insn_len;
847 break;
848 }
849
850 case TGSI_OPCODE_ENDIF:
851 {
852 uint32_t *hw;
853 if(!nvfx->use_nv4x)
854 goto nv3x_cflow;
855 assert(util_dynarray_contains(&fpc->if_stack, unsigned));
856 hw = &fpc->fp->insn[util_dynarray_pop(&fpc->if_stack, unsigned)];
857 if(!hw[2])
858 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH | fpc->fp->insn_len;
859 hw[3] = fpc->fp->insn_len;
860 break;
861 }
862
863 case TGSI_OPCODE_BRA:
864 /* This can in limited cases be implemented with an IF with the else and endif labels pointing to the target */
865 /* no state tracker uses this, so don't implement this for now */
866 assert(0);
867 nv40_fp_bra(fpc, finst->Label.Label);
868 break;
869
870 case TGSI_OPCODE_BGNSUB:
871 case TGSI_OPCODE_ENDSUB:
872 /* nothing to do here */
873 break;
874
875 case TGSI_OPCODE_CAL:
876 if(!nvfx->use_nv4x)
877 goto nv3x_cflow;
878 nv40_fp_cal(fpc, finst->Label.Label);
879 break;
880
881 case TGSI_OPCODE_RET:
882 if(!nvfx->use_nv4x)
883 goto nv3x_cflow;
884 nv40_fp_ret(fpc);
885 break;
886
887 case TGSI_OPCODE_BGNLOOP:
888 if(!nvfx->use_nv4x)
889 goto nv3x_cflow;
890 /* TODO: we should support using two nested REPs to allow a > 255 iteration count */
891 nv40_fp_rep(fpc, 255, finst->Label.Label);
892 break;
893
894 case TGSI_OPCODE_ENDLOOP:
895 break;
896
897 case TGSI_OPCODE_BRK:
898 if(!nvfx->use_nv4x)
899 goto nv3x_cflow;
900 nv40_fp_brk(fpc);
901 break;
902
903 case TGSI_OPCODE_CONT:
904 {
905 static int warned = 0;
906 if(!warned) {
907 NOUVEAU_ERR("Sorry, the continue keyword is not implemented: ignoring it.\n");
908 warned = 1;
909 }
910 break;
911 }
912
913 default:
914 NOUVEAU_ERR("invalid opcode %d\n", finst->Instruction.Opcode);
915 return FALSE;
916 }
917
918out:
919 release_temps(fpc);
920 return TRUE;
921nv3x_cflow:
922 {
923 static int warned = 0;
924 if(!warned) {
925 NOUVEAU_ERR(
926 "Sorry, control flow instructions are not supported in hardware on nv3x: ignoring them\n"
927 "If rendering is incorrect, try to disable GLSL support in the application.\n");
928 warned = 1;
929 }
930 }
931 goto out;
932}
933
934static boolean
935nvfx_fragprog_parse_decl_output(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
936 const struct tgsi_full_declaration *fdec)
937{
938 unsigned idx = fdec->Range.First;
939 unsigned hw;
940
941 switch (fdec->Semantic.Name) {
942 case TGSI_SEMANTIC_POSITION:
943 hw = 1;
944 break;
945 case TGSI_SEMANTIC_COLOR:
946 hw = ~0;
947 switch (fdec->Semantic.Index) {
948 case 0: hw = 0; break;
949 case 1: hw = 2; break;
950 case 2: hw = 3; break;
951 case 3: hw = 4; break;
952 }
953 if(hw > ((nvfx->use_nv4x) ? 4 : 2)) {
954 NOUVEAU_ERR("bad rcol index\n");
955 return FALSE;
956 }
957 break;
958 default:
959 NOUVEAU_ERR("bad output semantic\n");
960 return FALSE;
961 }
962
963 fpc->r_result[idx] = nvfx_reg(NVFXSR_OUTPUT, hw);
964 fpc->r_temps |= (1ULL << hw);
965 return TRUE;
966}
967
968static boolean
969nvfx_fragprog_prepare(struct nvfx_context* nvfx, struct nvfx_fpc *fpc)
970{
971 struct tgsi_parse_context p;
972 int high_temp = -1, i;
973 struct util_semantic_set set;
974 unsigned num_texcoords = nvfx->use_nv4x ? 10 : 8;
975
976 fpc->fp->num_slots = util_semantic_set_from_program_file(&set, fpc->pfp->pipe.tokens, TGSI_FILE_INPUT);
977 if(fpc->fp->num_slots > num_texcoords)
978 return FALSE;
979 util_semantic_layout_from_set(fpc->fp->slot_to_generic, &set, 0, num_texcoords);
980 util_semantic_table_from_layout(fpc->generic_to_slot, sizeof fpc->generic_to_slot,
981 fpc->fp->slot_to_generic, 0, num_texcoords);
982
983 memset(fpc->fp->slot_to_fp_input, 0xff, sizeof(fpc->fp->slot_to_fp_input));
984
985 fpc->r_imm = CALLOC(fpc->pfp->info.immediate_count, sizeof(struct nvfx_reg));
986
987 tgsi_parse_init(&p, fpc->pfp->pipe.tokens);
988 while (!tgsi_parse_end_of_tokens(&p)) {
989 const union tgsi_full_token *tok = &p.FullToken;
990
991 tgsi_parse_token(&p);
992 switch(tok->Token.Type) {
993 case TGSI_TOKEN_TYPE_DECLARATION:
994 {
995 const struct tgsi_full_declaration *fdec;
996 fdec = &p.FullToken.FullDeclaration;
997 switch (fdec->Declaration.File) {
998 case TGSI_FILE_OUTPUT:
999 if (!nvfx_fragprog_parse_decl_output(nvfx, fpc, fdec))
1000 goto out_err;
1001 break;
1002 case TGSI_FILE_TEMPORARY:
1003 if (fdec->Range.Last > high_temp) {
1004 high_temp =
1005 fdec->Range.Last;
1006 }
1007 break;
1008 default:
1009 break;
1010 }
1011 }
1012 break;
1013 case TGSI_TOKEN_TYPE_IMMEDIATE:
1014 {
1015 struct tgsi_full_immediate *imm;
1016
1017 imm = &p.FullToken.FullImmediate;
1018 assert(imm->Immediate.DataType == TGSI_IMM_FLOAT32);
1019 assert(fpc->nr_imm < fpc->pfp->info.immediate_count);
1020
1021 fpc->r_imm[fpc->nr_imm++] = nvfx_fp_imm(fpc, imm->u[0].Float, imm->u[1].Float, imm->u[2].Float, imm->u[3].Float);
1022 break;
1023 }
1024 default:
1025 break;
1026 }
1027 }
1028 tgsi_parse_free(&p);
1029
1030 if (++high_temp) {
1031 fpc->r_temp = CALLOC(high_temp, sizeof(struct nvfx_reg));
1032 for (i = 0; i < high_temp; i++)
1033 fpc->r_temp[i] = temp(fpc);
1034 fpc->r_temps_discard = 0ULL;
1035 }
1036
1037 return TRUE;
1038
1039out_err:
1040 if (fpc->r_temp) {
1041 FREE(fpc->r_temp);
1042 fpc->r_temp = NULL;
1043 }
1044 tgsi_parse_free(&p);
1045 return FALSE;
1046}
1047
1048DEBUG_GET_ONCE_BOOL_OPTION(nvfx_dump_fp, "NVFX_DUMP_FP", FALSE)
1049
1050static struct nvfx_fragment_program*
1051nvfx_fragprog_translate(struct nvfx_context *nvfx,
1052 struct nvfx_pipe_fragment_program *pfp,
1053 boolean emulate_sprite_flipping)
1054{
1055 struct tgsi_parse_context parse;
1056 struct nvfx_fpc *fpc = NULL;
1057 struct util_dynarray insns;
1058 struct nvfx_fragment_program* fp = NULL;
1059 const int min_size = 4096;
1060
1061 fp = CALLOC_STRUCT(nvfx_fragment_program);
1062 if(!fp)
1063 goto out_err;
1064
1065 fpc = CALLOC_STRUCT(nvfx_fpc);
1066 if (!fpc)
1067 goto out_err;
1068
1069 fpc->max_temps = nvfx->use_nv4x ? 48 : 32;
1070 fpc->pfp = pfp;
1071 fpc->fp = fp;
1072 fpc->num_regs = 2;
1073
1074 for (unsigned i = 0; i < pfp->info.num_properties; ++i) {
1075 if (pfp->info.properties[i].name == TGSI_PROPERTY_FS_COORD_ORIGIN) {
1076 if(pfp->info.properties[i].data[0])
1077 fp->coord_conventions |= NV30_3D_COORD_CONVENTIONS_ORIGIN_INVERTED;
1078 } else if (pfp->info.properties[i].name == TGSI_PROPERTY_FS_COORD_PIXEL_CENTER) {
1079 if(pfp->info.properties[i].data[0])
1080 fp->coord_conventions |= NV30_3D_COORD_CONVENTIONS_CENTER_INTEGER;
1081 }
1082 }
1083
1084 if (!nvfx_fragprog_prepare(nvfx, fpc))
1085 goto out_err;
1086
1087 tgsi_parse_init(&parse, pfp->pipe.tokens);
1088 util_dynarray_init(&insns);
1089
1090 if(emulate_sprite_flipping)
1091 {
1092 struct nvfx_reg reg = temp(fpc);
1093 struct nvfx_src sprite_input = nvfx_src(nvfx_reg(NVFXSR_RELOCATED, fp->num_slots));
1094 struct nvfx_src imm = nvfx_src(nvfx_fp_imm(fpc, 1, -1, 0, 0));
1095
1096 fpc->sprite_coord_temp = reg.index;
1097 fpc->r_temps_discard = 0ULL;
1098 nvfx_fp_emit(fpc, arith(0, MAD, reg, NVFX_FP_MASK_ALL, sprite_input, swz(imm, X, Y, X, X), swz(imm, Z, X, Z, Z)));
1099 }
1100
1101 while (!tgsi_parse_end_of_tokens(&parse)) {
1102 tgsi_parse_token(&parse);
1103
1104 switch (parse.FullToken.Token.Type) {
1105 case TGSI_TOKEN_TYPE_INSTRUCTION:
1106 {
1107 const struct tgsi_full_instruction *finst;
1108
1109 util_dynarray_append(&insns, unsigned, fp->insn_len);
1110 finst = &parse.FullToken.FullInstruction;
1111 if (!nvfx_fragprog_parse_instruction(nvfx, fpc, finst))
1112 goto out_err;
1113 }
1114 break;
1115 default:
1116 break;
1117 }
1118 }
1119 util_dynarray_append(&insns, unsigned, fp->insn_len);
1120
1121 for(unsigned i = 0; i < fpc->label_relocs.size; i += sizeof(struct nvfx_relocation))
1122 {
1123 struct nvfx_relocation* label_reloc = (struct nvfx_relocation*)((char*)fpc->label_relocs.data + i);
1124 fp->insn[label_reloc->location] |= ((unsigned*)insns.data)[label_reloc->target];
1125 }
1126 util_dynarray_fini(&insns);
1127
1128 if(!nvfx->is_nv4x)
1129 fp->fp_control |= (fpc->num_regs-1)/2;
1130 else
1131 fp->fp_control |= fpc->num_regs << NV40_3D_FP_CONTROL_TEMP_COUNT__SHIFT;
1132
1133 /* Terminate final instruction */
1134 if(fp->insn)
1135 fp->insn[fpc->inst_offset] |= 0x00000001;
1136
1137 /* Append NOP + END instruction for branches to the end of the program */
1138 fpc->inst_offset = fp->insn_len;
1139 grow_insns(fpc, 4);
1140 fp->insn[fpc->inst_offset + 0] = 0x00000001;
1141 fp->insn[fpc->inst_offset + 1] = 0x00000000;
1142 fp->insn[fpc->inst_offset + 2] = 0x00000000;
1143 fp->insn[fpc->inst_offset + 3] = 0x00000000;
1144
1145 if(debug_get_option_nvfx_dump_fp())
1146 {
1147 debug_printf("\n");
1148 tgsi_dump(pfp->pipe.tokens, 0);
1149
1150 debug_printf("\n%s fragment program:\n", nvfx->is_nv4x ? "nv4x" : "nv3x");
1151 for (unsigned i = 0; i < fp->insn_len; i += 4)
1152 debug_printf("%3u: %08x %08x %08x %08x\n", i >> 2, fp->insn[i], fp->insn[i + 1], fp->insn[i + 2], fp->insn[i + 3]);
1153 debug_printf("\n");
1154 }
1155
1156 fp->prog_size = (fp->insn_len * 4 + 63) & ~63;
1157
1158 if(fp->prog_size >= min_size)
1159 fp->progs_per_bo = 1;
1160 else
1161 fp->progs_per_bo = min_size / fp->prog_size;
1162 fp->bo_prog_idx = fp->progs_per_bo - 1;
1163
1164out:
1165 tgsi_parse_free(&parse);
1166 if(fpc)
1167 {
1168 if (fpc->r_temp)
1169 FREE(fpc->r_temp);
1170 util_dynarray_fini(&fpc->if_stack);
1171 util_dynarray_fini(&fpc->label_relocs);
1172 util_dynarray_fini(&fpc->imm_data);
1173 //util_dynarray_fini(&fpc->loop_stack);
1174 FREE(fpc);
1175 }
1176 return fp;
1177
1178out_err:
1179 _debug_printf("Error: failed to compile this fragment program:\n");
1180 tgsi_dump(pfp->pipe.tokens, 0);
1181
1182 if(fp)
1183 {
1184 FREE(fp);
1185 fp = NULL;
1186 }
1187 goto out;
1188}
1189
1190static inline void
1191nvfx_fp_memcpy(void* dst, const void* src, size_t len)
1192{
1193#ifndef PIPE_ARCH_BIG_ENDIAN
1194 memcpy(dst, src, len);
1195#else
1196 size_t i;
1197 for(i = 0; i < len; i += 4) {
1198 uint32_t v = *(uint32_t*)((char*)src + i);
1199 *(uint32_t*)((char*)dst + i) = (v >> 16) | (v << 16);
1200 }
1201#endif
1202}
1203
1204/* The hardware only supports immediate constants inside the fragment program,
1205 * and at least on nv30 doesn't support an indirect linkage table.
1206 *
1207 * Hence, we need to patch the fragment program itself both to update constants
1208 * and update linkage.
1209 *
1210 * Using a single fragment program would entail unacceptable stalls if the GPU is
1211 * already rendering with that fragment program.
1212 * Thus, we instead use a "rotating queue" of buffer objects, each of which is
1213 * packed with multiple versions of the same program.
1214 *
1215 * Whenever we need to patch something, we move to the next program and
1216 * patch it. If all buffer objects are in use by the GPU, we allocate another one,
1217 * expanding the queue.
1218 *
1219 * As an additional optimization, we record when all the programs have the
1220 * current input slot configuration, and at that point we stop patching inputs.
1221 * This happens, for instance, if a given fragment program is always used with
1222 * the same vertex program (i.e. always with GLSL), or if the layouts match
1223 * enough (non-GLSL).
1224 *
1225 * Note that instead of using multiple programs, we could push commands
1226 * on the FIFO to patch a single program: it's not fully clear which option is
1227 * faster, but my guess is that the current way is faster.
1228 *
1229 * We also track the previous slot assignments for each version and don't
1230 * patch if they are the same (this could perhaps be removed).
1231 */
1232
1233void
1234nvfx_fragprog_validate(struct nvfx_context *nvfx)
1235{
1236 struct nouveau_channel* chan = nvfx->screen->base.channel;
1237 struct nouveau_grobj *eng3d = nvfx->screen->eng3d;
1238 struct nvfx_pipe_fragment_program *pfp = nvfx->fragprog;
1239 struct nvfx_vertex_program* vp;
1240
1241 // TODO: the multiplication by point_quad_rasterization is probably superfluous
1242 unsigned sprite_coord_enable = nvfx->rasterizer->pipe.point_quad_rasterization * nvfx->rasterizer->pipe.sprite_coord_enable;
1243
1244 boolean emulate_sprite_flipping = sprite_coord_enable && nvfx->rasterizer->pipe.sprite_coord_mode;
1245 unsigned key = emulate_sprite_flipping;
1246 struct nvfx_fragment_program* fp;
1247
1248 fp = pfp->fps[key];
1249 if (!fp)
1250 {
1251 fp = nvfx_fragprog_translate(nvfx, pfp, emulate_sprite_flipping);
1252
1253 if(!fp)
1254 {
1255 if(!nvfx->dummy_fs)
1256 {
1257 struct ureg_program *ureg = ureg_create( TGSI_PROCESSOR_FRAGMENT );
1258 if (ureg)
1259 {
1260 ureg_END( ureg );
1261 nvfx->dummy_fs = ureg_create_shader_and_destroy( ureg, &nvfx->pipe );
1262 }
1263
1264 if(!nvfx->dummy_fs)
1265 {
1266 _debug_printf("Error: unable to create a dummy fragment shader: aborting.");
1267 abort();
1268 }
1269 }
1270
1271 fp = nvfx_fragprog_translate(nvfx, nvfx->dummy_fs, FALSE);
1272 emulate_sprite_flipping = FALSE;
1273
1274 if(!fp)
1275 {
1276 _debug_printf("Error: unable to compile even a dummy fragment shader: aborting.");
1277 abort();
1278 }
1279 }
1280
1281 pfp->fps[key] = fp;
1282 }
1283
1284 vp = nvfx->hw_vertprog;
1285
1286 if (fp->last_vp_id != vp->id || fp->last_sprite_coord_enable != sprite_coord_enable) {
1287 int sprite_real_input = -1;
1288 int sprite_reloc_input;
1289 unsigned i;
1290 fp->last_vp_id = vp->id;
1291 fp->last_sprite_coord_enable = sprite_coord_enable;
1292
1293 if(sprite_coord_enable)
1294 {
1295 sprite_real_input = vp->sprite_fp_input;
1296 if(sprite_real_input < 0)
1297 {
1298 unsigned used_texcoords = 0;
1299 for(unsigned i = 0; i < fp->num_slots; ++i) {
1300 unsigned generic = fp->slot_to_generic[i];
1301 if((generic < 32) && !((1 << generic) & sprite_coord_enable))
1302 {
1303 unsigned char slot_mask = vp->generic_to_fp_input[generic];
1304 if(slot_mask >= 0xf0)
1305 used_texcoords |= 1 << ((slot_mask & 0xf) - NVFX_FP_OP_INPUT_SRC_TC0);
1306 }
1307 }
1308
1309 sprite_real_input = NVFX_FP_OP_INPUT_SRC_TC(__builtin_ctz(~used_texcoords));
1310 }
1311
1312 fp->point_sprite_control |= (1 << (sprite_real_input - NVFX_FP_OP_INPUT_SRC_TC0 + 8));
1313 }
1314 else
1315 fp->point_sprite_control = 0;
1316
1317 if(emulate_sprite_flipping)
1318 sprite_reloc_input = 0;
1319 else
1320 sprite_reloc_input = sprite_real_input;
1321
1322 for(i = 0; i < fp->num_slots; ++i) {
1323 unsigned generic = fp->slot_to_generic[i];
1324 if((generic < 32) && ((1 << generic) & sprite_coord_enable))
1325 {
1326 if(fp->slot_to_fp_input[i] != sprite_reloc_input)
1327 goto update_slots;
1328 }
1329 else
1330 {
1331 unsigned char slot_mask = vp->generic_to_fp_input[generic];
1332 if((slot_mask >> 4) & (slot_mask ^ fp->slot_to_fp_input[i]))
1333 goto update_slots;
1334 }
1335 }
1336
1337 if(emulate_sprite_flipping)
1338 {
1339 if(fp->slot_to_fp_input[fp->num_slots] != sprite_real_input)
1340 goto update_slots;
1341 }
1342
1343 if(0)
1344 {
1345update_slots:
1346 /* optimization: we start updating from the slot we found the first difference in */
1347 for(; i < fp->num_slots; ++i)
1348 {
1349 unsigned generic = fp->slot_to_generic[i];
1350 if((generic < 32) && ((1 << generic) & sprite_coord_enable))
1351 fp->slot_to_fp_input[i] = sprite_reloc_input;
1352 else
1353 fp->slot_to_fp_input[i] = vp->generic_to_fp_input[generic] & 0xf;
1354 }
1355
1356 fp->slot_to_fp_input[fp->num_slots] = sprite_real_input;
1357
1358 if(nvfx->is_nv4x)
1359 {
1360 fp->or = 0;
1361 for(i = 0; i <= fp->num_slots; ++i) {
1362 unsigned fp_input = fp->slot_to_fp_input[i];
1363 if(fp_input == NVFX_FP_OP_INPUT_SRC_TC(8))
1364 fp->or |= (1 << 12);
1365 else if(fp_input == NVFX_FP_OP_INPUT_SRC_TC(9))
1366 fp->or |= (1 << 13);
1367 else if(fp_input >= NVFX_FP_OP_INPUT_SRC_TC(0) && fp_input <= NVFX_FP_OP_INPUT_SRC_TC(7))
1368 fp->or |= (1 << (fp_input - NVFX_FP_OP_INPUT_SRC_TC0 + 14));
1369 }
1370 }
1371
1372 fp->progs_left_with_obsolete_slot_assignments = fp->progs;
1373 goto update;
1374 }
1375 }
1376
1377 /* We must update constants even on "just" fragprog changes, because
1378 * we don't check whether the current constant buffer matches the latest
1379 * one bound to this fragment program.
1380 * Doing such a check would likely be a pessimization.
1381 */
1382 if ((nvfx->hw_fragprog != fp) || (nvfx->dirty & (NVFX_NEW_FRAGPROG | NVFX_NEW_FRAGCONST))) {
1383 int offset;
1384 uint32_t* fpmap;
1385
1386update:
1387 ++fp->bo_prog_idx;
1388 if(fp->bo_prog_idx >= fp->progs_per_bo)
1389 {
1390 if(fp->fpbo && !nouveau_bo_busy(fp->fpbo->next->bo, NOUVEAU_BO_WR))
1391 {
1392 fp->fpbo = fp->fpbo->next;
1393 }
1394 else
1395 {
1396 struct nvfx_fragment_program_bo* fpbo = os_malloc_aligned(sizeof(struct nvfx_fragment_program) + (fp->prog_size + 8) * fp->progs_per_bo, 16);
1397 uint8_t* map;
1398 uint8_t* buf;
1399
1400 fpbo->slots = (unsigned char*)&fpbo->insn[(fp->prog_size) * fp->progs_per_bo];
1401 memset(fpbo->slots, 0, 8 * fp->progs_per_bo);
1402 if(fp->fpbo)
1403 {
1404 fpbo->next = fp->fpbo->next;
1405 fp->fpbo->next = fpbo;
1406 }
1407 else
1408 fpbo->next = fpbo;
1409 fp->fpbo = fpbo;
1410 fpbo->bo = 0;
1411 fp->progs += fp->progs_per_bo;
1412 fp->progs_left_with_obsolete_slot_assignments += fp->progs_per_bo;
1413 nouveau_bo_new(nvfx->screen->base.device, NOUVEAU_BO_VRAM | NOUVEAU_BO_MAP, 64, fp->prog_size * fp->progs_per_bo, &fpbo->bo);
1414 nouveau_bo_map(fpbo->bo, NOUVEAU_BO_NOSYNC);
1415
1416 map = fpbo->bo->map;
1417 buf = (uint8_t*)fpbo->insn;
1418 for(unsigned i = 0; i < fp->progs_per_bo; ++i)
1419 {
1420 memcpy(buf, fp->insn, fp->insn_len * 4);
1421 nvfx_fp_memcpy(map, fp->insn, fp->insn_len * 4);
1422 map += fp->prog_size;
1423 buf += fp->prog_size;
1424 }
1425 }
1426 fp->bo_prog_idx = 0;
1427 }
1428
1429 offset = fp->bo_prog_idx * fp->prog_size;
1430 fpmap = (uint32_t*)((char*)fp->fpbo->bo->map + offset);
1431
1432 if(nvfx->constbuf[PIPE_SHADER_FRAGMENT]) {
1433 struct pipe_resource* constbuf = nvfx->constbuf[PIPE_SHADER_FRAGMENT];
1434 uint32_t* map = (uint32_t*)nvfx_buffer(constbuf)->data;
1435 uint32_t* fpmap = (uint32_t*)((char*)fp->fpbo->bo->map + offset);
1436 uint32_t* buf = (uint32_t*)((char*)fp->fpbo->insn + offset);
1437 int i;
1438 for (i = 0; i < fp->nr_consts; ++i) {
1439 unsigned off = fp->consts[i].offset;
1440 unsigned idx = fp->consts[i].index * 4;
1441
1442 /* TODO: is checking a good idea? */
1443 if(memcmp(&buf[off], &map[idx], 4 * sizeof(uint32_t))) {
1444 memcpy(&buf[off], &map[idx], 4 * sizeof(uint32_t));
1445 nvfx_fp_memcpy(&fpmap[off], &map[idx], 4 * sizeof(uint32_t));
1446 }
1447 }
1448 }
1449
1450 /* we only do this if we aren't sure that all program versions have the
1451 * current slot assignments, otherwise we just update constants for speed
1452 */
1453 if(fp->progs_left_with_obsolete_slot_assignments) {
1454 unsigned char* fpbo_slots = &fp->fpbo->slots[fp->bo_prog_idx * 8];
1455 /* also relocate sprite coord slot, if any */
1456 for(unsigned i = 0; i <= fp->num_slots; ++i) {
1457 unsigned value = fp->slot_to_fp_input[i];;
1458 if(value != fpbo_slots[i]) {
1459 unsigned* p;
1460 unsigned* begin = (unsigned*)fp->slot_relocations[i].data;
1461 unsigned* end = (unsigned*)((char*)fp->slot_relocations[i].data + fp->slot_relocations[i].size);
1462 //printf("fp %p reloc slot %u/%u: %u -> %u\n", fp, i, fp->num_slots, fpbo_slots[i], value);
1463 if(value == 0)
1464 {
1465 /* was relocated to an input, switch type to temporary */
1466 for(p = begin; p != end; ++p) {
1467 unsigned off = *p;
1468 unsigned dw = fp->insn[off];
1469 dw &=~ NVFX_FP_REG_TYPE_MASK;
1470 //printf("reloc_tmp at %x\n", off);
1471 nvfx_fp_memcpy(&fpmap[off], &dw, sizeof(dw));
1472 }
1473 } else {
1474 if(!fpbo_slots[i])
1475 {
1476 /* was relocated to a temporary, switch type to input */
1477 for(p= begin; p != end; ++p) {
1478 unsigned off = *p;
1479 unsigned dw = fp->insn[off];
1480 //printf("reloc_in at %x\n", off);
1481 dw |= NVFX_FP_REG_TYPE_INPUT << NVFX_FP_REG_TYPE_SHIFT;
1482 nvfx_fp_memcpy(&fpmap[off], &dw, sizeof(dw));
1483 }
1484 }
1485
1486 /* set the correct input index */
1487 for(p = begin; p != end; ++p) {
1488 unsigned off = *p & ~3;
1489 unsigned dw = fp->insn[off];
1490 //printf("reloc&~3 at %x\n", off);
1491 dw = (dw & ~NVFX_FP_OP_INPUT_SRC_MASK) | (value << NVFX_FP_OP_INPUT_SRC_SHIFT);
1492 nvfx_fp_memcpy(&fpmap[off], &dw, sizeof(dw));
1493 }
1494 }
1495 fpbo_slots[i] = value;
1496 }
1497 }
1498 --fp->progs_left_with_obsolete_slot_assignments;
1499 }
1500
1501 nvfx->hw_fragprog = fp;
1502
1503 MARK_RING(chan, 8, 1);
1504 BEGIN_RING(chan, eng3d, NV30_3D_FP_ACTIVE_PROGRAM, 1);
1505 OUT_RELOC(chan, fp->fpbo->bo, offset, NOUVEAU_BO_VRAM |
1506 NOUVEAU_BO_GART | NOUVEAU_BO_RD | NOUVEAU_BO_LOW |
1507 NOUVEAU_BO_OR, NV30_3D_FP_ACTIVE_PROGRAM_DMA0,
1508 NV30_3D_FP_ACTIVE_PROGRAM_DMA1);
1509 BEGIN_RING(chan, eng3d, NV30_3D_FP_CONTROL, 1);
1510 OUT_RING(chan, fp->fp_control);
1511 if(!nvfx->is_nv4x) {
1512 BEGIN_RING(chan, eng3d, NV30_3D_FP_REG_CONTROL, 1);
1513 OUT_RING(chan, (1<<16)|0x4);
1514 BEGIN_RING(chan, eng3d, NV30_3D_TEX_UNITS_ENABLE, 1);
1515 OUT_RING(chan, fp->samplers);
1516 }
1517 }
1518
1519 {
1520 unsigned pointsprite_control = fp->point_sprite_control | nvfx->rasterizer->pipe.point_quad_rasterization;
1521 if(pointsprite_control != nvfx->hw_pointsprite_control)
1522 {
1523 BEGIN_RING(chan, eng3d, NV30_3D_POINT_SPRITE, 1);
1524 OUT_RING(chan, pointsprite_control);
1525 nvfx->hw_pointsprite_control = pointsprite_control;
1526 }
1527 }
1528
1529 nvfx->relocs_needed &=~ NVFX_RELOCATE_FRAGPROG;
1530}
1531
1532void
1533nvfx_fragprog_relocate(struct nvfx_context *nvfx)
1534{
1535 struct nouveau_channel* chan = nvfx->screen->base.channel;
1536 struct nvfx_fragment_program *fp = nvfx->hw_fragprog;
1537 struct nouveau_bo* bo = fp->fpbo->bo;
1538 int offset = fp->bo_prog_idx * fp->prog_size;
1539 unsigned fp_flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD; // TODO: GART?
1540 fp_flags |= NOUVEAU_BO_DUMMY;
1541 MARK_RING(chan, 2, 2);
1542 OUT_RELOC(chan, bo, RING_3D(NV30_3D_FP_ACTIVE_PROGRAM, 1), fp_flags, 0, 0);
1543 OUT_RELOC(chan, bo, offset, fp_flags | NOUVEAU_BO_LOW |
1544 NOUVEAU_BO_OR, NV30_3D_FP_ACTIVE_PROGRAM_DMA0,
1545 NV30_3D_FP_ACTIVE_PROGRAM_DMA1);
1546 nvfx->relocs_needed &=~ NVFX_RELOCATE_FRAGPROG;
1547}
1548
1549void
1550nvfx_fragprog_destroy(struct nvfx_context *nvfx,
1551 struct nvfx_fragment_program *fp)
1552{
1553 unsigned i;
1554 struct nvfx_fragment_program_bo* fpbo = fp->fpbo;
1555 if(fpbo)
1556 {
1557 do
1558 {
1559 struct nvfx_fragment_program_bo* next = fpbo->next;
1560 nouveau_bo_unmap(fpbo->bo);
1561 nouveau_bo_ref(0, &fpbo->bo);
1562 os_free_aligned(fpbo);
1563 fpbo = next;
1564 }
1565 while(fpbo != fp->fpbo);
1566 }
1567
1568 for(i = 0; i < Elements(fp->slot_relocations); ++i)
1569 util_dynarray_fini(&fp->slot_relocations[i]);
1570
1571 if (fp->insn_len)
1572 FREE(fp->insn);
1573}
1574
1575static void *
1576nvfx_fp_state_create(struct pipe_context *pipe,
1577 const struct pipe_shader_state *cso)
1578{
1579 struct nvfx_pipe_fragment_program *pfp;
1580
1581 pfp = CALLOC(1, sizeof(struct nvfx_pipe_fragment_program));
1582 pfp->pipe.tokens = tgsi_dup_tokens(cso->tokens);
1583
1584 tgsi_scan_shader(pfp->pipe.tokens, &pfp->info);
1585
1586 return (void *)pfp;
1587}
1588
1589static void
1590nvfx_fp_state_bind(struct pipe_context *pipe, void *hwcso)
1591{
1592 struct nvfx_context *nvfx = nvfx_context(pipe);
1593
1594 nvfx->fragprog = hwcso;
1595 nvfx->dirty |= NVFX_NEW_FRAGPROG;
1596}
1597
1598static void
1599nvfx_fp_state_delete(struct pipe_context *pipe, void *hwcso)
1600{
1601 struct nvfx_context *nvfx = nvfx_context(pipe);
1602 struct nvfx_pipe_fragment_program *pfp = hwcso;
1603 unsigned i;
1604
1605 for(i = 0; i < Elements(pfp->fps); ++i)
1606 {
1607 if(pfp->fps[i])
1608 {
1609 nvfx_fragprog_destroy(nvfx, pfp->fps[i]);
1610 FREE(pfp->fps[i]);
1611 }
1612 }
1613
1614 FREE((void*)pfp->pipe.tokens);
1615 FREE(pfp);
1616}
1617
1618void
1619nvfx_init_fragprog_functions(struct nvfx_context *nvfx)
1620{
1621 nvfx->pipe.create_fs_state = nvfx_fp_state_create;
1622 nvfx->pipe.bind_fs_state = nvfx_fp_state_bind;
1623 nvfx->pipe.delete_fs_state = nvfx_fp_state_delete;
1624}
diff --git a/src/gallium/drivers/nvfx/nvfx_fragtex.c b/src/gallium/drivers/nvfx/nvfx_fragtex.c
deleted file mode 100644
index 036991e55dc..00000000000
--- a/src/gallium/drivers/nvfx/nvfx_fragtex.c
+++ /dev/null
@@ -1,355 +0,0 @@
1#include "nvfx_context.h"
2#include "nvfx_resource.h"
3#include "nvfx_tex.h"
4
5static void *
6nvfx_sampler_state_create(struct pipe_context *pipe,
7 const struct pipe_sampler_state *cso)
8{
9 struct nvfx_context *nvfx = nvfx_context(pipe);
10 struct nvfx_sampler_state *ps;
11
12 ps = MALLOC(sizeof(struct nvfx_sampler_state));
13
14 /* on nv30, we use this as an internal flag */
15 ps->fmt = cso->normalized_coords ? 0 : NV40_3D_TEX_FORMAT_RECT;
16 ps->en = 0;
17 ps->filt = nvfx_tex_filter(cso) | 0x2000; /*voodoo*/
18 ps->wrap = (nvfx_tex_wrap_mode(cso->wrap_s) << NV30_3D_TEX_WRAP_S__SHIFT) |
19 (nvfx_tex_wrap_mode(cso->wrap_t) << NV30_3D_TEX_WRAP_T__SHIFT) |
20 (nvfx_tex_wrap_mode(cso->wrap_r) << NV30_3D_TEX_WRAP_R__SHIFT);
21 ps->compare = FALSE;
22
23 if(cso->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE)
24 {
25 ps->wrap |= nvfx_tex_wrap_compare_mode(cso->compare_func);
26 ps->compare = TRUE;
27 }
28 ps->bcol = nvfx_tex_border_color(cso->border_color.f);
29
30 if(nvfx->is_nv4x)
31 nv40_sampler_state_init(pipe, ps, cso);
32 else
33 nv30_sampler_state_init(pipe, ps, cso);
34
35 return (void *)ps;
36}
37
38static void
39nvfx_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
40{
41 FREE(hwcso);
42}
43
44static void
45nvfx_sampler_state_bind(struct pipe_context *pipe, unsigned nr, void **sampler)
46{
47 struct nvfx_context *nvfx = nvfx_context(pipe);
48 unsigned unit;
49
50 for (unit = 0; unit < nr; unit++) {
51 nvfx->tex_sampler[unit] = sampler[unit];
52 nvfx->dirty_samplers |= (1 << unit);
53 }
54
55 for (unit = nr; unit < nvfx->nr_samplers; unit++) {
56 nvfx->tex_sampler[unit] = NULL;
57 nvfx->dirty_samplers |= (1 << unit);
58 }
59
60 nvfx->nr_samplers = nr;
61 nvfx->dirty |= NVFX_NEW_SAMPLER;
62}
63
64static struct pipe_sampler_view *
65nvfx_create_sampler_view(struct pipe_context *pipe,
66 struct pipe_resource *pt,
67 const struct pipe_sampler_view *templ)
68{
69 struct nvfx_context *nvfx = nvfx_context(pipe);
70 struct nvfx_sampler_view *sv = CALLOC_STRUCT(nvfx_sampler_view);
71 struct nvfx_texture_format *tf = &nvfx_texture_formats[templ->format];
72 unsigned txf;
73
74 if (!sv)
75 return NULL;
76
77 sv->base = *templ;
78 sv->base.reference.count = 1;
79 sv->base.texture = NULL;
80 pipe_resource_reference(&sv->base.texture, pt);
81 sv->base.context = pipe;
82
83 txf = NV30_3D_TEX_FORMAT_NO_BORDER;
84
85 switch (pt->target) {
86 case PIPE_TEXTURE_CUBE:
87 txf |= NV30_3D_TEX_FORMAT_CUBIC;
88 /* fall-through */
89 case PIPE_TEXTURE_2D:
90 case PIPE_TEXTURE_RECT:
91 txf |= NV30_3D_TEX_FORMAT_DIMS_2D;
92 break;
93 case PIPE_TEXTURE_3D:
94 txf |= NV30_3D_TEX_FORMAT_DIMS_3D;
95 break;
96 case PIPE_TEXTURE_1D:
97 txf |= NV30_3D_TEX_FORMAT_DIMS_1D;
98 break;
99 default:
100 assert(0);
101 }
102 sv->u.init_fmt = txf;
103
104 sv->swizzle = 0
105 | (tf->src[sv->base.swizzle_r] << NV30_3D_TEX_SWIZZLE_S0_Z__SHIFT)
106 | (tf->src[sv->base.swizzle_g] << NV30_3D_TEX_SWIZZLE_S0_Y__SHIFT)
107 | (tf->src[sv->base.swizzle_b] << NV30_3D_TEX_SWIZZLE_S0_X__SHIFT)
108 | (tf->src[sv->base.swizzle_a] << NV30_3D_TEX_SWIZZLE_S0_W__SHIFT)
109 | (tf->comp[sv->base.swizzle_r] << NV30_3D_TEX_SWIZZLE_S1_Z__SHIFT)
110 | (tf->comp[sv->base.swizzle_g] << NV30_3D_TEX_SWIZZLE_S1_Y__SHIFT)
111 | (tf->comp[sv->base.swizzle_b] << NV30_3D_TEX_SWIZZLE_S1_X__SHIFT)
112 | (tf->comp[sv->base.swizzle_a] << NV30_3D_TEX_SWIZZLE_S1_W__SHIFT);
113
114 sv->filt = tf->sign;
115 sv->wrap = tf->wrap;
116 sv->wrap_mask = ~0;
117
118 if (pt->target == PIPE_TEXTURE_CUBE)
119 {
120 sv->offset = 0;
121 sv->npot_size = (pt->width0 << NV30_3D_TEX_NPOT_SIZE_W__SHIFT) | pt->height0;
122 }
123 else
124 {
125 sv->offset = nvfx_subresource_offset(pt, 0, sv->base.u.tex.first_level, 0);
126 sv->npot_size = (u_minify(pt->width0, sv->base.u.tex.first_level) << NV30_3D_TEX_NPOT_SIZE_W__SHIFT) | u_minify(pt->height0, sv->base.u.tex.first_level);
127
128 /* apparently, we need to ignore the t coordinate for 1D textures to fix piglit tex1d-2dborder */
129 if(pt->target == PIPE_TEXTURE_1D)
130 {
131 sv->wrap_mask &=~ NV30_3D_TEX_WRAP_T__MASK;
132 sv->wrap |= NV30_3D_TEX_WRAP_T_REPEAT;
133 }
134 }
135
136 if(nvfx->is_nv4x)
137 nv40_sampler_view_init(pipe, sv);
138 else
139 nv30_sampler_view_init(pipe, sv);
140
141 return &sv->base;
142}
143
144static void
145nvfx_sampler_view_destroy(struct pipe_context *pipe,
146 struct pipe_sampler_view *view)
147{
148 pipe_resource_reference(&view->texture, NULL);
149 FREE(view);
150}
151
152static void
153nvfx_set_fragment_sampler_views(struct pipe_context *pipe,
154 unsigned nr,
155 struct pipe_sampler_view **views)
156{
157 struct nvfx_context *nvfx = nvfx_context(pipe);
158 unsigned unit;
159
160 for (unit = 0; unit < nr; unit++) {
161 pipe_sampler_view_reference(&nvfx->fragment_sampler_views[unit],
162 views[unit]);
163 nvfx->dirty_samplers |= (1 << unit);
164 }
165
166 for (unit = nr; unit < nvfx->nr_textures; unit++) {
167 pipe_sampler_view_reference(&nvfx->fragment_sampler_views[unit],
168 NULL);
169 nvfx->dirty_samplers |= (1 << unit);
170 }
171
172 nvfx->nr_textures = nr;
173 nvfx->dirty |= NVFX_NEW_SAMPLER;
174}
175
176void
177nvfx_fragtex_validate(struct nvfx_context *nvfx)
178{
179 struct nouveau_channel* chan = nvfx->screen->base.channel;
180 struct nouveau_grobj *eng3d = nvfx->screen->eng3d;
181 unsigned samplers, unit;
182
183 samplers = nvfx->dirty_samplers;
184 if(!samplers)
185 return;
186
187 while (samplers) {
188 unit = ffs(samplers) - 1;
189 samplers &= ~(1 << unit);
190
191 if(nvfx->fragment_sampler_views[unit] && nvfx->tex_sampler[unit]) {
192 if(!nvfx->is_nv4x)
193 nv30_fragtex_set(nvfx, unit);
194 else
195 nv40_fragtex_set(nvfx, unit);
196 } else {
197 /* this is OK for nv40 too */
198 BEGIN_RING(chan, eng3d, NV30_3D_TEX_ENABLE(unit), 1);
199 OUT_RING(chan, 0);
200 nvfx->hw_samplers &= ~(1 << unit);
201 }
202 }
203 nvfx->dirty_samplers = 0;
204 nvfx->relocs_needed &=~ NVFX_RELOCATE_FRAGTEX;
205}
206
207void
208nvfx_fragtex_relocate(struct nvfx_context *nvfx)
209{
210 struct nouveau_channel* chan = nvfx->screen->base.channel;
211 unsigned samplers, unit;
212 unsigned tex_flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD;
213
214 samplers = nvfx->hw_samplers;
215 while (samplers) {
216 struct nvfx_miptree* mt;
217 struct nouveau_bo *bo;
218
219 unit = ffs(samplers) - 1;
220 samplers &= ~(1 << unit);
221
222 mt = (struct nvfx_miptree*)nvfx->fragment_sampler_views[unit]->texture;
223 bo = mt->base.bo;
224
225 MARK_RING(chan, 3, 3);
226 OUT_RELOC(chan, bo, RING_3D(NV30_3D_TEX_OFFSET(unit), 2), tex_flags | NOUVEAU_BO_DUMMY, 0, 0);
227 OUT_RELOC(chan, bo, 0, tex_flags | NOUVEAU_BO_LOW | NOUVEAU_BO_DUMMY, 0, 0);
228 OUT_RELOC(chan, bo, nvfx->hw_txf[unit], tex_flags | NOUVEAU_BO_OR | NOUVEAU_BO_DUMMY,
229 NV30_3D_TEX_FORMAT_DMA0, NV30_3D_TEX_FORMAT_DMA1);
230 }
231 nvfx->relocs_needed &=~ NVFX_RELOCATE_FRAGTEX;
232}
233
234void
235nvfx_init_sampling_functions(struct nvfx_context *nvfx)
236{
237 nvfx->pipe.create_sampler_state = nvfx_sampler_state_create;
238 nvfx->pipe.bind_fragment_sampler_states = nvfx_sampler_state_bind;
239 nvfx->pipe.delete_sampler_state = nvfx_sampler_state_delete;
240 nvfx->pipe.set_fragment_sampler_views = nvfx_set_fragment_sampler_views;
241 nvfx->pipe.create_sampler_view = nvfx_create_sampler_view;
242 nvfx->pipe.sampler_view_destroy = nvfx_sampler_view_destroy;
243}
244
245#define NV30_3D_TEX_FORMAT_FORMAT_DXT1_RECT NV30_3D_TEX_FORMAT_FORMAT_DXT1
246#define NV30_3D_TEX_FORMAT_FORMAT_DXT3_RECT NV30_3D_TEX_FORMAT_FORMAT_DXT3
247#define NV30_3D_TEX_FORMAT_FORMAT_DXT5_RECT NV30_3D_TEX_FORMAT_FORMAT_DXT5
248
249#define NV40_3D_TEX_FORMAT_FORMAT_HILO16 NV40_3D_TEX_FORMAT_FORMAT_A16L16
250
251#define NV30_3D_TEX_FORMAT_FORMAT_RGBA16F 0x00004a00
252#define NV30_3D_TEX_FORMAT_FORMAT_RGBA16F_RECT NV30_3D_TEX_FORMAT_FORMAT_RGBA16F
253#define NV30_3D_TEX_FORMAT_FORMAT_RGBA32F 0x00004b00
254#define NV30_3D_TEX_FORMAT_FORMAT_RGBA32F_RECT NV30_3D_TEX_FORMAT_FORMAT_RGBA32F
255#define NV30_3D_TEX_FORMAT_FORMAT_R32F 0x00004c00
256#define NV30_3D_TEX_FORMAT_FORMAT_R32F_RECT NV30_3D_TEX_FORMAT_FORMAT_R32F
257
258// TODO: guess!
259#define NV40_3D_TEX_FORMAT_FORMAT_R32F 0x00001c00
260
261#define SRGB 0x00700000
262
263#define __(m,tf,tfc,ts0x,ts0y,ts0z,ts0w,ts1x,ts1y,ts1z,ts1w,sign,wrap) \
264[PIPE_FORMAT_##m] = { \
265 {NV30_3D_TEX_FORMAT_FORMAT_##tf, \
266 NV30_3D_TEX_FORMAT_FORMAT_##tfc, \
267 NV30_3D_TEX_FORMAT_FORMAT_##tf##_RECT, \
268 NV30_3D_TEX_FORMAT_FORMAT_##tfc##_RECT, \
269 NV40_3D_TEX_FORMAT_FORMAT_##tf, \
270 NV40_3D_TEX_FORMAT_FORMAT_##tfc}, \
271 sign, wrap, \
272 {ts0z, ts0y, ts0x, ts0w, 0, 1}, {ts1z, ts1y, ts1x, ts1w, 0, 0} \
273}
274
275#define _(m,tf,ts0x,ts0y,ts0z,ts0w,ts1x,ts1y,ts1z,ts1w,sign, wrap) \
276 __(m,tf,tf,ts0x,ts0y,ts0z,ts0w,ts1x,ts1y,ts1z,ts1w,sign, wrap)
277
278/* Depth formats works by reading the depth value most significant 8/16 bits.
279 * We are losing precision, but nVidia loses even more by using A8R8G8B8 instead of HILO16
280 * There is no 32-bit integer texture support, so other things are infeasible.
281 *
282 * TODO: is it possible to read 16 bits for Z16? A16 doesn't seem to work, either due to normalization or endianness issues
283 */
284
285#define T 2
286
287#define X 3
288#define Y 2
289#define Z 1
290#define W 0
291
292#define SNORM ((NV30_3D_TEX_FILTER_SIGNED_RED) | (NV30_3D_TEX_FILTER_SIGNED_GREEN) | (NV30_3D_TEX_FILTER_SIGNED_BLUE) | (NV30_3D_TEX_FILTER_SIGNED_ALPHA))
293#define UNORM 0
294
295struct nvfx_texture_format
296nvfx_texture_formats[PIPE_FORMAT_COUNT] = {
297 [0 ... PIPE_FORMAT_COUNT - 1] = {{-1, -1, -1, -1, -1, -1}},
298 _(B8G8R8X8_UNORM, A8R8G8B8, T, T, T, 1, X, Y, Z, W, UNORM, 0),
299 _(B8G8R8X8_SRGB, A8R8G8B8, T, T, T, 1, X, Y, Z, W, UNORM, SRGB),
300 _(B8G8R8A8_UNORM, A8R8G8B8, T, T, T, T, X, Y, Z, W, UNORM, 0),
301 _(B8G8R8A8_SRGB, A8R8G8B8, T, T, T, T, X, Y, Z, W, UNORM, SRGB),
302
303 _(R8G8B8A8_UNORM, A8R8G8B8, T, T, T, T, Z, Y, X, W, UNORM, 0),
304 _(R8G8B8A8_SRGB, A8R8G8B8, T, T, T, T, Z, Y, X, W, UNORM, SRGB),
305 _(R8G8B8X8_UNORM, A8R8G8B8, T, T, T, 1, Z, Y, X, W, UNORM, 0),
306
307 _(A8R8G8B8_UNORM, A8R8G8B8, T, T, T, T, W, Z, Y, X, UNORM, 0),
308 _(A8R8G8B8_SRGB, A8R8G8B8, T, T, T, T, W, Z, Y, X, UNORM, SRGB),
309 _(A8B8G8R8_UNORM, A8R8G8B8, T, T, T, T, W, X, Y, Z, UNORM, 0),
310 _(A8B8G8R8_SRGB, A8R8G8B8, T, T, T, T, W, X, Y, Z, UNORM, SRGB),
311 _(X8R8G8B8_UNORM, A8R8G8B8, T, T, T, 1, W, Z, Y, X, UNORM, 0),
312 _(X8R8G8B8_SRGB, A8R8G8B8, T, T, T, 1, W, Z, Y, X, UNORM, SRGB),
313
314 _(B5G5R5A1_UNORM, A1R5G5B5, T, T, T, T, X, Y, Z, W, UNORM, 0),
315 _(B5G5R5X1_UNORM, A1R5G5B5, T, T, T, 1, X, Y, Z, W, UNORM, 0),
316
317 _(B4G4R4A4_UNORM, A4R4G4B4, T, T, T, T, X, Y, Z, W, UNORM, 0),
318 _(B4G4R4X4_UNORM, A4R4G4B4, T, T, T, 1, X, Y, Z, W, UNORM, 0),
319
320 _(B5G6R5_UNORM, R5G6B5, T, T, T, 1, X, Y, Z, W, UNORM, 0),
321
322 _(R8_UNORM, L8, T, 0, 0, 1, X, X, X, X, UNORM, 0),
323 _(R8_SNORM, L8, T, 0, 0, 1, X, X, X, X, SNORM, 0),
324 _(L8_UNORM, L8, T, T, T, 1, X, X, X, X, UNORM, 0),
325 _(L8_SRGB, L8, T, T, T, 1, X, X, X, X, UNORM, SRGB),
326 _(A8_UNORM, L8, 0, 0, 0, T, X, X, X, X, UNORM, 0),
327 _(I8_UNORM, L8, T, T, T, T, X, X, X, X, UNORM, 0),
328
329 _(R8G8_UNORM, A8L8, T, T, T, T, X, X, X, W, UNORM, 0),
330 _(R8G8_SNORM, A8L8, T, T, T, T, X, X, X, W, SNORM, 0),
331 _(L8A8_UNORM, A8L8, T, T, T, T, X, X, X, W, UNORM, 0),
332 _(L8A8_SRGB, A8L8, T, T, T, T, X, X, X, W, UNORM, SRGB),
333
334 _(DXT1_RGB, DXT1, T, T, T, 1, X, Y, Z, W, UNORM, 0),
335 _(DXT1_SRGB, DXT1, T, T, T, 1, X, Y, Z, W, UNORM, SRGB),
336 _(DXT1_RGBA, DXT1, T, T, T, T, X, Y, Z, W, UNORM, 0),
337 _(DXT1_SRGBA, DXT1, T, T, T, T, X, Y, Z, W, UNORM, SRGB),
338 _(DXT3_RGBA, DXT3, T, T, T, T, X, Y, Z, W, UNORM, 0),
339 _(DXT3_SRGBA, DXT3, T, T, T, T, X, Y, Z, W, UNORM, SRGB),
340 _(DXT5_RGBA, DXT5, T, T, T, T, X, Y, Z, W, UNORM, 0),
341 _(DXT5_SRGBA, DXT5, T, T, T, T, X, Y, Z, W, UNORM, SRGB),
342
343 __(Z16_UNORM, A8L8, Z16, T, T, T, 1, W, W, W, W, UNORM, 0),
344 __(S8_UINT_Z24_UNORM,HILO16,Z24, T, T, T, 1, W, W, W, W, UNORM, 0),
345 __(X8Z24_UNORM, HILO16,Z24, T, T, T, 1, W, W, W, W, UNORM, 0),
346
347 _(R16_UNORM, A16, T, 0, 0, 1, X, X, X, X, UNORM, 0),
348 _(R16_SNORM, A16, T, 0, 0, 1, X, X, X, X, SNORM, 0),
349 _(R16G16_UNORM, HILO16, T, T, 0, 1, X, Y, X, X, UNORM, 0),
350 _(R16G16_SNORM, HILO16, T, T, 0, 1, X, Y, X, X, SNORM, 0),
351
352 _(R16G16B16A16_FLOAT, RGBA16F, T, T, T, T, X, Y, Z, W, UNORM, 0),
353 _(R32G32B32A32_FLOAT, RGBA32F, T, T, T, T, X, Y, Z, W, UNORM, 0),
354 _(R32_FLOAT, R32F, T, 0, 0, 1, X, X, X, X, UNORM, 0)
355};
diff --git a/src/gallium/drivers/nvfx/nvfx_miptree.c b/src/gallium/drivers/nvfx/nvfx_miptree.c
deleted file mode 100644
index dd9ad350089..00000000000
--- a/src/gallium/drivers/nvfx/nvfx_miptree.c
+++ /dev/null
@@ -1,214 +0,0 @@
1#include "pipe/p_state.h"
2#include "pipe/p_defines.h"
3#include "util/u_inlines.h"
4#include "util/u_format.h"
5#include "util/u_memory.h"
6#include "util/u_math.h"
7#include "util/u_staging.h"
8#include "state_tracker/drm_driver.h"
9#include "nouveau/nouveau_winsys.h"
10#include "nouveau/nouveau_screen.h"
11#include "nvfx_screen.h"
12#include "nvfx_resource.h"
13
14static void
15nvfx_miptree_choose_format(struct nvfx_miptree *mt)
16{
17 struct pipe_resource *pt = &mt->base.base;
18 unsigned uniform_pitch = 0;
19 static int no_swizzle = -1;
20 if(no_swizzle < 0)
21 no_swizzle = debug_get_bool_option("NV40_NO_SWIZZLE", FALSE); /* this will break things on nv30 */
22
23 if (!util_is_power_of_two(pt->width0) ||
24 !util_is_power_of_two(pt->height0) ||
25 !util_is_power_of_two(pt->depth0) ||
26 (!nvfx_screen(pt->screen)->is_nv4x && pt->target == PIPE_TEXTURE_RECT)
27 )
28 uniform_pitch = 1;
29
30 if (
31 (pt->bind & (PIPE_BIND_SCANOUT | PIPE_BIND_DISPLAY_TARGET))
32 || (pt->usage & PIPE_USAGE_DYNAMIC) || (pt->usage & PIPE_USAGE_STAGING)
33 || util_format_is_compressed(pt->format)
34 || no_swizzle
35 )
36 mt->base.base.flags |= NOUVEAU_RESOURCE_FLAG_LINEAR;
37
38 /* non compressed formats with uniform pitch must be linear, and vice versa */
39 if(!util_format_is_s3tc(pt->format)
40 && (uniform_pitch || mt->base.base.flags & NOUVEAU_RESOURCE_FLAG_LINEAR))
41 {
42 mt->base.base.flags |= NOUVEAU_RESOURCE_FLAG_LINEAR;
43 uniform_pitch = 1;
44 }
45
46 if(uniform_pitch)
47 {
48 mt->linear_pitch = util_format_get_stride(pt->format, pt->width0);
49
50 // TODO: this is only a constraint for rendering and not sampling, apparently
51 // we may also want this unconditionally
52 if(pt->bind & (PIPE_BIND_SAMPLER_VIEW |
53 PIPE_BIND_DEPTH_STENCIL |
54 PIPE_BIND_RENDER_TARGET |
55 PIPE_BIND_DISPLAY_TARGET |
56 PIPE_BIND_SCANOUT))
57 mt->linear_pitch = align(mt->linear_pitch, 64);
58 }
59 else
60 mt->linear_pitch = 0;
61}
62
63static unsigned
64nvfx_miptree_layout(struct nvfx_miptree *mt)
65{
66 struct pipe_resource* pt = &mt->base.base;
67 uint offset = 0;
68
69 if(!nvfx_screen(pt->screen)->is_nv4x)
70 {
71 assert(pt->target == PIPE_TEXTURE_RECT
72 || (util_is_power_of_two(pt->width0) && util_is_power_of_two(pt->height0)));
73 }
74
75 for (unsigned l = 0; l <= pt->last_level; l++)
76 {
77 unsigned size;
78 mt->level_offset[l] = offset;
79
80 if(mt->linear_pitch)
81 size = mt->linear_pitch;
82 else
83 size = util_format_get_stride(pt->format, u_minify(pt->width0, l));
84 size = util_format_get_2d_size(pt->format, size, u_minify(pt->height0, l));
85
86 if(pt->target == PIPE_TEXTURE_3D)
87 size *= u_minify(pt->depth0, l);
88
89 offset += size;
90 }
91
92 offset = align(offset, 128);
93 mt->face_size = offset;
94 if(mt->base.base.target == PIPE_TEXTURE_CUBE)
95 offset += 5 * mt->face_size;
96 return offset;
97}
98
99static void
100nvfx_miptree_surface_final_destroy(struct pipe_surface* ps)
101{
102 pipe_resource_reference(&ps->texture, 0);
103 FREE(ps);
104}
105
106void
107nvfx_miptree_destroy(struct pipe_screen *screen, struct pipe_resource *pt)
108{
109 struct nvfx_miptree *mt = (struct nvfx_miptree *)pt;
110 util_surfaces_destroy(&mt->surfaces, pt, nvfx_miptree_surface_final_destroy);
111 nouveau_screen_bo_release(screen, mt->base.bo);
112 FREE(mt);
113}
114
115static struct nvfx_miptree*
116nvfx_miptree_create_skeleton(struct pipe_screen *pscreen, const struct pipe_resource *pt)
117{
118 struct nvfx_miptree *mt;
119
120 if(pt->width0 > 4096 || pt->height0 > 4096)
121 return NULL;
122
123 mt = CALLOC_STRUCT(nvfx_miptree);
124 if (!mt)
125 return NULL;
126
127 mt->base.base = *pt;
128
129 pipe_reference_init(&mt->base.base.reference, 1);
130 mt->base.base.screen = pscreen;
131
132 // set this to the actual capabilities, we use it to decide whether to use the 3D engine for copies
133 // TODO: is this the correct way to use Gallium?
134 mt->base.base.bind = pt->bind | PIPE_BIND_RENDER_TARGET | PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_DEPTH_STENCIL;
135
136 // on our current driver (and the driver too), format support does not depend on geometry, so don't bother computing it
137 // TODO: may want to revisit this
138 if(!pscreen->is_format_supported(pscreen, pt->format, pt->target, 0, PIPE_BIND_RENDER_TARGET))
139 mt->base.base.bind &=~ PIPE_BIND_RENDER_TARGET;
140 if(!pscreen->is_format_supported(pscreen, pt->format, pt->target, 0, PIPE_BIND_SAMPLER_VIEW))
141 mt->base.base.bind &=~ PIPE_BIND_SAMPLER_VIEW;
142 if(!pscreen->is_format_supported(pscreen, pt->format, pt->target, 0, PIPE_BIND_DEPTH_STENCIL))
143 mt->base.base.bind &=~ PIPE_BIND_DEPTH_STENCIL;
144
145 return mt;
146}
147
148
149struct pipe_resource *
150nvfx_miptree_create(struct pipe_screen *pscreen, const struct pipe_resource *pt)
151{
152 struct nvfx_miptree* mt = nvfx_miptree_create_skeleton(pscreen, pt);
153 unsigned size;
154 nvfx_miptree_choose_format(mt);
155
156 size = nvfx_miptree_layout(mt);
157
158 mt->base.bo = nouveau_screen_bo_new(pscreen, 256, pt->usage, pt->bind, size);
159
160 if (!mt->base.bo) {
161 FREE(mt);
162 return NULL;
163 }
164 return &mt->base.base;
165}
166
167// TODO: redo this, just calling miptree_layout
168struct pipe_resource *
169nvfx_miptree_from_handle(struct pipe_screen *pscreen, const struct pipe_resource *template, struct winsys_handle *whandle)
170{
171 struct nvfx_miptree* mt = nvfx_miptree_create_skeleton(pscreen, template);
172 unsigned stride;
173 if(whandle->stride) {
174 mt->linear_pitch = whandle->stride;
175 mt->base.base.flags |= NOUVEAU_RESOURCE_FLAG_LINEAR;
176 } else
177 nvfx_miptree_choose_format(mt);
178
179 nvfx_miptree_layout(mt);
180
181 mt->base.bo = nouveau_screen_bo_from_handle(pscreen, whandle, &stride);
182 if (mt->base.bo == NULL) {
183 FREE(mt);
184 return NULL;
185 }
186 return &mt->base.base;
187}
188
189struct pipe_surface *
190nvfx_miptree_surface_new(struct pipe_context *pipe, struct pipe_resource *pt,
191 const struct pipe_surface *surf_tmpl)
192{
193 struct nvfx_miptree *mt = (struct nvfx_miptree *)pt;
194 unsigned level = surf_tmpl->u.tex.level;
195 struct nvfx_surface *ns = NULL;
196
197 assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
198 if(util_surfaces_get(&mt->surfaces, sizeof(struct nvfx_surface), pipe,
199 pt, level, surf_tmpl->u.tex.first_layer,
200 surf_tmpl->usage, (struct pipe_surface **)&ns)) {
201 ns->pitch = nvfx_subresource_pitch(pt, level);
202 ns->offset = nvfx_subresource_offset(pt, surf_tmpl->u.tex.first_layer, level, surf_tmpl->u.tex.first_layer);
203 }
204
205 return &ns->base;
206}
207
208void
209nvfx_miptree_surface_del(struct pipe_context *pipe, struct pipe_surface *ps)
210{
211 util_surfaces_detach(&((struct nvfx_miptree*)ps->texture)->surfaces, ps);
212 pipe_resource_reference(&ps->texture, 0);
213 FREE(ps);
214}
diff --git a/src/gallium/drivers/nvfx/nvfx_push.c b/src/gallium/drivers/nvfx/nvfx_push.c
deleted file mode 100644
index 6391741a2e5..00000000000
--- a/src/gallium/drivers/nvfx/nvfx_push.c
+++ /dev/null
@@ -1,431 +0,0 @@
1#include "pipe/p_context.h"
2#include "pipe/p_state.h"
3#include "util/u_inlines.h"
4#include "util/u_format.h"
5#include "util/u_split_prim.h"
6#include "translate/translate.h"
7
8#include "nvfx_context.h"
9#include "nvfx_resource.h"
10
11struct push_context {
12 struct nouveau_channel* chan;
13 struct nouveau_grobj *eng3d;
14
15 void *idxbuf;
16 int32_t idxbias;
17
18 float edgeflag;
19 int edgeflag_attr;
20
21 unsigned vertex_length;
22 unsigned max_vertices_per_packet;
23
24 struct translate* translate;
25};
26
27static void
28emit_edgeflag(void *priv, boolean enabled)
29{
30 struct push_context* ctx = priv;
31 struct nouveau_grobj *eng3d = ctx->eng3d;
32 struct nouveau_channel *chan = ctx->chan;
33
34 BEGIN_RING(chan, eng3d, NV30_3D_EDGEFLAG, 1);
35 OUT_RING(chan, enabled ? 1 : 0);
36}
37
38static void
39emit_vertices_lookup8(void *priv, unsigned start, unsigned count)
40{
41 struct push_context *ctx = priv;
42 struct nouveau_grobj *eng3d = ctx->eng3d;
43 uint8_t* elts = (uint8_t*)ctx->idxbuf + start;
44
45 while(count)
46 {
47 unsigned push = MIN2(count, ctx->max_vertices_per_packet);
48 unsigned length = push * ctx->vertex_length;
49
50 BEGIN_RING_NI(ctx->chan, eng3d, NV30_3D_VERTEX_DATA, length);
51 ctx->translate->run_elts8(ctx->translate, elts, push, 0, ctx->chan->cur);
52 ctx->chan->cur += length;
53
54 count -= push;
55 elts += push;
56 }
57}
58
59static void
60emit_vertices_lookup16(void *priv, unsigned start, unsigned count)
61{
62 struct push_context *ctx = priv;
63 struct nouveau_grobj *eng3d = ctx->eng3d;
64 uint16_t* elts = (uint16_t*)ctx->idxbuf + start;
65
66 while(count)
67 {
68 unsigned push = MIN2(count, ctx->max_vertices_per_packet);
69 unsigned length = push * ctx->vertex_length;
70
71 BEGIN_RING_NI(ctx->chan, eng3d, NV30_3D_VERTEX_DATA, length);
72 ctx->translate->run_elts16(ctx->translate, elts, push, 0, ctx->chan->cur);
73 ctx->chan->cur += length;
74
75 count -= push;
76 elts += push;
77 }
78}
79
80static void
81emit_vertices_lookup32(void *priv, unsigned start, unsigned count)
82{
83 struct push_context *ctx = priv;
84 struct nouveau_grobj *eng3d = ctx->eng3d;
85 uint32_t* elts = (uint32_t*)ctx->idxbuf + start;
86
87 while(count)
88 {
89 unsigned push = MIN2(count, ctx->max_vertices_per_packet);
90 unsigned length = push * ctx->vertex_length;
91
92 BEGIN_RING_NI(ctx->chan, eng3d, NV30_3D_VERTEX_DATA, length);
93 ctx->translate->run_elts(ctx->translate, elts, push, 0, ctx->chan->cur);
94 ctx->chan->cur += length;
95
96 count -= push;
97 elts += push;
98 }
99}
100
101static void
102emit_vertices(void *priv, unsigned start, unsigned count)
103{
104 struct push_context *ctx = priv;
105 struct nouveau_grobj *eng3d = ctx->eng3d;
106
107 while(count)
108 {
109 unsigned push = MIN2(count, ctx->max_vertices_per_packet);
110 unsigned length = push * ctx->vertex_length;
111
112 BEGIN_RING_NI(ctx->chan, eng3d, NV30_3D_VERTEX_DATA, length);
113 ctx->translate->run(ctx->translate, start, push, 0, ctx->chan->cur);
114 ctx->chan->cur += length;
115
116 count -= push;
117 start += push;
118 }
119}
120
121static void
122emit_ranges(void* priv, unsigned start, unsigned vc, unsigned reg)
123{
124 struct push_context* ctx = priv;
125 struct nouveau_grobj *eng3d = ctx->eng3d;
126 struct nouveau_channel *chan = ctx->chan;
127 unsigned nr = (vc & 0xff);
128 if (nr) {
129 BEGIN_RING(chan, eng3d, reg, 1);
130 OUT_RING (chan, ((nr - 1) << 24) | start);
131 start += nr;
132 }
133
134 nr = vc >> 8;
135 while (nr) {
136 unsigned push = nr > 2047 ? 2047 : nr;
137
138 nr -= push;
139
140 BEGIN_RING_NI(chan, eng3d, reg, push);
141 while (push--) {
142 OUT_RING(chan, ((0x100 - 1) << 24) | start);
143 start += 0x100;
144 }
145 }
146}
147
148static void
149emit_ib_ranges(void* priv, unsigned start, unsigned vc)
150{
151 emit_ranges(priv, start, vc, NV30_3D_VB_INDEX_BATCH);
152}
153
154static void
155emit_vb_ranges(void* priv, unsigned start, unsigned vc)
156{
157 emit_ranges(priv, start, vc, NV30_3D_VB_VERTEX_BATCH);
158}
159
160static INLINE void
161emit_elt8(void* priv, unsigned start, unsigned vc)
162{
163 struct push_context* ctx = priv;
164 struct nouveau_grobj *eng3d = ctx->eng3d;
165 struct nouveau_channel *chan = ctx->chan;
166 uint8_t *elts = (uint8_t *)ctx->idxbuf + start;
167 int idxbias = ctx->idxbias;
168
169 if (vc & 1) {
170 BEGIN_RING(chan, eng3d, NV30_3D_VB_ELEMENT_U32, 1);
171 OUT_RING (chan, elts[0]);
172 elts++; vc--;
173 }
174
175 while (vc) {
176 unsigned i;
177 unsigned push = MIN2(vc, 2047 * 2);
178
179 BEGIN_RING_NI(chan, eng3d, NV30_3D_VB_ELEMENT_U16, push >> 1);
180 for (i = 0; i < push; i+=2)
181 OUT_RING(chan, ((elts[i+1] + idxbias) << 16) | (elts[i] + idxbias));
182
183 vc -= push;
184 elts += push;
185 }
186}
187
188static INLINE void
189emit_elt16(void* priv, unsigned start, unsigned vc)
190{
191 struct push_context* ctx = priv;
192 struct nouveau_grobj *eng3d = ctx->eng3d;
193 struct nouveau_channel *chan = ctx->chan;
194 uint16_t *elts = (uint16_t *)ctx->idxbuf + start;
195 int idxbias = ctx->idxbias;
196
197 if (vc & 1) {
198 BEGIN_RING(chan, eng3d, NV30_3D_VB_ELEMENT_U32, 1);
199 OUT_RING (chan, elts[0]);
200 elts++; vc--;
201 }
202
203 while (vc) {
204 unsigned i;
205 unsigned push = MIN2(vc, 2047 * 2);
206
207 BEGIN_RING_NI(chan, eng3d, NV30_3D_VB_ELEMENT_U16, push >> 1);
208 for (i = 0; i < push; i+=2)
209 OUT_RING(chan, ((elts[i+1] + idxbias) << 16) | (elts[i] + idxbias));
210
211 vc -= push;
212 elts += push;
213 }
214}
215
216static INLINE void
217emit_elt32(void* priv, unsigned start, unsigned vc)
218{
219 struct push_context* ctx = priv;
220 struct nouveau_grobj *eng3d = ctx->eng3d;
221 struct nouveau_channel *chan = ctx->chan;
222 uint32_t *elts = (uint32_t *)ctx->idxbuf + start;
223 int idxbias = ctx->idxbias;
224
225 while (vc) {
226 unsigned push = MIN2(vc, 2047);
227
228 BEGIN_RING_NI(chan, eng3d, NV30_3D_VB_ELEMENT_U32, push);
229 if(idxbias)
230 {
231 for(unsigned i = 0; i < push; ++i)
232 OUT_RING(chan, elts[i] + idxbias);
233 }
234 else
235 OUT_RINGp(chan, elts, push);
236
237 vc -= push;
238 elts += push;
239 }
240}
241
242void
243nvfx_push_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
244{
245 struct nvfx_context *nvfx = nvfx_context(pipe);
246 struct nouveau_channel *chan = nvfx->screen->base.channel;
247 struct nouveau_grobj *eng3d = nvfx->screen->eng3d;
248 struct push_context ctx;
249 struct util_split_prim s;
250 unsigned instances_left = info->instance_count;
251 int vtx_value;
252 unsigned hw_mode = nvgl_primitive(info->mode);
253 int i;
254 struct
255 {
256 uint8_t* map;
257 unsigned step;
258 } per_instance[16];
259 unsigned p_overhead = 64 /* magic fix */
260 + 4 /* begin/end */
261 + 4; /* potential edgeflag enable/disable */
262
263 ctx.chan = nvfx->screen->base.channel;
264 ctx.eng3d = nvfx->screen->eng3d;
265 ctx.translate = nvfx->vtxelt->translate;
266 ctx.idxbuf = NULL;
267 ctx.vertex_length = nvfx->vtxelt->vertex_length;
268 ctx.max_vertices_per_packet = nvfx->vtxelt->max_vertices_per_packet;
269 ctx.edgeflag = 0.5f;
270 // TODO: figure out if we really want to handle this, and do so in that case
271 ctx.edgeflag_attr = 0xff; // nvfx->vertprog->cfg.edgeflag_in;
272
273 if(!nvfx->use_vertex_buffers)
274 {
275 for(i = 0; i < nvfx->vtxelt->num_per_vertex_buffer_infos; ++i)
276 {
277 struct nvfx_per_vertex_buffer_info* vbi = &nvfx->vtxelt->per_vertex_buffer_info[i];
278 struct pipe_vertex_buffer *vb = &nvfx->vtxbuf[vbi->vertex_buffer_index];
279 uint8_t* data = nvfx_buffer(vb->buffer)->data + vb->buffer_offset;
280 if(info->indexed)
281 data += info->index_bias * vb->stride;
282 ctx.translate->set_buffer(ctx.translate, i, data, vb->stride, ~0);
283 }
284
285 if(ctx.edgeflag_attr < 16)
286 vtx_value = -(ctx.vertex_length + 3); /* vertex data and edgeflag header and value */
287 else
288 {
289 p_overhead += 1; /* initial vertex_data header */
290 vtx_value = -ctx.vertex_length; /* vertex data and edgeflag header and value */
291 }
292
293 if (info->indexed) {
294 // XXX: this case and is broken and probably need a new VTX_ATTR push path
295 if (nvfx->idxbuf.index_size == 1)
296 s.emit = emit_vertices_lookup8;
297 else if (nvfx->idxbuf.index_size == 2)
298 s.emit = emit_vertices_lookup16;
299 else
300 s.emit = emit_vertices_lookup32;
301 } else
302 s.emit = emit_vertices;
303 }
304 else
305 {
306 if(!info->indexed || nvfx->use_index_buffer)
307 {
308 s.emit = info->indexed ? emit_ib_ranges : emit_vb_ranges;
309 p_overhead += 3;
310 vtx_value = 0;
311 }
312 else if (nvfx->idxbuf.index_size == 4)
313 {
314 s.emit = emit_elt32;
315 p_overhead += 1;
316 vtx_value = 8;
317 }
318 else
319 {
320 s.emit = (nvfx->idxbuf.index_size == 2) ? emit_elt16 : emit_elt8;
321 p_overhead += 3;
322 vtx_value = 7;
323 }
324 }
325
326 ctx.idxbias = info->index_bias;
327 if(nvfx->use_vertex_buffers)
328 ctx.idxbias -= nvfx->base_vertex;
329
330 /* map index buffer, if present */
331 if (info->indexed && !nvfx->use_index_buffer)
332 ctx.idxbuf = nvfx_buffer(nvfx->idxbuf.buffer)->data + nvfx->idxbuf.offset;
333
334 s.priv = &ctx;
335 s.edge = emit_edgeflag;
336
337 for (i = 0; i < nvfx->vtxelt->num_per_instance; ++i)
338 {
339 struct nvfx_per_instance_element *ve = &nvfx->vtxelt->per_instance[i];
340 struct pipe_vertex_buffer *vb = &nvfx->vtxbuf[ve->base.vertex_buffer_index];
341 float v[4];
342 per_instance[i].step = info->start_instance % ve->instance_divisor;
343 per_instance[i].map = nvfx_buffer(vb->buffer)->data + vb->buffer_offset + ve->base.src_offset;
344
345 nvfx->vtxelt->per_instance[i].base.fetch_rgba_float(v, per_instance[i].map, 0, 0);
346
347 nvfx_emit_vtx_attr(chan, eng3d,
348 nvfx->vtxelt->per_instance[i].base.idx, v,
349 nvfx->vtxelt->per_instance[i].base.ncomp);
350 }
351
352 /* per-instance loop */
353 while (instances_left--) {
354 int max_verts;
355 boolean done;
356
357 util_split_prim_init(&s, info->mode, info->start, info->count);
358 nvfx_state_emit(nvfx);
359 for(;;) {
360 max_verts = AVAIL_RING(chan);
361 max_verts -= p_overhead;
362
363 /* if vtx_value < 0, each vertex is -vtx_value words long
364 * otherwise, each vertex is 2^(vtx_value) / 255 words long (this is an approximation)
365 */
366 if(vtx_value < 0)
367 {
368 max_verts /= -vtx_value;
369 max_verts -= (max_verts >> 10); /* vertex data headers */
370 }
371 else
372 {
373 if(max_verts >= (1 << 23)) /* avoid overflow here */
374 max_verts = (1 << 23);
375 max_verts = (max_verts * 255) >> vtx_value;
376 }
377
378 //printf("avail %u max_verts %u\n", AVAIL_RING(chan), max_verts);
379
380 if(max_verts >= 16)
381 {
382 /* XXX: any command a lot of times seems to (mostly) fix corruption that would otherwise happen */
383 /* this seems to cause issues on nv3x, and also be unneeded there */
384 if(nvfx->is_nv4x)
385 {
386 int i;
387 for(i = 0; i < 32; ++i)
388 {
389 BEGIN_RING(chan, eng3d,
390 0x1dac, 1);
391 OUT_RING(chan, 0);
392 }
393 }
394
395 BEGIN_RING(chan, eng3d,
396 NV30_3D_VERTEX_BEGIN_END, 1);
397 OUT_RING(chan, hw_mode);
398 done = util_split_prim_next(&s, max_verts);
399 BEGIN_RING(chan, eng3d,
400 NV30_3D_VERTEX_BEGIN_END, 1);
401 OUT_RING(chan, 0);
402
403 if(done)
404 break;
405 }
406
407 FIRE_RING(chan);
408 nvfx_state_emit(nvfx);
409 }
410
411 /* set data for the next instance, if any changed */
412 for (i = 0; i < nvfx->vtxelt->num_per_instance; ++i)
413 {
414 struct nvfx_per_instance_element *ve = &nvfx->vtxelt->per_instance[i];
415 struct pipe_vertex_buffer *vb = &nvfx->vtxbuf[ve->base.vertex_buffer_index];
416
417 if(++per_instance[i].step == ve->instance_divisor)
418 {
419 float v[4];
420 per_instance[i].map += vb->stride;
421 per_instance[i].step = 0;
422
423 nvfx->vtxelt->per_instance[i].base.fetch_rgba_float(v, per_instance[i].map, 0, 0);
424 nvfx_emit_vtx_attr(chan, eng3d,
425 nvfx->vtxelt->per_instance[i].base.idx,
426 v,
427 nvfx->vtxelt->per_instance[i].base.ncomp);
428 }
429 }
430 }
431}
diff --git a/src/gallium/drivers/nvfx/nvfx_query.c b/src/gallium/drivers/nvfx/nvfx_query.c
deleted file mode 100644
index 76fb715b830..00000000000
--- a/src/gallium/drivers/nvfx/nvfx_query.c
+++ /dev/null
@@ -1,147 +0,0 @@
1#include "pipe/p_context.h"
2
3#include "nvfx_context.h"
4
5struct nvfx_query {
6 struct list_head list;
7 struct nouveau_resource *object;
8 unsigned type;
9 boolean ready;
10 uint64_t result;
11};
12
13static INLINE struct nvfx_query *
14nvfx_query(struct pipe_query *pipe)
15{
16 return (struct nvfx_query *)pipe;
17}
18
19static struct pipe_query *
20nvfx_query_create(struct pipe_context *pipe, unsigned query_type)
21{
22 struct nvfx_query *q;
23
24 q = CALLOC(1, sizeof(struct nvfx_query));
25 q->type = query_type;
26
27 assert(q->type == PIPE_QUERY_OCCLUSION_COUNTER);
28
29 return (struct pipe_query *)q;
30}
31
32static void
33nvfx_query_destroy(struct pipe_context *pipe, struct pipe_query *pq)
34{
35 struct nvfx_query *q = nvfx_query(pq);
36
37 if (q->object)
38 {
39 nouveau_resource_free(&q->object);
40 LIST_DEL(&q->list);
41 }
42 FREE(q);
43}
44
45static void
46nvfx_query_begin(struct pipe_context *pipe, struct pipe_query *pq)
47{
48 struct nvfx_context *nvfx = nvfx_context(pipe);
49 struct nvfx_query *q = nvfx_query(pq);
50 struct nvfx_screen *screen = nvfx->screen;
51 struct nouveau_channel *chan = screen->base.channel;
52 struct nouveau_grobj *eng3d = screen->eng3d;
53 uint64_t tmp;
54
55 assert(!nvfx->query);
56
57 /* Happens when end_query() is called, then another begin_query()
58 * without querying the result in-between. For now we'll wait for
59 * the existing query to notify completion, but it could be better.
60 */
61 if (q->object)
62 pipe->get_query_result(pipe, pq, 1, (void*)&tmp);
63
64 while (nouveau_resource_alloc(nvfx->screen->query_heap, 1, NULL, &q->object))
65 {
66 struct nvfx_query* oldestq;
67 assert(!LIST_IS_EMPTY(&nvfx->screen->query_list));
68 oldestq = LIST_ENTRY(struct nvfx_query, nvfx->screen->query_list.next, list);
69 pipe->get_query_result(pipe, (struct pipe_query*)oldestq, 1, (void*)&tmp);
70 }
71
72 LIST_ADDTAIL(&q->list, &nvfx->screen->query_list);
73
74 nouveau_notifier_reset(nvfx->screen->query, q->object->start);
75
76 BEGIN_RING(chan, eng3d, NV30_3D_QUERY_RESET, 1);
77 OUT_RING(chan, 1);
78 BEGIN_RING(chan, eng3d, NV30_3D_QUERY_ENABLE, 1);
79 OUT_RING(chan, 1);
80
81 q->ready = FALSE;
82
83 nvfx->query = pq;
84}
85
86static void
87nvfx_query_end(struct pipe_context *pipe, struct pipe_query *pq)
88{
89 struct nvfx_context *nvfx = nvfx_context(pipe);
90 struct nouveau_channel *chan = nvfx->screen->base.channel;
91 struct nouveau_grobj *eng3d = nvfx->screen->eng3d;
92 struct nvfx_query *q = nvfx_query(pq);
93
94 assert(nvfx->query == pq);
95
96 BEGIN_RING(chan, eng3d, NV30_3D_QUERY_GET, 1);
97 OUT_RING (chan, (0x01 << NV30_3D_QUERY_GET_UNK24__SHIFT) |
98 ((q->object->start * 32) << NV30_3D_QUERY_GET_OFFSET__SHIFT));
99 BEGIN_RING(chan, eng3d, NV30_3D_QUERY_ENABLE, 1);
100 OUT_RING(chan, 0);
101 FIRE_RING(chan);
102
103 nvfx->query = 0;
104}
105
106static boolean
107nvfx_query_result(struct pipe_context *pipe, struct pipe_query *pq,
108 boolean wait, union pipe_query_result *vresult)
109{
110 uint64_t *result = (uint64_t *)vresult;
111 struct nvfx_context *nvfx = nvfx_context(pipe);
112 struct nvfx_query *q = nvfx_query(pq);
113
114 if (!q->ready) {
115 unsigned status;
116
117 status = nouveau_notifier_status(nvfx->screen->query,
118 q->object->start);
119 if (status != NV_NOTIFY_STATE_STATUS_COMPLETED) {
120 if (wait == FALSE)
121 return FALSE;
122
123 nouveau_notifier_wait_status(nvfx->screen->query,
124 q->object->start,
125 NV_NOTIFY_STATE_STATUS_COMPLETED, 0);
126 }
127
128 q->result = nouveau_notifier_return_val(nvfx->screen->query,
129 q->object->start);
130 q->ready = TRUE;
131 nouveau_resource_free(&q->object);
132 LIST_DEL(&q->list);
133 }
134
135 *result = q->result;
136 return TRUE;
137}
138
139void
140nvfx_init_query_functions(struct nvfx_context *nvfx)
141{
142 nvfx->pipe.create_query = nvfx_query_create;
143 nvfx->pipe.destroy_query = nvfx_query_destroy;
144 nvfx->pipe.begin_query = nvfx_query_begin;
145 nvfx->pipe.end_query = nvfx_query_end;
146 nvfx->pipe.get_query_result = nvfx_query_result;
147}
diff --git a/src/gallium/drivers/nvfx/nvfx_resource.c b/src/gallium/drivers/nvfx/nvfx_resource.c
deleted file mode 100644
index 42e77c53621..00000000000
--- a/src/gallium/drivers/nvfx/nvfx_resource.c
+++ /dev/null
@@ -1,66 +0,0 @@
1
2#include "pipe/p_context.h"
3#include "util/u_staging.h"
4#include "nvfx_resource.h"
5#include "nouveau/nouveau_screen.h"
6
7
8static struct pipe_resource *
9nvfx_resource_create(struct pipe_screen *screen,
10 const struct pipe_resource *template)
11{
12 if (template->target == PIPE_BUFFER)
13 return nvfx_buffer_create(screen, template);
14 else
15 return nvfx_miptree_create(screen, template);
16}
17
18static void
19nvfx_resource_destroy(struct pipe_screen *screen, struct pipe_resource *pr)
20{
21 if (pr->target == PIPE_BUFFER)
22 return nvfx_buffer_destroy(screen, pr);
23 else
24 return nvfx_miptree_destroy(screen, pr);
25}
26
27static struct pipe_resource *
28nvfx_resource_from_handle(struct pipe_screen * screen,
29 const struct pipe_resource *template,
30 struct winsys_handle *whandle)
31{
32 if (template->target == PIPE_BUFFER)
33 return NULL;
34 else
35 return nvfx_miptree_from_handle(screen, template, whandle);
36}
37
38static boolean
39nvfx_resource_get_handle(struct pipe_screen *pscreen,
40 struct pipe_resource *pr,
41 struct winsys_handle *whandle)
42{
43 struct nvfx_resource* res = (struct nvfx_resource*)pr;
44
45 if (!res || !res->bo)
46 return FALSE;
47
48 return nouveau_screen_bo_get_handle(pscreen, res->bo, nvfx_subresource_pitch(pr, 0), whandle);
49}
50
51void
52nvfx_init_resource_functions(struct pipe_context *pipe)
53{
54 pipe->create_surface = nvfx_miptree_surface_new;
55 pipe->surface_destroy = nvfx_miptree_surface_del;
56}
57
58void
59nvfx_screen_init_resource_functions(struct pipe_screen *pscreen)
60{
61 pscreen->resource_create = nvfx_resource_create;
62 pscreen->resource_from_handle = nvfx_resource_from_handle;
63 pscreen->resource_get_handle = nvfx_resource_get_handle;
64 pscreen->resource_destroy = nvfx_resource_destroy;
65 pscreen->user_buffer_create = nvfx_user_buffer_create;
66}
diff --git a/src/gallium/drivers/nvfx/nvfx_resource.h b/src/gallium/drivers/nvfx/nvfx_resource.h
deleted file mode 100644
index 4a663583b46..00000000000
--- a/src/gallium/drivers/nvfx/nvfx_resource.h
+++ /dev/null
@@ -1,194 +0,0 @@
1#ifndef NVFX_RESOURCE_H
2#define NVFX_RESOURCE_H
3
4#include "util/u_transfer.h"
5#include "util/u_format.h"
6#include "util/u_math.h"
7#include "util/u_double_list.h"
8#include "util/u_surfaces.h"
9#include "util/u_dirty_surfaces.h"
10#include <nouveau/nouveau_bo.h>
11
12struct pipe_resource;
13struct nv04_region;
14
15struct nvfx_resource {
16 struct pipe_resource base;
17 struct nouveau_bo *bo;
18};
19
20static INLINE
21struct nvfx_resource *nvfx_resource(struct pipe_resource *resource)
22{
23 return (struct nvfx_resource *)resource;
24}
25
26#define NVFX_RESOURCE_FLAG_USER (NOUVEAU_RESOURCE_FLAG_DRV_PRIV << 0)
27
28/* is resource mapped into the GPU's address space (i.e. VRAM or GART) ? */
29static INLINE boolean
30nvfx_resource_mapped_by_gpu(struct pipe_resource *resource)
31{
32 return nvfx_resource(resource)->bo->handle;
33}
34
35/* is resource in VRAM? */
36static inline int
37nvfx_resource_on_gpu(struct pipe_resource* pr)
38{
39#if 0
40 // a compiler error here means you need to apply libdrm-nouveau-add-domain.patch to libdrm
41 // TODO: return FALSE if not VRAM and on a PCI-E system
42 return ((struct nvfx_resource*)pr)->bo->domain & (NOUVEAU_BO_VRAM | NOUVEAU_BO_GART);
43#else
44 return TRUE;
45#endif
46}
47
48#define NVFX_MAX_TEXTURE_LEVELS 16
49
50struct nvfx_miptree {
51 struct nvfx_resource base;
52
53 unsigned linear_pitch; /* for linear textures, 0 for swizzled and compressed textures with level-dependent minimal pitch */
54 unsigned face_size; /* 128-byte aligned face/total size */
55 unsigned level_offset[NVFX_MAX_TEXTURE_LEVELS];
56
57 struct util_surfaces surfaces;
58};
59
60struct nvfx_surface {
61 struct pipe_surface base;
62 unsigned pitch;
63 unsigned offset;
64};
65
66static INLINE struct nouveau_bo *
67nvfx_surface_buffer(struct pipe_surface *surf)
68{
69 struct nvfx_resource *mt = nvfx_resource(surf->texture);
70
71 return mt->bo;
72}
73
74void
75nvfx_init_resource_functions(struct pipe_context *pipe);
76
77void
78nvfx_screen_init_resource_functions(struct pipe_screen *pscreen);
79
80
81/* Internal:
82 */
83
84struct pipe_resource *
85nvfx_miptree_create(struct pipe_screen *pscreen, const struct pipe_resource *pt);
86
87void
88nvfx_miptree_destroy(struct pipe_screen *pscreen,
89 struct pipe_resource *presource);
90
91struct pipe_resource *
92nvfx_miptree_from_handle(struct pipe_screen *pscreen,
93 const struct pipe_resource *template,
94 struct winsys_handle *whandle);
95
96void
97nvfx_miptree_surface_del(struct pipe_context *pipe, struct pipe_surface *ps);
98
99struct pipe_surface *
100nvfx_miptree_surface_new(struct pipe_context *pipe, struct pipe_resource *pt,
101 const struct pipe_surface *surf_tmpl);
102
103/* only for miptrees, don't use for buffers */
104
105/* NOTE: for swizzled 3D textures, this just returns the offset of the mipmap level */
106static inline unsigned
107nvfx_subresource_offset(struct pipe_resource* pt, unsigned face, unsigned level, unsigned zslice)
108{
109 if(pt->target == PIPE_BUFFER)
110 return 0;
111 else
112 {
113 struct nvfx_miptree *mt = (struct nvfx_miptree *)pt;
114
115 unsigned offset = mt->level_offset[level];
116 if (pt->target == PIPE_TEXTURE_CUBE)
117 offset += mt->face_size * face;
118 else if (pt->target == PIPE_TEXTURE_3D && mt->linear_pitch)
119 offset += zslice * util_format_get_2d_size(pt->format, (mt->linear_pitch ? mt->linear_pitch : util_format_get_stride(pt->format, u_minify(pt->width0, level))), u_minify(pt->height0, level));
120 return offset;
121 }
122}
123
124static inline unsigned
125nvfx_subresource_pitch(struct pipe_resource* pt, unsigned level)
126{
127 if(pt->target == PIPE_BUFFER)
128 return ((struct nvfx_resource*)pt)->bo->size;
129 else
130 {
131 struct nvfx_miptree *mt = (struct nvfx_miptree *)pt;
132
133 if(mt->linear_pitch)
134 return mt->linear_pitch;
135 else
136 return util_format_get_stride(pt->format, u_minify(pt->width0, level));
137 }
138}
139
140struct nvfx_buffer
141{
142 struct nvfx_resource base;
143 uint8_t* data;
144 unsigned size;
145
146 /* the range of data not yet uploaded to the GPU bo */
147 unsigned dirty_begin;
148 unsigned dirty_end;
149
150 /* whether all transfers were unsynchronized */
151 boolean dirty_unsynchronized;
152
153 /* whether it would have been profitable to upload
154 * the latest updated data to the GPU immediately */
155 boolean last_update_static;
156
157 /* how many bytes we need to draw before we deem
158 * the buffer to be static
159 */
160 long long bytes_to_draw_until_static;
161};
162
163static inline struct nvfx_buffer* nvfx_buffer(struct pipe_resource* pr)
164{
165 return (struct nvfx_buffer*)pr;
166}
167
168/* this is an heuristic to determine whether we are better off uploading the
169 * buffer to the GPU, or just continuing pushing it on the FIFO
170 */
171static inline boolean nvfx_buffer_seems_static(struct nvfx_buffer* buffer)
172{
173 return buffer->last_update_static
174 || buffer->bytes_to_draw_until_static < 0;
175}
176
177struct pipe_resource *
178nvfx_buffer_create(struct pipe_screen *pscreen,
179 const struct pipe_resource *template);
180
181void
182nvfx_buffer_destroy(struct pipe_screen *pscreen,
183 struct pipe_resource *presource);
184
185struct pipe_resource *
186nvfx_user_buffer_create(struct pipe_screen *screen,
187 void *ptr,
188 unsigned bytes,
189 unsigned usage);
190
191void
192nvfx_buffer_upload(struct nvfx_buffer* buffer);
193
194#endif
diff --git a/src/gallium/drivers/nvfx/nvfx_screen.c b/src/gallium/drivers/nvfx/nvfx_screen.c
deleted file mode 100644
index 71e7c1591d8..00000000000
--- a/src/gallium/drivers/nvfx/nvfx_screen.c
+++ /dev/null
@@ -1,665 +0,0 @@
1#include "pipe/p_screen.h"
2#include "pipe/p_state.h"
3#include "util/u_format.h"
4#include "util/u_format_s3tc.h"
5#include "vl/vl_decoder.h"
6#include "vl/vl_video_buffer.h"
7
8#include "nouveau/nouveau_screen.h"
9#include "nouveau/nv_object.xml.h"
10#include "nvfx_context.h"
11#include "nvfx_screen.h"
12#include "nvfx_resource.h"
13#include "nvfx_tex.h"
14
15#define NV30_3D_CHIPSET_3X_MASK 0x00000003
16#define NV34_3D_CHIPSET_3X_MASK 0x00000010
17#define NV35_3D_CHIPSET_3X_MASK 0x000001e0
18
19#define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
20#define NV4X_GRCLASS4497_CHIPSETS 0x00005450
21#define NV6X_GRCLASS4497_CHIPSETS 0x00000088
22
23static int
24nvfx_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
25{
26 struct nvfx_screen *screen = nvfx_screen(pscreen);
27
28 switch (param) {
29 case PIPE_CAP_NPOT_TEXTURES:
30 return screen->advertise_npot;
31 case PIPE_CAP_TWO_SIDED_STENCIL:
32 return 1;
33 case PIPE_CAP_SM3:
34 /* TODO: >= nv4x support Shader Model 3.0 */
35 return 0;
36 case PIPE_CAP_GLSL_FEATURE_LEVEL:
37 return 120;
38 case PIPE_CAP_ANISOTROPIC_FILTER:
39 return 1;
40 case PIPE_CAP_POINT_SPRITE:
41 return 1;
42 case PIPE_CAP_MAX_RENDER_TARGETS:
43 return screen->use_nv4x ? 4 : 1;
44 case PIPE_CAP_OCCLUSION_QUERY:
45 return 1;
46 case PIPE_CAP_TIMER_QUERY:
47 return 0;
48 case PIPE_CAP_TEXTURE_SHADOW_MAP:
49 return 1;
50 case PIPE_CAP_TEXTURE_SWIZZLE:
51 return 1;
52 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
53 return 13;
54 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
55 return 10;
56 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
57 return 13;
58 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
59 return !!screen->use_nv4x;
60 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
61 return screen->advertise_blend_equation_separate;
62 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
63 return 16;
64 case PIPE_CAP_INDEP_BLEND_ENABLE:
65 /* TODO: on nv40 we have separate color masks */
66 /* TODO: nv40 mrt blending is probably broken */
67 return 0;
68 case PIPE_CAP_INDEP_BLEND_FUNC:
69 return 0;
70 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
71 return 0;
72 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
73 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
74 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
75 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
76 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
77 return 1;
78 case PIPE_CAP_DEPTH_CLIP_DISABLE:
79 return 0; // TODO: implement depth clamp
80 case PIPE_CAP_PRIMITIVE_RESTART:
81 return 0; // TODO: implement primitive restart
82 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
83 case PIPE_CAP_TGSI_INSTANCEID:
84 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
85 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
86 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
87 case PIPE_CAP_SEAMLESS_CUBE_MAP:
88 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
89 case PIPE_CAP_SHADER_STENCIL_EXPORT:
90 case PIPE_CAP_MIN_TEXEL_OFFSET:
91 case PIPE_CAP_MAX_TEXEL_OFFSET:
92 case PIPE_CAP_CONDITIONAL_RENDER:
93 case PIPE_CAP_TEXTURE_BARRIER:
94 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
95 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
96 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
97 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
98 case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
99 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
100 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
101 return 0;
102 default:
103 NOUVEAU_ERR("Warning: unknown PIPE_CAP %d\n", param);
104 return 0;
105 }
106}
107
108static int
109nvfx_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, enum pipe_shader_cap param)
110{
111 struct nvfx_screen *screen = nvfx_screen(pscreen);
112
113 switch(shader) {
114 case PIPE_SHADER_FRAGMENT:
115 switch(param) {
116 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
117 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
118 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
119 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
120 return 4096;
121 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
122 /* FIXME: is it the dynamic (nv30:0/nv40:24) or the static
123 value (nv30:0/nv40:4) ? */
124 return screen->use_nv4x ? 4 : 0;
125 case PIPE_SHADER_CAP_MAX_INPUTS:
126 return screen->use_nv4x ? 12 : 10;
127 case PIPE_SHADER_CAP_MAX_CONSTS:
128 return screen->use_nv4x ? 224 : 32;
129 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
130 return 1;
131 case PIPE_SHADER_CAP_MAX_TEMPS:
132 return 32;
133 case PIPE_SHADER_CAP_MAX_ADDRS:
134 return screen->use_nv4x ? 1 : 0;
135 case PIPE_SHADER_CAP_MAX_PREDS:
136 return 0; /* we could expose these, but nothing uses them */
137 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
138 return 0;
139 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
140 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
141 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
142 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
143 return 0;
144 case PIPE_SHADER_CAP_SUBROUTINES:
145 return screen->use_nv4x ? 1 : 0;
146 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
147 return 16;
148 default:
149 break;
150 }
151 break;
152 case PIPE_SHADER_VERTEX:
153 switch(param) {
154 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
155 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
156 return screen->use_nv4x ? 512 : 256;
157 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
158 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
159 return screen->use_nv4x ? 512 : 0;
160 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
161 /* FIXME: is it the dynamic (nv30:24/nv40:24) or the static
162 value (nv30:1/nv40:4) ? */
163 return screen->use_nv4x ? 4 : 1;
164 case PIPE_SHADER_CAP_MAX_INPUTS:
165 return 16;
166 case PIPE_SHADER_CAP_MAX_CONSTS:
167 /* - 6 is for clip planes; Gallium should be fixed to put
168 * them in the vertex shader itself, so we don't need to reserve these */
169 return (screen->use_nv4x ? 468 : 256) - 6;
170 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
171 return 1;
172 case PIPE_SHADER_CAP_MAX_TEMPS:
173 return screen->use_nv4x ? 32 : 13;
174 case PIPE_SHADER_CAP_MAX_ADDRS:
175 return 2;
176 case PIPE_SHADER_CAP_MAX_PREDS:
177 return 0; /* we could expose these, but nothing uses them */
178 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
179 return 1;
180 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
181 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
182 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
183 return 0;
184 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
185 return 1;
186 case PIPE_SHADER_CAP_SUBROUTINES:
187 return 1;
188 case PIPE_SHADER_CAP_INTEGERS:
189 return 0;
190 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
191 return 0; /* We have 4 on nv40 - but unsupported currently */
192 default:
193 break;
194 }
195 break;
196 default:
197 break;
198 }
199 return 0;
200}
201
202static float
203nvfx_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
204{
205 struct nvfx_screen *screen = nvfx_screen(pscreen);
206
207 switch (param) {
208 case PIPE_CAPF_MAX_LINE_WIDTH:
209 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
210 return 10.0;
211 case PIPE_CAPF_MAX_POINT_WIDTH:
212 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
213 return 64.0;
214 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
215 return screen->use_nv4x ? 16.0 : 8.0;
216 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
217 return 15.0;
218 default:
219 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
220 return 0.0;
221 }
222}
223
224static int
225nvfx_screen_get_video_param(struct pipe_screen *screen,
226 enum pipe_video_profile profile,
227 enum pipe_video_cap param)
228{
229 switch (param) {
230 case PIPE_VIDEO_CAP_SUPPORTED:
231 return vl_profile_supported(screen, profile);
232 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
233 return 0;
234 case PIPE_VIDEO_CAP_MAX_WIDTH:
235 case PIPE_VIDEO_CAP_MAX_HEIGHT:
236 return vl_video_buffer_max_size(screen);
237 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
238 return PIPE_FORMAT_NV12;
239 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
240 return false;
241 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
242 return false;
243 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
244 return true;
245 default:
246 return 0;
247 }
248}
249
250static boolean
251nvfx_screen_is_format_supported(struct pipe_screen *pscreen,
252 enum pipe_format format,
253 enum pipe_texture_target target,
254 unsigned sample_count,
255 unsigned bind)
256{
257 struct nvfx_screen *screen = nvfx_screen(pscreen);
258
259 if (!util_format_is_supported(format, bind))
260 return FALSE;
261
262 if (sample_count > 1)
263 return FALSE;
264
265 if (bind & PIPE_BIND_RENDER_TARGET) {
266 switch (format) {
267 case PIPE_FORMAT_B8G8R8A8_UNORM:
268 case PIPE_FORMAT_B8G8R8X8_UNORM:
269 case PIPE_FORMAT_R8G8B8A8_UNORM:
270 case PIPE_FORMAT_R8G8B8X8_UNORM:
271 case PIPE_FORMAT_B5G6R5_UNORM:
272 break;
273 case PIPE_FORMAT_R16G16B16A16_FLOAT:
274 if(!screen->advertise_fp16)
275 return FALSE;
276 break;
277 case PIPE_FORMAT_R32G32B32A32_FLOAT:
278 if(!screen->advertise_fp32)
279 return FALSE;
280 break;
281 default:
282 return FALSE;
283 }
284 }
285
286 if (bind & PIPE_BIND_DEPTH_STENCIL) {
287 switch (format) {
288 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
289 case PIPE_FORMAT_X8Z24_UNORM:
290 case PIPE_FORMAT_Z16_UNORM:
291 break;
292 default:
293 return FALSE;
294 }
295 }
296
297 if (bind & PIPE_BIND_SAMPLER_VIEW) {
298 struct nvfx_texture_format* tf = &nvfx_texture_formats[format];
299 if(util_format_is_s3tc(format) && !util_format_s3tc_enabled)
300 return FALSE;
301 if(format == PIPE_FORMAT_R16G16B16A16_FLOAT && !screen->advertise_fp16)
302 return FALSE;
303 if(format == PIPE_FORMAT_R32G32B32A32_FLOAT && !screen->advertise_fp32)
304 return FALSE;
305 if(screen->use_nv4x)
306 {
307 if(tf->fmt[4] < 0)
308 return FALSE;
309 }
310 else
311 {
312 if(tf->fmt[0] < 0)
313 return FALSE;
314 }
315 }
316
317 // note that we do actually support everything through translate
318 if (bind & PIPE_BIND_VERTEX_BUFFER) {
319 unsigned type = nvfx_vertex_formats[format];
320 if(!type)
321 return FALSE;
322 }
323
324 if (bind & PIPE_BIND_INDEX_BUFFER) {
325 // 8-bit indices supported, but not in hardware index buffer
326 if(format != PIPE_FORMAT_R16_USCALED && format != PIPE_FORMAT_R32_USCALED)
327 return FALSE;
328 }
329
330 if(bind & PIPE_BIND_STREAM_OUTPUT)
331 return FALSE;
332
333 return TRUE;
334}
335
336static void
337nvfx_screen_destroy(struct pipe_screen *pscreen)
338{
339 struct nvfx_screen *screen = nvfx_screen(pscreen);
340
341 nouveau_resource_destroy(&screen->vp_exec_heap);
342 nouveau_resource_destroy(&screen->vp_data_heap);
343 nouveau_resource_destroy(&screen->query_heap);
344 nouveau_notifier_free(&screen->query);
345 nouveau_notifier_free(&screen->sync);
346 nouveau_grobj_free(&screen->eng3d);
347 nvfx_screen_surface_takedown(pscreen);
348 nouveau_bo_ref(NULL, &screen->fence);
349
350 nouveau_screen_fini(&screen->base);
351
352 FREE(pscreen);
353}
354
355static void nv30_screen_init(struct nvfx_screen *screen)
356{
357 struct nouveau_channel *chan = screen->base.channel;
358 struct nouveau_grobj *eng3d = screen->eng3d;
359 int i;
360
361 /* TODO: perhaps we should do some of this on nv40 too? */
362 for (i=1; i<8; i++) {
363 BEGIN_RING(chan, eng3d, NV30_3D_VIEWPORT_CLIP_HORIZ(i), 1);
364 OUT_RING(chan, 0);
365 BEGIN_RING(chan, eng3d, NV30_3D_VIEWPORT_CLIP_VERT(i), 1);
366 OUT_RING(chan, 0);
367 }
368
369 BEGIN_RING(chan, eng3d, 0x220, 1);
370 OUT_RING(chan, 1);
371
372 BEGIN_RING(chan, eng3d, 0x03b0, 1);
373 OUT_RING(chan, 0x00100000);
374 BEGIN_RING(chan, eng3d, 0x1454, 1);
375 OUT_RING(chan, 0);
376 BEGIN_RING(chan, eng3d, 0x1d80, 1);
377 OUT_RING(chan, 3);
378 BEGIN_RING(chan, eng3d, 0x1450, 1);
379 OUT_RING(chan, 0x00030004);
380
381 /* NEW */
382 BEGIN_RING(chan, eng3d, 0x1e98, 1);
383 OUT_RING(chan, 0);
384 BEGIN_RING(chan, eng3d, 0x17e0, 3);
385 OUT_RING(chan, fui(0.0));
386 OUT_RING(chan, fui(0.0));
387 OUT_RING(chan, fui(1.0));
388 BEGIN_RING(chan, eng3d, 0x1f80, 16);
389 for (i=0; i<16; i++) {
390 OUT_RING(chan, (i==8) ? 0x0000ffff : 0);
391 }
392
393 BEGIN_RING(chan, eng3d, 0x120, 3);
394 OUT_RING(chan, 0);
395 OUT_RING(chan, 1);
396 OUT_RING(chan, 2);
397
398 BEGIN_RING(chan, eng3d, 0x1d88, 1);
399 OUT_RING(chan, 0x00001200);
400
401 BEGIN_RING(chan, eng3d, NV30_3D_RC_ENABLE, 1);
402 OUT_RING(chan, 0);
403
404 BEGIN_RING(chan, eng3d, NV30_3D_DEPTH_RANGE_NEAR, 2);
405 OUT_RING(chan, fui(0.0));
406 OUT_RING(chan, fui(1.0));
407
408 BEGIN_RING(chan, eng3d, NV30_3D_MULTISAMPLE_CONTROL, 1);
409 OUT_RING(chan, 0xffff0000);
410
411 /* enables use of vp rather than fixed-function somehow */
412 BEGIN_RING(chan, eng3d, 0x1e94, 1);
413 OUT_RING(chan, 0x13);
414}
415
416static void nv40_screen_init(struct nvfx_screen *screen)
417{
418 struct nouveau_channel *chan = screen->base.channel;
419 struct nouveau_grobj *eng3d = screen->eng3d;
420
421 BEGIN_RING(chan, eng3d, NV40_3D_DMA_COLOR2, 2);
422 OUT_RING(chan, screen->base.channel->vram->handle);
423 OUT_RING(chan, screen->base.channel->vram->handle);
424
425 BEGIN_RING(chan, eng3d, 0x1450, 1);
426 OUT_RING(chan, 0x00000004);
427
428 BEGIN_RING(chan, eng3d, 0x1ea4, 3);
429 OUT_RING(chan, 0x00000010);
430 OUT_RING(chan, 0x01000100);
431 OUT_RING(chan, 0xff800006);
432
433 /* vtxprog output routing */
434 BEGIN_RING(chan, eng3d, 0x1fc4, 1);
435 OUT_RING(chan, 0x06144321);
436 BEGIN_RING(chan, eng3d, 0x1fc8, 2);
437 OUT_RING(chan, 0xedcba987);
438 OUT_RING(chan, 0x0000006f);
439 BEGIN_RING(chan, eng3d, 0x1fd0, 1);
440 OUT_RING(chan, 0x00171615);
441 BEGIN_RING(chan, eng3d, 0x1fd4, 1);
442 OUT_RING(chan, 0x001b1a19);
443
444 BEGIN_RING(chan, eng3d, 0x1ef8, 1);
445 OUT_RING(chan, 0x0020ffff);
446 BEGIN_RING(chan, eng3d, 0x1d64, 1);
447 OUT_RING(chan, 0x01d300d4);
448 BEGIN_RING(chan, eng3d, 0x1e94, 1);
449 OUT_RING(chan, 0x00000001);
450
451 BEGIN_RING(chan, eng3d, NV40_3D_MIPMAP_ROUNDING, 1);
452 OUT_RING(chan, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
453}
454
455static unsigned
456nvfx_screen_get_vertex_buffer_flags(struct nvfx_screen* screen)
457{
458 int vram_hack_default = 0;
459 int vram_hack;
460 // TODO: this is a bit of a guess; also add other cards that may need this hack.
461 // It may also depend on the specific card or the AGP/PCIe chipset.
462 if(screen->base.device->chipset == 0x47 /* G70 */
463 || screen->base.device->chipset == 0x49 /* G71 */
464 || screen->base.device->chipset == 0x46 /* G72 */
465 )
466 vram_hack_default = 1;
467 vram_hack = debug_get_bool_option("NOUVEAU_VTXIDX_IN_VRAM", vram_hack_default);
468
469 return vram_hack ? NOUVEAU_BO_VRAM : NOUVEAU_BO_GART;
470}
471
472static void nvfx_channel_flush_notify(struct nouveau_channel* chan)
473{
474 struct nvfx_screen* screen = chan->user_private;
475 struct nvfx_context* nvfx = screen->cur_ctx;
476 if(nvfx)
477 nvfx->relocs_needed = NVFX_RELOCATE_ALL;
478}
479
480struct pipe_screen *
481nvfx_screen_create(struct nouveau_device *dev)
482{
483 static const unsigned query_sizes[] = {(4096 - 4 * 32) / 32, 3 * 1024 / 32, 2 * 1024 / 32, 1024 / 32};
484 struct nvfx_screen *screen = CALLOC_STRUCT(nvfx_screen);
485 struct nouveau_channel *chan;
486 struct pipe_screen *pscreen;
487 unsigned eng3d_class = 0;
488 int ret, i;
489
490 if (!screen)
491 return NULL;
492
493 pscreen = &screen->base.base;
494
495 ret = nouveau_screen_init(&screen->base, dev);
496 if (ret) {
497 nvfx_screen_destroy(pscreen);
498 return NULL;
499 }
500 chan = screen->base.channel;
501 screen->cur_ctx = NULL;
502 chan->user_private = screen;
503 chan->flush_notify = nvfx_channel_flush_notify;
504
505 pscreen->destroy = nvfx_screen_destroy;
506 pscreen->get_param = nvfx_screen_get_param;
507 pscreen->get_shader_param = nvfx_screen_get_shader_param;
508 pscreen->get_paramf = nvfx_screen_get_paramf;
509 pscreen->get_video_param = nvfx_screen_get_video_param;
510 pscreen->is_format_supported = nvfx_screen_is_format_supported;
511 pscreen->is_video_format_supported = vl_video_buffer_is_format_supported;
512 pscreen->context_create = nvfx_create;
513
514 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, 4096, &screen->fence);
515 if (ret) {
516 nvfx_screen_destroy(pscreen);
517 return NULL;
518 }
519
520 switch (dev->chipset & 0xf0) {
521 case 0x30:
522 if (NV30_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
523 eng3d_class = NV30_3D;
524 else if (NV34_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
525 eng3d_class = NV34_3D;
526 else if (NV35_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
527 eng3d_class = NV35_3D;
528 break;
529 case 0x40:
530 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (dev->chipset & 0x0f)))
531 eng3d_class = NV40_3D;
532 else if (NV4X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
533 eng3d_class = NV44_3D;
534 screen->is_nv4x = ~0;
535 break;
536 case 0x60:
537 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
538 eng3d_class = NV44_3D;
539 screen->is_nv4x = ~0;
540 break;
541 }
542
543 if (!eng3d_class) {
544 NOUVEAU_ERR("Unknown nv3x/nv4x chipset: nv%02x\n", dev->chipset);
545 return NULL;
546 }
547
548 screen->advertise_npot = !!screen->is_nv4x;
549 screen->advertise_blend_equation_separate = !!screen->is_nv4x;
550 screen->use_nv4x = screen->is_nv4x;
551
552 if(screen->is_nv4x) {
553 if(debug_get_bool_option("NVFX_SIMULATE_NV30", FALSE))
554 screen->use_nv4x = 0;
555 if(!debug_get_bool_option("NVFX_NPOT", TRUE))
556 screen->advertise_npot = 0;
557 if(!debug_get_bool_option("NVFX_BLEND_EQ_SEP", TRUE))
558 screen->advertise_blend_equation_separate = 0;
559 }
560
561 screen->force_swtnl = debug_get_bool_option("NVFX_SWTNL", FALSE);
562 screen->trace_draw = debug_get_bool_option("NVFX_TRACE_DRAW", FALSE);
563
564 screen->buffer_allocation_cost = debug_get_num_option("NVFX_BUFFER_ALLOCATION_COST", 16384);
565 screen->inline_cost_per_hardware_cost = atof(debug_get_option("NVFX_INLINE_COST_PER_HARDWARE_COST", "1.0"));
566 screen->static_reuse_threshold = atof(debug_get_option("NVFX_STATIC_REUSE_THRESHOLD", "2.0"));
567
568 /* We don't advertise these by default because filtering and blending doesn't work as
569 * it should, due to several restrictions.
570 * The only exception is fp16 on nv40.
571 */
572 screen->advertise_fp16 = debug_get_bool_option("NVFX_FP16", !!screen->use_nv4x);
573 screen->advertise_fp32 = debug_get_bool_option("NVFX_FP32", 0);
574
575 screen->vertex_buffer_reloc_flags = nvfx_screen_get_vertex_buffer_flags(screen);
576
577 /* surely both nv3x and nv44 support index buffers too: find out how and test that */
578 if(eng3d_class == NV40_3D)
579 screen->index_buffer_reloc_flags = screen->vertex_buffer_reloc_flags;
580
581 if(!screen->force_swtnl && screen->vertex_buffer_reloc_flags == screen->index_buffer_reloc_flags)
582 screen->base.vertex_buffer_flags = screen->base.index_buffer_flags = screen->vertex_buffer_reloc_flags;
583
584 nvfx_screen_init_resource_functions(pscreen);
585
586 ret = nouveau_grobj_alloc(chan, 0xbeef3097, eng3d_class, &screen->eng3d);
587 if (ret) {
588 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
589 return FALSE;
590 }
591
592 /* 2D engine setup */
593 nvfx_screen_surface_init(pscreen);
594
595 /* Notifier for sync purposes */
596 ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
597 if (ret) {
598 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
599 nvfx_screen_destroy(pscreen);
600 return NULL;
601 }
602
603 /* Query objects */
604 for(i = 0; i < sizeof(query_sizes) / sizeof(query_sizes[0]); ++i)
605 {
606 ret = nouveau_notifier_alloc(chan, 0xbeef0302, query_sizes[i], &screen->query);
607 if(!ret)
608 break;
609 }
610
611 if (ret) {
612 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
613 nvfx_screen_destroy(pscreen);
614 return NULL;
615 }
616
617 ret = nouveau_resource_init(&screen->query_heap, 0, query_sizes[i]);
618 if (ret) {
619 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
620 nvfx_screen_destroy(pscreen);
621 return NULL;
622 }
623
624 LIST_INITHEAD(&screen->query_list);
625
626 /* Vtxprog resources */
627 if (nouveau_resource_init(&screen->vp_exec_heap, 0, screen->use_nv4x ? 512 : 256) ||
628 nouveau_resource_init(&screen->vp_data_heap, 0, screen->use_nv4x ? 468 : 256)) {
629 nvfx_screen_destroy(pscreen);
630 return NULL;
631 }
632
633 BIND_RING(chan, screen->eng3d, 7);
634
635 /* Static eng3d initialisation */
636 /* note that we just started using the channel, so we must have space in the pushbuffer */
637 BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_NOTIFY, 1);
638 OUT_RING(chan, screen->sync->handle);
639 BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_TEXTURE0, 2);
640 OUT_RING(chan, chan->vram->handle);
641 OUT_RING(chan, chan->gart->handle);
642 BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_COLOR1, 1);
643 OUT_RING(chan, chan->vram->handle);
644 BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_COLOR0, 2);
645 OUT_RING(chan, chan->vram->handle);
646 OUT_RING(chan, chan->vram->handle);
647 BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_VTXBUF0, 2);
648 OUT_RING(chan, chan->vram->handle);
649 OUT_RING(chan, chan->gart->handle);
650
651 BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_FENCE, 2);
652 OUT_RING(chan, 0);
653 OUT_RING(chan, screen->query->handle);
654
655 BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_UNK1AC, 2);
656 OUT_RING(chan, chan->vram->handle);
657 OUT_RING(chan, chan->vram->handle);
658
659 if(!screen->is_nv4x)
660 nv30_screen_init(screen);
661 else
662 nv40_screen_init(screen);
663
664 return pscreen;
665}
diff --git a/src/gallium/drivers/nvfx/nvfx_screen.h b/src/gallium/drivers/nvfx/nvfx_screen.h
deleted file mode 100644
index 35c9d910479..00000000000
--- a/src/gallium/drivers/nvfx/nvfx_screen.h
+++ /dev/null
@@ -1,65 +0,0 @@
1#ifndef __NVFX_SCREEN_H__
2#define __NVFX_SCREEN_H__
3
4#include "pipe/p_compiler.h"
5#include "util/u_double_list.h"
6#include "nouveau/nouveau_screen.h"
7
8struct pipe_screen;
9
10struct nvfx_screen {
11 struct nouveau_screen base;
12
13 struct nouveau_bo *fence;
14
15 struct nvfx_context *cur_ctx;
16
17 unsigned is_nv4x; /* either 0 or ~0 */
18 unsigned use_nv4x; /* either 0 or ~0 */
19 boolean force_swtnl;
20 boolean trace_draw;
21 unsigned vertex_buffer_reloc_flags;
22 unsigned index_buffer_reloc_flags;
23 unsigned advertise_fp16;
24 unsigned advertise_fp32;
25 unsigned advertise_npot;
26 unsigned advertise_blend_equation_separate;
27
28 /* HW graphics objects */
29 struct nouveau_grobj *eng3d;
30 struct nouveau_notifier *sync;
31
32 /* Query object resources */
33 struct nouveau_notifier *query;
34 struct nouveau_resource *query_heap;
35 struct list_head query_list;
36
37 /* Vtxprog resources */
38 struct nouveau_resource *vp_exec_heap;
39 struct nouveau_resource *vp_data_heap;
40
41 struct nv04_2d_context* eng2d;
42
43 /* Once the amount of bytes drawn from the buffer reaches the updated size times this value,
44 * we will assume that the buffer will be drawn an huge number of times before the
45 * next modification
46 */
47 float static_reuse_threshold;
48
49 /* Cost of allocating a buffer in terms of the cost of copying a byte to an hardware buffer */
50 unsigned buffer_allocation_cost;
51
52 /* inline_cost/hardware_cost conversion ration */
53 float inline_cost_per_hardware_cost;
54};
55
56static INLINE struct nvfx_screen *
57nvfx_screen(struct pipe_screen *screen)
58{
59 return (struct nvfx_screen *)screen;
60}
61
62int nvfx_screen_surface_init(struct pipe_screen *pscreen);
63void nvfx_screen_surface_takedown(struct pipe_screen *pscreen);
64
65#endif
diff --git a/src/gallium/drivers/nvfx/nvfx_shader.h b/src/gallium/drivers/nvfx/nvfx_shader.h
deleted file mode 100644
index 46406b27940..00000000000
--- a/src/gallium/drivers/nvfx/nvfx_shader.h
+++ /dev/null
@@ -1,526 +0,0 @@
1#ifndef __NVFX_SHADER_H__
2#define __NVFX_SHADER_H__
3
4#include <stdint.h>
5
6#include "pipe/p_compiler.h"
7
8#define NVFX_SWZ_IDENTITY ((3 << 6) | (2 << 4) | (1 << 2) | (0 << 0))
9
10/* this will resolve to either the NV30 or the NV40 version
11 * depending on the current hardware */
12/* unusual, but very fast and compact method */
13#define NVFX_VP(c) ((NV30_VP_##c) + (nvfx->is_nv4x & ((NV40_VP_##c) - (NV30_VP_##c))))
14
15#define NVFX_VP_INST_SLOT_VEC 0
16#define NVFX_VP_INST_SLOT_SCA 1
17
18#define NVFX_VP_INST_IN_POS 0 /* These seem to match the bindings specified in */
19#define NVFX_VP_INST_IN_WEIGHT 1 /* the ARB_v_p spec (2.14.3.1) */
20#define NVFX_VP_INST_IN_NORMAL 2
21#define NVFX_VP_INST_IN_COL0 3 /* Should probably confirm them all though */
22#define NVFX_VP_INST_IN_COL1 4
23#define NVFX_VP_INST_IN_FOGC 5
24#define NVFX_VP_INST_IN_TC0 8
25#define NVFX_VP_INST_IN_TC(n) (8+n)
26
27#define NVFX_VP_INST_SCA_OP_NOP 0x00
28#define NVFX_VP_INST_SCA_OP_MOV 0x01
29#define NVFX_VP_INST_SCA_OP_RCP 0x02
30#define NVFX_VP_INST_SCA_OP_RCC 0x03
31#define NVFX_VP_INST_SCA_OP_RSQ 0x04
32#define NVFX_VP_INST_SCA_OP_EXP 0x05
33#define NVFX_VP_INST_SCA_OP_LOG 0x06
34#define NVFX_VP_INST_SCA_OP_LIT 0x07
35#define NVFX_VP_INST_SCA_OP_BRA 0x09
36#define NVFX_VP_INST_SCA_OP_CAL 0x0B
37#define NVFX_VP_INST_SCA_OP_RET 0x0C
38#define NVFX_VP_INST_SCA_OP_LG2 0x0D
39#define NVFX_VP_INST_SCA_OP_EX2 0x0E
40#define NVFX_VP_INST_SCA_OP_SIN 0x0F
41#define NVFX_VP_INST_SCA_OP_COS 0x10
42
43#define NV40_VP_INST_SCA_OP_PUSHA 0x13
44#define NV40_VP_INST_SCA_OP_POPA 0x14
45
46#define NVFX_VP_INST_VEC_OP_NOP 0x00
47#define NVFX_VP_INST_VEC_OP_MOV 0x01
48#define NVFX_VP_INST_VEC_OP_MUL 0x02
49#define NVFX_VP_INST_VEC_OP_ADD 0x03
50#define NVFX_VP_INST_VEC_OP_MAD 0x04
51#define NVFX_VP_INST_VEC_OP_DP3 0x05
52#define NVFX_VP_INST_VEC_OP_DPH 0x06
53#define NVFX_VP_INST_VEC_OP_DP4 0x07
54#define NVFX_VP_INST_VEC_OP_DST 0x08
55#define NVFX_VP_INST_VEC_OP_MIN 0x09
56#define NVFX_VP_INST_VEC_OP_MAX 0x0A
57#define NVFX_VP_INST_VEC_OP_SLT 0x0B
58#define NVFX_VP_INST_VEC_OP_SGE 0x0C
59#define NVFX_VP_INST_VEC_OP_ARL 0x0D
60#define NVFX_VP_INST_VEC_OP_FRC 0x0E
61#define NVFX_VP_INST_VEC_OP_FLR 0x0F
62#define NVFX_VP_INST_VEC_OP_SEQ 0x10
63#define NVFX_VP_INST_VEC_OP_SFL 0x11
64#define NVFX_VP_INST_VEC_OP_SGT 0x12
65#define NVFX_VP_INST_VEC_OP_SLE 0x13
66#define NVFX_VP_INST_VEC_OP_SNE 0x14
67#define NVFX_VP_INST_VEC_OP_STR 0x15
68#define NVFX_VP_INST_VEC_OP_SSG 0x16
69#define NVFX_VP_INST_VEC_OP_ARR 0x17
70#define NVFX_VP_INST_VEC_OP_ARA 0x18
71
72#define NV40_VP_INST_VEC_OP_TXL 0x19
73
74/* DWORD 3 */
75#define NVFX_VP_INST_LAST (1 << 0)
76
77/*
78 * Each fragment program opcode appears to be comprised of 4 32-bit values.
79 *
80 * 0: OPDEST
81 * 0: program end
82 * 1-6: destination register
83 * 7: destination register is fp16?? (use for outputs)
84 * 8: set condition code
85 * 9: writemask x
86 * 10: writemask y
87 * 11: writemask z
88 * 12: writemask w
89 * 13-16: source attribute register number (e.g. COL0)
90 * 17-20: texture unit number
91 * 21: expand value on texture operation (x -> 2x - 1)
92 * 22-23: precision 0 = fp32, 1 = fp16, 2 = s1.10 fixed, 3 = s0.8 fixed (nv40-only))
93 * 24-29: opcode
94 * 30: no destination
95 * 31: saturate
96 * 1 - SRC0
97 * 0-17: see common source fields
98 * 18: execute if condition code less
99 * 19: execute if condition code equal
100 * 20: execute if condition code greater
101 * 21-22: condition code swizzle x source component
102 * 23-24: condition code swizzle y source component
103 * 25-26: condition code swizzle z source component
104 * 27-28: condition code swizzle w source component
105 * 29: source 0 absolute
106 * 30: always 0 in renouveau tests
107 * 31: always 0 in renouveau tests
108 * 2 - SRC1
109 * 0-17: see common source fields
110 * 18: source 1 absolute
111 * 19-20: input precision 0 = fp32, 1 = fp16, 2 = s1.10 fixed, 3 = ???
112 * 21-27: always 0 in renouveau tests
113 * 28-30: scale (0 = 1x, 1 = 2x, 2 = 4x, 3 = 8x, 4 = ???, 5, = 1/2, 6 = 1/4, 7 = 1/8)
114 * 31: opcode is branch
115 * 3 - SRC2
116 * 0-17: see common source fields
117 * 18: source 2 absolute
118 * 19-29: address register displacement
119 * 30: use index register
120 * 31: disable perspective-correct interpolation?
121 *
122* Common fields of 0, 1, 2 - SRC
123 * 0-1: source register type (0 = temp, 1 = input, 2 = immediate, 3 = ???)
124 * 2-7: source temp register index
125 * 8: source register is fp16??
126 * 9-10: source swizzle x source component
127 * 11-12: source swizzle y source component
128 * 13-14: source swizzle z source component
129 * 15-16: source swizzle w source component
130 * 17: negate
131
132 * There appears to be no special difference between result regs and temp regs.
133 * result.color == R0.xyzw
134 * result.depth == R1.z
135 * When the fragprog contains instructions to write depth, NV30_TCL_PRIMITIVE_3D_UNK1D78=0
136 * otherwise it is set to 1.
137 *
138 * Constants are inserted directly after the instruction that uses them.
139 *
140 * It appears that it's not possible to use two input registers in one
141 * instruction as the input sourcing is done in the instruction dword
142 * and not the source selection dwords. As such instructions such as:
143 *
144 * ADD result.color, fragment.color, fragment.texcoord[0];
145 *
146 * must be split into two MOV's and then an ADD (nvidia does this) but
147 * I'm not sure why it's not just one MOV and then source the second input
148 * in the ADD instruction..
149 *
150 * Negation of the full source is done with NV30_FP_REG_NEGATE, arbitrary
151 * negation requires multiplication with a const.
152 *
153 * Arbitrary swizzling is supported with the exception of SWIZZLE_ZERO/SWIZZLE_ONE
154 * The temp/result regs appear to be initialised to (0.0, 0.0, 0.0, 0.0) as SWIZZLE_ZERO
155 * is implemented simply by not writing to the relevant components of the destination.
156 *
157 * Conditional execution
158 * TODO
159 *
160 * Non-native instructions:
161 * LIT
162 * LRP - MAD+MAD
163 * SUB - ADD, negate second source
164 * RSQ - LG2 + EX2
165 * POW - LG2 + MUL + EX2
166 * SCS - COS + SIN
167 * XPD
168 *
169 * NV40 Looping
170 * Loops appear to be fairly expensive on NV40 at least, the proprietary
171 * driver goes to a lot of effort to avoid using the native looping
172 * instructions. If the total number of *executed* instructions between
173 * REP/ENDREP or LOOP/ENDLOOP is <=500, the driver will unroll the loop.
174 * The maximum loop count is 255.
175 *
176 */
177
178//== Opcode / Destination selection ==
179#define NVFX_FP_OP_PROGRAM_END (1 << 0)
180#define NVFX_FP_OP_OUT_REG_SHIFT 1
181#define NV30_FP_OP_OUT_REG_MASK (31 << 1) /* uncertain */
182#define NV40_FP_OP_OUT_REG_MASK (63 << 1)
183/* Needs to be set when writing outputs to get expected result.. */
184#define NVFX_FP_OP_OUT_REG_HALF (1 << 7)
185#define NVFX_FP_OP_COND_WRITE_ENABLE (1 << 8)
186#define NVFX_FP_OP_OUTMASK_SHIFT 9
187#define NVFX_FP_OP_OUTMASK_MASK (0xF << 9)
188# define NVFX_FP_OP_OUT_X (1<<9)
189# define NVFX_FP_OP_OUT_Y (1<<10)
190# define NVFX_FP_OP_OUT_Z (1<<11)
191# define NVFX_FP_OP_OUT_W (1<<12)
192/* Uncertain about these, especially the input_src values.. it's possible that
193 * they can be dynamically changed.
194 */
195#define NVFX_FP_OP_INPUT_SRC_SHIFT 13
196#define NVFX_FP_OP_INPUT_SRC_MASK (15 << 13)
197# define NVFX_FP_OP_INPUT_SRC_POSITION 0x0
198# define NVFX_FP_OP_INPUT_SRC_COL0 0x1
199# define NVFX_FP_OP_INPUT_SRC_COL1 0x2
200# define NVFX_FP_OP_INPUT_SRC_FOGC 0x3
201# define NVFX_FP_OP_INPUT_SRC_TC0 0x4
202# define NVFX_FP_OP_INPUT_SRC_TC(n) (0x4 + n)
203# define NV40_FP_OP_INPUT_SRC_FACING 0xE
204#define NVFX_FP_OP_TEX_UNIT_SHIFT 17
205#define NVFX_FP_OP_TEX_UNIT_MASK (0xF << 17) /* guess */
206#define NVFX_FP_OP_PRECISION_SHIFT 22
207#define NVFX_FP_OP_PRECISION_MASK (3 << 22)
208# define NVFX_FP_PRECISION_FP32 0
209# define NVFX_FP_PRECISION_FP16 1
210# define NVFX_FP_PRECISION_FX12 2
211#define NVFX_FP_OP_OPCODE_SHIFT 24
212#define NVFX_FP_OP_OPCODE_MASK (0x3F << 24)
213/* NV30/NV40 fragment program opcodes */
214#define NVFX_FP_OP_OPCODE_NOP 0x00
215#define NVFX_FP_OP_OPCODE_MOV 0x01
216#define NVFX_FP_OP_OPCODE_MUL 0x02
217#define NVFX_FP_OP_OPCODE_ADD 0x03
218#define NVFX_FP_OP_OPCODE_MAD 0x04
219#define NVFX_FP_OP_OPCODE_DP3 0x05
220#define NVFX_FP_OP_OPCODE_DP4 0x06
221#define NVFX_FP_OP_OPCODE_DST 0x07
222#define NVFX_FP_OP_OPCODE_MIN 0x08
223#define NVFX_FP_OP_OPCODE_MAX 0x09
224#define NVFX_FP_OP_OPCODE_SLT 0x0A
225#define NVFX_FP_OP_OPCODE_SGE 0x0B
226#define NVFX_FP_OP_OPCODE_SLE 0x0C
227#define NVFX_FP_OP_OPCODE_SGT 0x0D
228#define NVFX_FP_OP_OPCODE_SNE 0x0E
229#define NVFX_FP_OP_OPCODE_SEQ 0x0F
230#define NVFX_FP_OP_OPCODE_FRC 0x10
231#define NVFX_FP_OP_OPCODE_FLR 0x11
232#define NVFX_FP_OP_OPCODE_KIL 0x12
233#define NVFX_FP_OP_OPCODE_PK4B 0x13
234#define NVFX_FP_OP_OPCODE_UP4B 0x14
235#define NVFX_FP_OP_OPCODE_DDX 0x15 /* can only write XY */
236#define NVFX_FP_OP_OPCODE_DDY 0x16 /* can only write XY */
237#define NVFX_FP_OP_OPCODE_TEX 0x17
238#define NVFX_FP_OP_OPCODE_TXP 0x18
239#define NVFX_FP_OP_OPCODE_TXD 0x19
240#define NVFX_FP_OP_OPCODE_RCP 0x1A
241#define NVFX_FP_OP_OPCODE_EX2 0x1C
242#define NVFX_FP_OP_OPCODE_LG2 0x1D
243#define NVFX_FP_OP_OPCODE_STR 0x20
244#define NVFX_FP_OP_OPCODE_SFL 0x21
245#define NVFX_FP_OP_OPCODE_COS 0x22
246#define NVFX_FP_OP_OPCODE_SIN 0x23
247#define NVFX_FP_OP_OPCODE_PK2H 0x24
248#define NVFX_FP_OP_OPCODE_UP2H 0x25
249#define NVFX_FP_OP_OPCODE_PK4UB 0x27
250#define NVFX_FP_OP_OPCODE_UP4UB 0x28
251#define NVFX_FP_OP_OPCODE_PK2US 0x29
252#define NVFX_FP_OP_OPCODE_UP2US 0x2A
253#define NVFX_FP_OP_OPCODE_DP2A 0x2E
254#define NVFX_FP_OP_OPCODE_TXB 0x31
255#define NVFX_FP_OP_OPCODE_DIV 0x3A
256
257/* NV30 only fragment program opcodes */
258#define NVFX_FP_OP_OPCODE_RSQ_NV30 0x1B
259#define NVFX_FP_OP_OPCODE_LIT_NV30 0x1E
260#define NVFX_FP_OP_OPCODE_LRP_NV30 0x1F
261#define NVFX_FP_OP_OPCODE_POW_NV30 0x26
262#define NVFX_FP_OP_OPCODE_RFL_NV30 0x36
263
264/* NV40 only fragment program opcodes */
265#define NVFX_FP_OP_OPCODE_TXL_NV40 0x2F
266#define NVFX_FP_OP_OPCODE_LITEX2_NV40 0x3C
267
268/* The use of these instructions appears to be indicated by bit 31 of DWORD 2.*/
269#define NV40_FP_OP_BRA_OPCODE_BRK 0x0
270#define NV40_FP_OP_BRA_OPCODE_CAL 0x1
271#define NV40_FP_OP_BRA_OPCODE_IF 0x2
272#define NV40_FP_OP_BRA_OPCODE_LOOP 0x3
273#define NV40_FP_OP_BRA_OPCODE_REP 0x4
274#define NV40_FP_OP_BRA_OPCODE_RET 0x5
275
276#define NV40_FP_OP_OUT_NONE (1 << 30)
277#define NVFX_FP_OP_OUT_SAT (1 << 31)
278
279/* high order bits of SRC0 */
280#define NVFX_FP_OP_SRC0_ABS (1 << 29)
281#define NVFX_FP_OP_COND_SWZ_W_SHIFT 27
282#define NVFX_FP_OP_COND_SWZ_W_MASK (3 << 27)
283#define NVFX_FP_OP_COND_SWZ_Z_SHIFT 25
284#define NVFX_FP_OP_COND_SWZ_Z_MASK (3 << 25)
285#define NVFX_FP_OP_COND_SWZ_Y_SHIFT 23
286#define NVFX_FP_OP_COND_SWZ_Y_MASK (3 << 23)
287#define NVFX_FP_OP_COND_SWZ_X_SHIFT 21
288#define NVFX_FP_OP_COND_SWZ_X_MASK (3 << 21)
289#define NVFX_FP_OP_COND_SWZ_ALL_SHIFT 21
290#define NVFX_FP_OP_COND_SWZ_ALL_MASK (0xFF << 21)
291#define NVFX_FP_OP_COND_SHIFT 18
292#define NVFX_FP_OP_COND_MASK (0x07 << 18)
293# define NVFX_FP_OP_COND_FL 0
294# define NVFX_FP_OP_COND_LT 1
295# define NVFX_FP_OP_COND_EQ 2
296# define NVFX_FP_OP_COND_LE 3
297# define NVFX_FP_OP_COND_GT 4
298# define NVFX_FP_OP_COND_NE 5
299# define NVFX_FP_OP_COND_GE 6
300# define NVFX_FP_OP_COND_TR 7
301
302/* high order bits of SRC1 */
303#define NV40_FP_OP_OPCODE_IS_BRANCH (1<<31)
304#define NVFX_FP_OP_DST_SCALE_SHIFT 28
305#define NVFX_FP_OP_DST_SCALE_MASK (3 << 28)
306#define NVFX_FP_OP_DST_SCALE_1X 0
307#define NVFX_FP_OP_DST_SCALE_2X 1
308#define NVFX_FP_OP_DST_SCALE_4X 2
309#define NVFX_FP_OP_DST_SCALE_8X 3
310#define NVFX_FP_OP_DST_SCALE_INV_2X 5
311#define NVFX_FP_OP_DST_SCALE_INV_4X 6
312#define NVFX_FP_OP_DST_SCALE_INV_8X 7
313#define NVFX_FP_OP_SRC1_ABS (1 << 18)
314
315/* SRC1 LOOP */
316#define NV40_FP_OP_LOOP_INCR_SHIFT 19
317#define NV40_FP_OP_LOOP_INCR_MASK (0xFF << 19)
318#define NV40_FP_OP_LOOP_INDEX_SHIFT 10
319#define NV40_FP_OP_LOOP_INDEX_MASK (0xFF << 10)
320#define NV40_FP_OP_LOOP_COUNT_SHIFT 2
321#define NV40_FP_OP_LOOP_COUNT_MASK (0xFF << 2)
322
323/* SRC1 IF: absolute offset in dwords */
324#define NV40_FP_OP_ELSE_OFFSET_SHIFT 0
325#define NV40_FP_OP_ELSE_OFFSET_MASK (0x7FFFFFFF << 0)
326
327/* SRC1 CAL */
328#define NV40_FP_OP_SUB_OFFSET_SHIFT 0
329#define NV40_FP_OP_SUB_OFFSET_MASK (0x7FFFFFFF << 0)
330
331/* SRC1 REP
332 * I have no idea why there are 3 count values here.. but they
333 * have always been filled with the same value in my tests so
334 * far..
335 */
336#define NV40_FP_OP_REP_COUNT1_SHIFT 2
337#define NV40_FP_OP_REP_COUNT1_MASK (0xFF << 2)
338#define NV40_FP_OP_REP_COUNT2_SHIFT 10
339#define NV40_FP_OP_REP_COUNT2_MASK (0xFF << 10)
340#define NV40_FP_OP_REP_COUNT3_SHIFT 19
341#define NV40_FP_OP_REP_COUNT3_MASK (0xFF << 19)
342
343/* SRC2 REP/IF: absolute offset in dwords */
344#define NV40_FP_OP_END_OFFSET_SHIFT 0
345#define NV40_FP_OP_END_OFFSET_MASK (0x7FFFFFFF << 0)
346
347/* high order bits of SRC2 */
348#define NVFX_FP_OP_INDEX_INPUT (1 << 30)
349#define NV40_FP_OP_ADDR_INDEX_SHIFT 19
350#define NV40_FP_OP_ADDR_INDEX_MASK (0xF << 19)
351
352//== Register selection ==
353#define NVFX_FP_REG_TYPE_SHIFT 0
354#define NVFX_FP_REG_TYPE_MASK (3 << 0)
355# define NVFX_FP_REG_TYPE_TEMP 0
356# define NVFX_FP_REG_TYPE_INPUT 1
357# define NVFX_FP_REG_TYPE_CONST 2
358#define NVFX_FP_REG_SRC_SHIFT 2
359#define NV30_FP_REG_SRC_MASK (31 << 2)
360#define NV40_FP_REG_SRC_MASK (63 << 2)
361#define NVFX_FP_REG_SRC_HALF (1 << 8)
362#define NVFX_FP_REG_SWZ_ALL_SHIFT 9
363#define NVFX_FP_REG_SWZ_ALL_MASK (255 << 9)
364#define NVFX_FP_REG_SWZ_X_SHIFT 9
365#define NVFX_FP_REG_SWZ_X_MASK (3 << 9)
366#define NVFX_FP_REG_SWZ_Y_SHIFT 11
367#define NVFX_FP_REG_SWZ_Y_MASK (3 << 11)
368#define NVFX_FP_REG_SWZ_Z_SHIFT 13
369#define NVFX_FP_REG_SWZ_Z_MASK (3 << 13)
370#define NVFX_FP_REG_SWZ_W_SHIFT 15
371#define NVFX_FP_REG_SWZ_W_MASK (3 << 15)
372# define NVFX_FP_SWIZZLE_X 0
373# define NVFX_FP_SWIZZLE_Y 1
374# define NVFX_FP_SWIZZLE_Z 2
375# define NVFX_FP_SWIZZLE_W 3
376#define NVFX_FP_REG_NEGATE (1 << 17)
377
378#define NVFXSR_NONE 0
379#define NVFXSR_OUTPUT 1
380#define NVFXSR_INPUT 2
381#define NVFXSR_TEMP 3
382#define NVFXSR_CONST 5
383#define NVFXSR_IMM 6
384#define NVFXSR_RELOCATED 7
385
386#define NVFX_COND_FL 0
387#define NVFX_COND_LT 1
388#define NVFX_COND_EQ 2
389#define NVFX_COND_LE 3
390#define NVFX_COND_GT 4
391#define NVFX_COND_NE 5
392#define NVFX_COND_GE 6
393#define NVFX_COND_TR 7
394
395/* Yes, this are ordered differently... */
396
397#define NVFX_VP_MASK_X 8
398#define NVFX_VP_MASK_Y 4
399#define NVFX_VP_MASK_Z 2
400#define NVFX_VP_MASK_W 1
401#define NVFX_VP_MASK_ALL 0xf
402
403#define NVFX_FP_MASK_X 1
404#define NVFX_FP_MASK_Y 2
405#define NVFX_FP_MASK_Z 4
406#define NVFX_FP_MASK_W 8
407#define NVFX_FP_MASK_ALL 0xf
408
409#define NVFX_SWZ_X 0
410#define NVFX_SWZ_Y 1
411#define NVFX_SWZ_Z 2
412#define NVFX_SWZ_W 3
413
414#define swz(s,x,y,z,w) nvfx_src_swz((s), NVFX_SWZ_##x, NVFX_SWZ_##y, NVFX_SWZ_##z, NVFX_SWZ_##w)
415#define neg(s) nvfx_src_neg((s))
416#define abs(s) nvfx_src_abs((s))
417
418struct nvfx_reg {
419 int8_t type;
420 uint32_t index;
421};
422
423struct nvfx_src {
424 struct nvfx_reg reg;
425
426 uint8_t indirect : 1;
427 uint8_t indirect_reg : 1;
428 uint8_t indirect_swz : 2;
429 uint8_t negate : 1;
430 uint8_t abs : 1;
431 uint8_t swz[4];
432};
433
434struct nvfx_insn
435{
436 uint8_t op;
437 char scale;
438 int8_t unit;
439 uint8_t mask;
440 uint8_t cc_swz[4];
441
442 uint8_t sat : 1;
443 uint8_t cc_update : 1;
444 uint8_t cc_update_reg : 1;
445 uint8_t cc_test : 3;
446 uint8_t cc_test_reg : 1;
447
448 struct nvfx_reg dst;
449 struct nvfx_src src[3];
450};
451
452static INLINE struct nvfx_insn
453nvfx_insn(boolean sat, unsigned op, int unit, struct nvfx_reg dst, unsigned mask, struct nvfx_src s0, struct nvfx_src s1, struct nvfx_src s2)
454{
455 struct nvfx_insn insn = {
456 .op = op,
457 .scale = 0,
458 .unit = unit,
459 .sat = sat,
460 .mask = mask,
461 .cc_update = 0,
462 .cc_update_reg = 0,
463 .cc_test = NVFX_COND_TR,
464 .cc_test_reg = 0,
465 .cc_swz = { 0, 1, 2, 3 },
466 .dst = dst,
467 .src = {s0, s1, s2}
468 };
469 return insn;
470}
471
472static INLINE struct nvfx_reg
473nvfx_reg(int type, int index)
474{
475 struct nvfx_reg temp = {
476 .type = type,
477 .index = index,
478 };
479 return temp;
480}
481
482static INLINE struct nvfx_src
483nvfx_src(struct nvfx_reg reg)
484{
485 struct nvfx_src temp = {
486 .reg = reg,
487 .abs = 0,
488 .negate = 0,
489 .swz = { 0, 1, 2, 3 },
490 .indirect = 0,
491 };
492 return temp;
493}
494
495static INLINE struct nvfx_src
496nvfx_src_swz(struct nvfx_src src, int x, int y, int z, int w)
497{
498 struct nvfx_src dst = src;
499
500 dst.swz[NVFX_SWZ_X] = src.swz[x];
501 dst.swz[NVFX_SWZ_Y] = src.swz[y];
502 dst.swz[NVFX_SWZ_Z] = src.swz[z];
503 dst.swz[NVFX_SWZ_W] = src.swz[w];
504 return dst;
505}
506
507static INLINE struct nvfx_src
508nvfx_src_neg(struct nvfx_src src)
509{
510 src.negate = !src.negate;
511 return src;
512}
513
514static INLINE struct nvfx_src
515nvfx_src_abs(struct nvfx_src src)
516{
517 src.abs = 1;
518 return src;
519}
520
521struct nvfx_relocation {
522 unsigned location;
523 unsigned target;
524};
525
526#endif
diff --git a/src/gallium/drivers/nvfx/nvfx_state.c b/src/gallium/drivers/nvfx/nvfx_state.c
deleted file mode 100644
index f3dcb205c61..00000000000
--- a/src/gallium/drivers/nvfx/nvfx_state.c
+++ /dev/null
@@ -1,389 +0,0 @@
1#include "pipe/p_state.h"
2#include "pipe/p_defines.h"
3#include "util/u_inlines.h"
4#include "util/u_framebuffer.h"
5
6#include "draw/draw_context.h"
7
8#include "tgsi/tgsi_parse.h"
9
10#include "nvfx_context.h"
11#include "nvfx_state.h"
12#include "nvfx_tex.h"
13
14static void *
15nvfx_blend_state_create(struct pipe_context *pipe,
16 const struct pipe_blend_state *cso)
17{
18 struct nvfx_context *nvfx = nvfx_context(pipe);
19 struct nvfx_blend_state *bso = CALLOC(1, sizeof(*bso));
20 struct nouveau_statebuf_builder sb = sb_init(bso->sb);
21
22 if (cso->rt[0].blend_enable) {
23 sb_method(sb, NV30_3D_BLEND_FUNC_ENABLE, 3);
24 sb_data(sb, 1);
25 sb_data(sb, (nvgl_blend_func(cso->rt[0].alpha_src_factor) << 16) |
26 nvgl_blend_func(cso->rt[0].rgb_src_factor));
27 sb_data(sb, nvgl_blend_func(cso->rt[0].alpha_dst_factor) << 16 |
28 nvgl_blend_func(cso->rt[0].rgb_dst_factor));
29 if(nvfx->screen->base.device->chipset < 0x40) {
30 sb_method(sb, NV30_3D_BLEND_EQUATION, 1);
31 sb_data(sb, nvgl_blend_eqn(cso->rt[0].rgb_func));
32 } else {
33 sb_method(sb, NV40_3D_BLEND_EQUATION, 1);
34 sb_data(sb, nvgl_blend_eqn(cso->rt[0].alpha_func) << 16 |
35 nvgl_blend_eqn(cso->rt[0].rgb_func));
36 }
37 } else {
38 sb_method(sb, NV30_3D_BLEND_FUNC_ENABLE, 1);
39 sb_data(sb, 0);
40 }
41
42 sb_method(sb, NV30_3D_COLOR_MASK, 1);
43 sb_data(sb, (((cso->rt[0].colormask & PIPE_MASK_A) ? (0x01 << 24) : 0) |
44 ((cso->rt[0].colormask & PIPE_MASK_R) ? (0x01 << 16) : 0) |
45 ((cso->rt[0].colormask & PIPE_MASK_G) ? (0x01 << 8) : 0) |
46 ((cso->rt[0].colormask & PIPE_MASK_B) ? (0x01 << 0) : 0)));
47
48 /* TODO: add NV40 MRT color mask */
49
50 if (cso->logicop_enable) {
51 sb_method(sb, NV30_3D_COLOR_LOGIC_OP_ENABLE, 2);
52 sb_data(sb, 1);
53 sb_data(sb, nvgl_logicop_func(cso->logicop_func));
54 } else {
55 sb_method(sb, NV30_3D_COLOR_LOGIC_OP_ENABLE, 1);
56 sb_data(sb, 0);
57 }
58
59 sb_method(sb, NV30_3D_DITHER_ENABLE, 1);
60 sb_data(sb, cso->dither ? 1 : 0);
61
62 bso->sb_len = sb_len(sb, bso->sb);
63 bso->pipe = *cso;
64 return (void *)bso;
65}
66
67static void
68nvfx_blend_state_bind(struct pipe_context *pipe, void *hwcso)
69{
70 struct nvfx_context *nvfx = nvfx_context(pipe);
71
72 nvfx->blend = hwcso;
73 nvfx->dirty |= NVFX_NEW_BLEND;
74}
75
76static void
77nvfx_blend_state_delete(struct pipe_context *pipe, void *hwcso)
78{
79 struct nvfx_blend_state *bso = hwcso;
80
81 FREE(bso);
82}
83
84static void *
85nvfx_rasterizer_state_create(struct pipe_context *pipe,
86 const struct pipe_rasterizer_state *cso)
87{
88 struct nvfx_rasterizer_state *rsso = CALLOC(1, sizeof(*rsso));
89 struct nouveau_statebuf_builder sb = sb_init(rsso->sb);
90
91 /*XXX: ignored:
92 * point_smooth -nohw
93 * multisample
94 * sprite_coord_origin
95 */
96
97 sb_method(sb, NV30_3D_SHADE_MODEL, 1);
98 sb_data(sb, cso->flatshade ? NV30_3D_SHADE_MODEL_FLAT :
99 NV30_3D_SHADE_MODEL_SMOOTH);
100
101 sb_method(sb, NV30_3D_VERTEX_TWO_SIDE_ENABLE, 1);
102 sb_data(sb, cso->light_twoside);
103
104 sb_method(sb, NV30_3D_LINE_WIDTH, 2);
105 sb_data(sb, (unsigned char)(cso->line_width * 8.0) & 0xff);
106 sb_data(sb, cso->line_smooth ? 1 : 0);
107 sb_method(sb, NV30_3D_LINE_STIPPLE_ENABLE, 2);
108 sb_data(sb, cso->line_stipple_enable ? 1 : 0);
109 sb_data(sb, (cso->line_stipple_pattern << 16) |
110 cso->line_stipple_factor);
111
112 sb_method(sb, NV30_3D_POINT_SIZE, 1);
113 sb_data(sb, fui(cso->point_size));
114
115 sb_method(sb, NV30_3D_POLYGON_MODE_FRONT, 6);
116 sb_data(sb, nvgl_polygon_mode(cso->fill_front));
117 sb_data(sb, nvgl_polygon_mode(cso->fill_back));
118 switch (cso->cull_face) {
119 case PIPE_FACE_FRONT:
120 sb_data(sb, NV30_3D_CULL_FACE_FRONT);
121 break;
122 case PIPE_FACE_BACK:
123 sb_data(sb, NV30_3D_CULL_FACE_BACK);
124 break;
125 case PIPE_FACE_FRONT_AND_BACK:
126 sb_data(sb, NV30_3D_CULL_FACE_FRONT_AND_BACK);
127 break;
128 default:
129 sb_data(sb, NV30_3D_CULL_FACE_BACK);
130 break;
131 }
132 if (cso->front_ccw) {
133 sb_data(sb, NV30_3D_FRONT_FACE_CCW);
134 } else {
135 sb_data(sb, NV30_3D_FRONT_FACE_CW);
136 }
137 sb_data(sb, cso->poly_smooth ? 1 : 0);
138 sb_data(sb, (cso->cull_face != PIPE_FACE_NONE) ? 1 : 0);
139
140 sb_method(sb, NV30_3D_POLYGON_STIPPLE_ENABLE, 1);
141 sb_data(sb, cso->poly_stipple_enable ? 1 : 0);
142
143 sb_method(sb, NV30_3D_POLYGON_OFFSET_POINT_ENABLE, 3);
144 sb_data(sb, cso->offset_point);
145 sb_data(sb, cso->offset_line);
146 sb_data(sb, cso->offset_tri);
147
148 if (cso->offset_point || cso->offset_line || cso->offset_tri) {
149 sb_method(sb, NV30_3D_POLYGON_OFFSET_FACTOR, 2);
150 sb_data(sb, fui(cso->offset_scale));
151 sb_data(sb, fui(cso->offset_units * 2));
152 }
153
154 sb_method(sb, NV30_3D_FLATSHADE_FIRST, 1);
155 sb_data(sb, cso->flatshade_first);
156
157 rsso->pipe = *cso;
158 rsso->sb_len = sb_len(sb, rsso->sb);
159 return (void *)rsso;
160}
161
162static void
163nvfx_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
164{
165 struct nvfx_context *nvfx = nvfx_context(pipe);
166
167 if(nvfx->rasterizer && hwcso)
168 {
169 if(!nvfx->rasterizer || ((struct nvfx_rasterizer_state*)hwcso)->pipe.scissor
170 != nvfx->rasterizer->pipe.scissor)
171 {
172 nvfx->dirty |= NVFX_NEW_SCISSOR;
173 nvfx->draw_dirty |= NVFX_NEW_SCISSOR;
174 }
175
176 if(((struct nvfx_rasterizer_state*)hwcso)->pipe.point_quad_rasterization != nvfx->rasterizer->pipe.point_quad_rasterization
177 || ((struct nvfx_rasterizer_state*)hwcso)->pipe.sprite_coord_enable != nvfx->rasterizer->pipe.sprite_coord_enable
178 || ((struct nvfx_rasterizer_state*)hwcso)->pipe.sprite_coord_mode != nvfx->rasterizer->pipe.sprite_coord_mode)
179 {
180 nvfx->dirty |= NVFX_NEW_SPRITE;
181 }
182 }
183
184 nvfx->rasterizer = hwcso;
185 nvfx->dirty |= NVFX_NEW_RAST;
186 nvfx->draw_dirty |= NVFX_NEW_RAST;
187}
188
189static void
190nvfx_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
191{
192 struct nvfx_rasterizer_state *rsso = hwcso;
193
194 FREE(rsso);
195}
196
197static void *
198nvfx_depth_stencil_alpha_state_create(struct pipe_context *pipe,
199 const struct pipe_depth_stencil_alpha_state *cso)
200{
201 struct nvfx_zsa_state *zsaso = CALLOC(1, sizeof(*zsaso));
202 struct nouveau_statebuf_builder sb = sb_init(zsaso->sb);
203
204 sb_method(sb, NV30_3D_DEPTH_FUNC, 1);
205 sb_data (sb, nvgl_comparison_op(cso->depth.func));
206
207 sb_method(sb, NV30_3D_ALPHA_FUNC_ENABLE, 3);
208 sb_data (sb, cso->alpha.enabled ? 1 : 0);
209 sb_data (sb, nvgl_comparison_op(cso->alpha.func));
210 sb_data (sb, float_to_ubyte(cso->alpha.ref_value));
211
212 if (cso->stencil[0].enabled) {
213 sb_method(sb, NV30_3D_STENCIL_ENABLE(0), 3);
214 sb_data (sb, cso->stencil[0].enabled ? 1 : 0);
215 sb_data (sb, cso->stencil[0].writemask);
216 sb_data (sb, nvgl_comparison_op(cso->stencil[0].func));
217 sb_method(sb, NV30_3D_STENCIL_FUNC_MASK(0), 4);
218 sb_data (sb, cso->stencil[0].valuemask);
219 sb_data (sb, nvgl_stencil_op(cso->stencil[0].fail_op));
220 sb_data (sb, nvgl_stencil_op(cso->stencil[0].zfail_op));
221 sb_data (sb, nvgl_stencil_op(cso->stencil[0].zpass_op));
222 } else {
223 sb_method(sb, NV30_3D_STENCIL_ENABLE(0), 1);
224 sb_data (sb, 0);
225 }
226
227 if (cso->stencil[1].enabled) {
228 sb_method(sb, NV30_3D_STENCIL_ENABLE(1), 3);
229 sb_data (sb, cso->stencil[1].enabled ? 1 : 0);
230 sb_data (sb, cso->stencil[1].writemask);
231 sb_data (sb, nvgl_comparison_op(cso->stencil[1].func));
232 sb_method(sb, NV30_3D_STENCIL_FUNC_MASK(1), 4);
233 sb_data (sb, cso->stencil[1].valuemask);
234 sb_data (sb, nvgl_stencil_op(cso->stencil[1].fail_op));
235 sb_data (sb, nvgl_stencil_op(cso->stencil[1].zfail_op));
236 sb_data (sb, nvgl_stencil_op(cso->stencil[1].zpass_op));
237 } else {
238 sb_method(sb, NV30_3D_STENCIL_ENABLE(1), 1);
239 sb_data (sb, 0);
240 }
241
242 zsaso->pipe = *cso;
243 zsaso->sb_len = sb_len(sb, zsaso->sb);
244 return (void *)zsaso;
245}
246
247static void
248nvfx_depth_stencil_alpha_state_bind(struct pipe_context *pipe, void *hwcso)
249{
250 struct nvfx_context *nvfx = nvfx_context(pipe);
251
252 nvfx->zsa = hwcso;
253 nvfx->dirty |= NVFX_NEW_ZSA;
254}
255
256static void
257nvfx_depth_stencil_alpha_state_delete(struct pipe_context *pipe, void *hwcso)
258{
259 struct nvfx_zsa_state *zsaso = hwcso;
260
261 FREE(zsaso);
262}
263
264static void
265nvfx_set_blend_color(struct pipe_context *pipe,
266 const struct pipe_blend_color *bcol)
267{
268 struct nvfx_context *nvfx = nvfx_context(pipe);
269
270 nvfx->blend_colour = *bcol;
271 nvfx->dirty |= NVFX_NEW_BCOL;
272}
273
274static void
275nvfx_set_stencil_ref(struct pipe_context *pipe,
276 const struct pipe_stencil_ref *sr)
277{
278 struct nvfx_context *nvfx = nvfx_context(pipe);
279
280 nvfx->stencil_ref = *sr;
281 nvfx->dirty |= NVFX_NEW_SR;
282}
283
284static void
285nvfx_set_clip_state(struct pipe_context *pipe,
286 const struct pipe_clip_state *clip)
287{
288 struct nvfx_context *nvfx = nvfx_context(pipe);
289
290 nvfx->clip = *clip;
291 nvfx->dirty |= NVFX_NEW_UCP;
292 nvfx->draw_dirty |= NVFX_NEW_UCP;
293}
294
295static void
296nvfx_set_sample_mask(struct pipe_context *pipe,
297 unsigned sample_mask)
298{
299}
300
301static void
302nvfx_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index,
303 struct pipe_resource *buf )
304{
305 struct nvfx_context *nvfx = nvfx_context(pipe);
306
307 pipe_resource_reference(&nvfx->constbuf[shader], buf);
308 nvfx->constbuf_nr[shader] = buf ? (buf->width0 / (4 * sizeof(float))) : 0;
309
310 if (shader == PIPE_SHADER_VERTEX) {
311 nvfx->dirty |= NVFX_NEW_VERTCONST;
312 } else
313 if (shader == PIPE_SHADER_FRAGMENT) {
314 nvfx->dirty |= NVFX_NEW_FRAGCONST;
315 }
316}
317
318static void
319nvfx_set_framebuffer_state(struct pipe_context *pipe,
320 const struct pipe_framebuffer_state *fb)
321{
322 struct nvfx_context *nvfx = nvfx_context(pipe);
323
324 if(fb)
325 util_copy_framebuffer_state(&nvfx->framebuffer, fb);
326 else
327 util_unreference_framebuffer_state(&nvfx->framebuffer);
328 nvfx->dirty |= NVFX_NEW_FB;
329}
330
331static void
332nvfx_set_polygon_stipple(struct pipe_context *pipe,
333 const struct pipe_poly_stipple *stipple)
334{
335 struct nvfx_context *nvfx = nvfx_context(pipe);
336
337 memcpy(nvfx->stipple, stipple->stipple, 4 * 32);
338 nvfx->dirty |= NVFX_NEW_STIPPLE;
339}
340
341static void
342nvfx_set_scissor_state(struct pipe_context *pipe,
343 const struct pipe_scissor_state *s)
344{
345 struct nvfx_context *nvfx = nvfx_context(pipe);
346
347 nvfx->scissor = *s;
348 nvfx->dirty |= NVFX_NEW_SCISSOR;
349}
350
351static void
352nvfx_set_viewport_state(struct pipe_context *pipe,
353 const struct pipe_viewport_state *vpt)
354{
355 struct nvfx_context *nvfx = nvfx_context(pipe);
356
357 nvfx->viewport = *vpt;
358 nvfx->dirty |= NVFX_NEW_VIEWPORT;
359 nvfx->draw_dirty |= NVFX_NEW_VIEWPORT;
360}
361
362void
363nvfx_init_state_functions(struct nvfx_context *nvfx)
364{
365 nvfx->pipe.create_blend_state = nvfx_blend_state_create;
366 nvfx->pipe.bind_blend_state = nvfx_blend_state_bind;
367 nvfx->pipe.delete_blend_state = nvfx_blend_state_delete;
368
369 nvfx->pipe.create_rasterizer_state = nvfx_rasterizer_state_create;
370 nvfx->pipe.bind_rasterizer_state = nvfx_rasterizer_state_bind;
371 nvfx->pipe.delete_rasterizer_state = nvfx_rasterizer_state_delete;
372
373 nvfx->pipe.create_depth_stencil_alpha_state =
374 nvfx_depth_stencil_alpha_state_create;
375 nvfx->pipe.bind_depth_stencil_alpha_state =
376 nvfx_depth_stencil_alpha_state_bind;
377 nvfx->pipe.delete_depth_stencil_alpha_state =
378 nvfx_depth_stencil_alpha_state_delete;
379
380 nvfx->pipe.set_blend_color = nvfx_set_blend_color;
381 nvfx->pipe.set_stencil_ref = nvfx_set_stencil_ref;
382 nvfx->pipe.set_clip_state = nvfx_set_clip_state;
383 nvfx->pipe.set_sample_mask = nvfx_set_sample_mask;
384 nvfx->pipe.set_constant_buffer = nvfx_set_constant_buffer;
385 nvfx->pipe.set_framebuffer_state = nvfx_set_framebuffer_state;
386 nvfx->pipe.set_polygon_stipple = nvfx_set_polygon_stipple;
387 nvfx->pipe.set_scissor_state = nvfx_set_scissor_state;
388 nvfx->pipe.set_viewport_state = nvfx_set_viewport_state;
389}
diff --git a/src/gallium/drivers/nvfx/nvfx_state.h b/src/gallium/drivers/nvfx/nvfx_state.h
deleted file mode 100644
index 15e1cbb1986..00000000000
--- a/src/gallium/drivers/nvfx/nvfx_state.h
+++ /dev/null
@@ -1,115 +0,0 @@
1#ifndef __NVFX_STATE_H__
2#define __NVFX_STATE_H__
3
4#include "pipe/p_state.h"
5#include "pipe/p_video_state.h"
6#include "tgsi/tgsi_scan.h"
7#include "nouveau/nouveau_statebuf.h"
8#include "util/u_dynarray.h"
9#include "util/u_linkage.h"
10
11struct nvfx_vertex_program_exec {
12 uint32_t data[4];
13};
14
15struct nvfx_vertex_program_data {
16 int index; /* immediates == -1 */
17 float value[4];
18};
19
20struct nvfx_vertex_program {
21 unsigned long long id;
22
23 struct nvfx_vertex_program_exec *insns;
24 unsigned nr_insns;
25 struct nvfx_vertex_program_data *consts;
26 unsigned nr_consts;
27
28 char generic_to_fp_input[256];
29 int sprite_fp_input;
30
31 struct nouveau_resource *exec;
32 unsigned exec_start;
33 struct nouveau_resource *data;
34 unsigned data_start;
35 unsigned data_start_min;
36
37 uint32_t ir;
38 uint32_t or;
39 int clip_nr;
40
41 struct util_dynarray branch_relocs;
42 struct util_dynarray const_relocs;
43};
44
45#define NVFX_VP_FAILED ((struct nvfx_vertex_program*)-1)
46
47struct nvfx_pipe_vertex_program {
48 struct pipe_shader_state pipe;
49 struct tgsi_shader_info info;
50
51 unsigned draw_elements;
52 boolean draw_no_elements;
53 struct draw_vertex_shader *draw_vs;
54 struct nvfx_vertex_program* draw_vp;
55
56 struct nvfx_vertex_program* vp;
57};
58
59struct nvfx_fragment_program_data {
60 unsigned offset;
61 unsigned index;
62};
63
64struct nvfx_fragment_program_bo {
65 struct nvfx_fragment_program_bo* next;
66 struct nouveau_bo* bo;
67 unsigned char* slots;
68 char insn[] __attribute__((aligned(16)));
69};
70
71struct nvfx_fragment_program {
72 unsigned samplers;
73 unsigned point_sprite_control;
74 unsigned or;
75 unsigned coord_conventions;
76
77 uint32_t *insn;
78 int insn_len;
79
80 struct nvfx_fragment_program_data *consts;
81 unsigned nr_consts;
82
83 /* the slot at num_slots is for the sprite coordinate, if any */
84 unsigned num_slots; /* how many input semantics? */
85 unsigned char slot_to_generic[10]; /* semantics */
86 unsigned char slot_to_fp_input[11]; /* current assignment of slots for each used semantic */
87 struct util_dynarray slot_relocations[11];
88
89 /* This is reset to progs on any relocation update, and decreases every time we
90 * move to a new prog due to a constant update
91 * When this is the same as progs, applying relocations is no longer necessary.
92 */
93 unsigned progs_left_with_obsolete_slot_assignments;
94
95 unsigned long long last_vp_id;
96 unsigned last_sprite_coord_enable;
97
98 uint32_t fp_control;
99
100 unsigned bo_prog_idx;
101 unsigned prog_size;
102 unsigned progs_per_bo;
103 unsigned progs;
104
105 struct nvfx_fragment_program_bo* fpbo;
106};
107
108struct nvfx_pipe_fragment_program {
109 struct pipe_shader_state pipe;
110 struct tgsi_shader_info info;
111
112 struct nvfx_fragment_program* fps[2];
113};
114
115#endif
diff --git a/src/gallium/drivers/nvfx/nvfx_state_emit.c b/src/gallium/drivers/nvfx/nvfx_state_emit.c
deleted file mode 100644
index 60ed2d0a4c6..00000000000
--- a/src/gallium/drivers/nvfx/nvfx_state_emit.c
+++ /dev/null
@@ -1,439 +0,0 @@
1#include "nvfx_context.h"
2#include "nvfx_state.h"
3#include "nvfx_resource.h"
4#include "draw/draw_context.h"
5
6void
7nvfx_state_viewport_validate(struct nvfx_context *nvfx)
8{
9 struct nouveau_channel *chan = nvfx->screen->base.channel;
10 struct nouveau_grobj *eng3d = nvfx->screen->eng3d;
11 struct pipe_viewport_state *vpt = &nvfx->viewport;
12
13 if(nvfx->render_mode == HW) {
14 BEGIN_RING(chan, eng3d, NV30_3D_VIEWPORT_TRANSLATE_X, 8);
15 OUT_RINGf(chan, vpt->translate[0]);
16 OUT_RINGf(chan, vpt->translate[1]);
17 OUT_RINGf(chan, vpt->translate[2]);
18 OUT_RINGf(chan, vpt->translate[3]);
19 OUT_RINGf(chan, vpt->scale[0]);
20 OUT_RINGf(chan, vpt->scale[1]);
21 OUT_RINGf(chan, vpt->scale[2]);
22 OUT_RINGf(chan, vpt->scale[3]);
23 BEGIN_RING(chan, eng3d, 0x1d78, 1);
24 OUT_RING(chan, 1);
25 } else {
26 BEGIN_RING(chan, eng3d, NV30_3D_VIEWPORT_TRANSLATE_X, 8);
27 OUT_RINGf(chan, 0.0f);
28 OUT_RINGf(chan, 0.0f);
29 OUT_RINGf(chan, 0.0f);
30 OUT_RINGf(chan, 0.0f);
31 OUT_RINGf(chan, 1.0f);
32 OUT_RINGf(chan, 1.0f);
33 OUT_RINGf(chan, 1.0f);
34 OUT_RINGf(chan, 1.0f);
35 BEGIN_RING(chan, eng3d, 0x1d78, 1);
36 OUT_RING(chan, nvfx->is_nv4x ? 0x110 : 1);
37 }
38}
39
40void
41nvfx_state_scissor_validate(struct nvfx_context *nvfx)
42{
43 struct nouveau_channel *chan = nvfx->screen->base.channel;
44 struct nouveau_grobj *eng3d = nvfx->screen->eng3d;
45 struct pipe_rasterizer_state *rast = &nvfx->rasterizer->pipe;
46 struct pipe_scissor_state *s = &nvfx->scissor;
47
48 if ((rast->scissor == 0 && nvfx->state.scissor_enabled == 0))
49 return;
50 nvfx->state.scissor_enabled = rast->scissor;
51
52 BEGIN_RING(chan, eng3d, NV30_3D_SCISSOR_HORIZ, 2);
53 if (nvfx->state.scissor_enabled) {
54 OUT_RING(chan, ((s->maxx - s->minx) << 16) | s->minx);
55 OUT_RING(chan, ((s->maxy - s->miny) << 16) | s->miny);
56 } else {
57 OUT_RING(chan, 4096 << 16);
58 OUT_RING(chan, 4096 << 16);
59 }
60}
61
62void
63nvfx_state_sr_validate(struct nvfx_context *nvfx)
64{
65 struct nouveau_channel* chan = nvfx->screen->base.channel;
66 struct nouveau_grobj *eng3d = nvfx->screen->eng3d;
67 struct pipe_stencil_ref *sr = &nvfx->stencil_ref;
68
69 BEGIN_RING(chan, eng3d, NV30_3D_STENCIL_FUNC_REF(0), 1);
70 OUT_RING(chan, sr->ref_value[0]);
71 BEGIN_RING(chan, eng3d, NV30_3D_STENCIL_FUNC_REF(1), 1);
72 OUT_RING(chan, sr->ref_value[1]);
73}
74
75void
76nvfx_state_blend_colour_validate(struct nvfx_context *nvfx)
77{
78 struct nouveau_channel* chan = nvfx->screen->base.channel;
79 struct nouveau_grobj *eng3d = nvfx->screen->eng3d;
80 struct pipe_blend_color *bcol = &nvfx->blend_colour;
81
82 BEGIN_RING(chan, eng3d, NV30_3D_BLEND_COLOR, 1);
83 OUT_RING(chan, ((float_to_ubyte(bcol->color[3]) << 24) |
84 (float_to_ubyte(bcol->color[0]) << 16) |
85 (float_to_ubyte(bcol->color[1]) << 8) |
86 (float_to_ubyte(bcol->color[2]) << 0)));
87}
88
89void
90nvfx_state_stipple_validate(struct nvfx_context *nvfx)
91{
92 struct nouveau_channel *chan = nvfx->screen->base.channel;
93 struct nouveau_grobj *eng3d = nvfx->screen->eng3d;
94
95 BEGIN_RING(chan, eng3d, NV30_3D_POLYGON_STIPPLE_PATTERN(0), 32);
96 OUT_RINGp(chan, nvfx->stipple, 32);
97}
98
99static void
100nvfx_coord_conventions_validate(struct nvfx_context* nvfx)
101{
102 struct nouveau_channel* chan = nvfx->screen->base.channel;
103 struct nouveau_grobj *eng3d = nvfx->screen->eng3d;
104 unsigned value = nvfx->hw_fragprog->coord_conventions;
105 if(value & NV30_3D_COORD_CONVENTIONS_ORIGIN_INVERTED)
106 value |= nvfx->framebuffer.height << NV30_3D_COORD_CONVENTIONS_HEIGHT__SHIFT;
107
108 BEGIN_RING(chan, eng3d, NV30_3D_COORD_CONVENTIONS, 1);
109 OUT_RING(chan, value);
110}
111
112static void
113nvfx_ucp_validate(struct nvfx_context* nvfx)
114{
115 struct nouveau_channel* chan = nvfx->screen->base.channel;
116 struct nouveau_grobj *eng3d = nvfx->screen->eng3d;
117 unsigned enables[] =
118 {
119 NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE0,
120 NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE1,
121 NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE2,
122 NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE3,
123 NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE4,
124 NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE5
125 };
126 unsigned i, enable = 0, nr = 0;
127
128 for (i = 0; i < 6; i++) {
129 if (nvfx->rasterizer->pipe.clip_plane_enable & (1 << i)) {
130 enable |= enables[i];
131 nr = i+1;
132 }
133 }
134
135 if(!nvfx->use_vp_clipping)
136 {
137 BEGIN_RING(chan, eng3d, NV30_3D_VP_CLIP_PLANES_ENABLE, 1);
138 OUT_RING(chan, 0);
139
140 BEGIN_RING(chan, eng3d, NV30_3D_VP_CLIP_PLANE(0, 0),
141 nr * 4);
142 OUT_RINGp(chan, &nvfx->clip.ucp[0][0], nr * 4);
143 }
144
145 BEGIN_RING(chan, eng3d, NV30_3D_VP_CLIP_PLANES_ENABLE, 1);
146 OUT_RING(chan, enable);
147}
148
149static void
150nvfx_vertprog_ucp_validate(struct nvfx_context* nvfx)
151{
152 struct nouveau_channel* chan = nvfx->screen->base.channel;
153 struct nouveau_grobj *eng3d = nvfx->screen->eng3d;
154 unsigned i;
155 struct nvfx_vertex_program* vp = nvfx->hw_vertprog;
156 unsigned enable = nvfx->rasterizer->pipe.clip_plane_enable;
157 unsigned nr = util_bitcount(enable);
158
159 if(nr != vp->clip_nr)
160 {
161 unsigned idx;
162
163 /* remove last instruction bit */
164 if(vp->clip_nr >= 0)
165 {
166 idx = vp->nr_insns - 7 + vp->clip_nr;
167 BEGIN_RING(chan, eng3d, NV30_3D_VP_UPLOAD_FROM_ID, 1);
168 OUT_RING(chan, vp->exec->start + idx);
169 BEGIN_RING(chan, eng3d, NV30_3D_VP_UPLOAD_INST(0), 4);
170 OUT_RINGp (chan, vp->insns[idx].data, 4);
171 }
172
173 /* set last instruction bit */
174 idx = vp->nr_insns - 7 + nr;
175 BEGIN_RING(chan, eng3d, NV30_3D_VP_UPLOAD_FROM_ID, 1);
176 OUT_RING(chan, vp->exec->start + idx);
177 BEGIN_RING(chan, eng3d, NV30_3D_VP_UPLOAD_INST(0), 4);
178 OUT_RINGp(chan, vp->insns[idx].data, 3);
179 OUT_RING(chan, vp->insns[idx].data[3] | 1);
180 vp->clip_nr = nr;
181 }
182
183 // TODO: only do this for the ones changed
184 for(i = 0; enable; ++i)
185 {
186 unsigned index = ffs(enable) - 1;
187 enable &= ~(1 << index);
188
189 BEGIN_RING(chan, eng3d, NV30_3D_VP_UPLOAD_CONST_ID, 5);
190 OUT_RING(chan, vp->data->start + i);
191 OUT_RINGp (chan, nvfx->clip.ucp[index], 4);
192 }
193}
194
195static boolean
196nvfx_state_validate_common(struct nvfx_context *nvfx)
197{
198 struct nouveau_channel* chan = nvfx->screen->base.channel;
199 struct nouveau_grobj *eng3d = nvfx->screen->eng3d;
200 unsigned dirty;
201 unsigned still_dirty = 0;
202 boolean flush_tex_cache = FALSE;
203
204 if(nvfx != nvfx->screen->cur_ctx)
205 {
206 nvfx->dirty = ~0;
207 nvfx->hw_vtxelt_nr = 16;
208 nvfx->hw_pointsprite_control = -1;
209 nvfx->hw_vp_output = -1;
210 nvfx->screen->cur_ctx = nvfx;
211 nvfx->relocs_needed = NVFX_RELOCATE_ALL;
212 }
213
214 dirty = nvfx->dirty;
215
216 if(nvfx->render_mode == HW)
217 {
218 if(dirty & (NVFX_NEW_VERTPROG | NVFX_NEW_VERTCONST))
219 {
220 if(!nvfx_vertprog_validate(nvfx))
221 return FALSE;
222 }
223
224 if(dirty & NVFX_NEW_ARRAYS)
225 {
226 if(!nvfx_vbo_validate(nvfx))
227 return FALSE;
228 }
229
230 if(dirty & NVFX_NEW_INDEX)
231 {
232 if(nvfx->use_index_buffer)
233 nvfx_idxbuf_validate(nvfx);
234 else
235 still_dirty = NVFX_NEW_INDEX;
236 }
237 }
238 else
239 {
240 if(dirty & NVFX_NEW_VERTPROG) {
241 assert(nvfx_vertprog_validate(nvfx));
242 nvfx_vbo_swtnl_validate(nvfx);
243 }
244 }
245
246 if(dirty & NVFX_NEW_SAMPLER) {
247 /* XXX: we take the big hammer here, I have no idea why this is needed
248 to make this work properly */
249 nvfx->dirty &= ~NVFX_NEW_SAMPLER;
250 nvfx_fragtex_validate(nvfx);
251
252 // TODO: only set this if really necessary
253 flush_tex_cache = TRUE;
254 }
255
256 if(dirty & NVFX_NEW_RAST)
257 sb_emit(chan, nvfx->rasterizer->sb, nvfx->rasterizer->sb_len);
258
259 if(dirty & NVFX_NEW_SCISSOR)
260 nvfx_state_scissor_validate(nvfx);
261
262 if(dirty & NVFX_NEW_STIPPLE)
263 nvfx_state_stipple_validate(nvfx);
264
265 if(nvfx->dirty & (NVFX_NEW_UCP | NVFX_NEW_RAST))
266 nvfx_ucp_validate(nvfx);
267
268 if(nvfx->use_vp_clipping && (nvfx->dirty &
269 (NVFX_NEW_UCP | NVFX_NEW_VERTPROG |
270 NVFX_NEW_RAST)))
271 nvfx_vertprog_ucp_validate(nvfx);
272
273 if(dirty & (NVFX_NEW_FRAGPROG | NVFX_NEW_FRAGCONST |
274 NVFX_NEW_VERTPROG | NVFX_NEW_SPRITE))
275 {
276 nvfx_fragprog_validate(nvfx);
277 if(dirty & NVFX_NEW_FRAGPROG)
278 flush_tex_cache = TRUE; // TODO: do we need this?
279 }
280
281 if(nvfx->is_nv4x)
282 {
283 unsigned vp_output = nvfx->hw_vertprog->or | nvfx->hw_fragprog->or;
284 vp_output |= ((1 << (nvfx->rasterizer->pipe.clip_plane_enable & 63)) - 1) << 6;
285
286 if(vp_output != nvfx->hw_vp_output)
287 {
288 BEGIN_RING(chan, eng3d, NV40_3D_VP_RESULT_EN, 1);
289 OUT_RING(chan, vp_output);
290 nvfx->hw_vp_output = vp_output;
291 }
292 }
293
294 if(dirty & NVFX_NEW_FB)
295 nvfx_framebuffer_validate(nvfx);
296
297 if(dirty & NVFX_NEW_BLEND)
298 sb_emit(chan, nvfx->blend->sb, nvfx->blend->sb_len);
299
300 if(dirty & NVFX_NEW_BCOL)
301 nvfx_state_blend_colour_validate(nvfx);
302
303 if(dirty & NVFX_NEW_ZSA)
304 sb_emit(chan, nvfx->zsa->sb, nvfx->zsa->sb_len);
305
306 if(dirty & NVFX_NEW_SR)
307 nvfx_state_sr_validate(nvfx);
308
309 /* XXX: nv3x needs viewport revalidation after RAST or ZSA change */
310 if(dirty & (NVFX_NEW_VIEWPORT | NVFX_NEW_RAST | NVFX_NEW_ZSA))
311 {
312 nvfx_state_viewport_validate(nvfx);
313 }
314
315 if(dirty & (NVFX_NEW_ZSA | NVFX_NEW_FB))
316 {
317 BEGIN_RING(chan, eng3d, NV30_3D_DEPTH_WRITE_ENABLE, 2);
318 OUT_RING(chan, nvfx->framebuffer.zsbuf &&
319 nvfx->zsa->pipe.depth.writemask);
320 OUT_RING(chan, nvfx->framebuffer.zsbuf &&
321 nvfx->zsa->pipe.depth.enabled);
322 }
323
324 if(dirty & (NVFX_NEW_FRAGPROG | NVFX_NEW_FB))
325 nvfx_coord_conventions_validate(nvfx);
326
327 if(flush_tex_cache && nvfx->is_nv4x)
328 {
329 BEGIN_RING(chan, eng3d, NV40_3D_TEX_CACHE_CTL, 1);
330 OUT_RING(chan, 2);
331 BEGIN_RING(chan, eng3d, NV40_3D_TEX_CACHE_CTL, 1);
332 OUT_RING(chan, 1);
333 }
334
335 nvfx->dirty = dirty & still_dirty;
336
337 return TRUE;
338}
339
340inline void
341nvfx_state_relocate(struct nvfx_context *nvfx, unsigned relocs)
342{
343 struct nouveau_channel* chan = nvfx->screen->base.channel;
344 /* we need to ensure there is enough space to output relocations in one go */
345 const unsigned max_relocs = 0
346 + 16 /* vertex buffers, incl. dma flag */
347 + 2 /* index buffer plus format+dma flag */
348 + 2 * 5 /* 4 cbufs + zsbuf, plus dma objects */
349 + 2 * 16 /* fragment textures plus format+dma flag */
350 + 2 * 4 /* vertex textures plus format+dma flag */
351 + 1 /* fragprog incl dma flag */
352 ;
353
354 MARK_RING(chan, max_relocs * 2, max_relocs * 2);
355
356 if(relocs & NVFX_RELOCATE_FRAMEBUFFER)
357 nvfx_framebuffer_relocate(nvfx);
358 if(relocs & NVFX_RELOCATE_FRAGTEX)
359 nvfx_fragtex_relocate(nvfx);
360 if(relocs & NVFX_RELOCATE_FRAGPROG)
361 nvfx_fragprog_relocate(nvfx);
362 if(relocs & NVFX_RELOCATE_VTXBUF)
363 nvfx_vbo_relocate(nvfx);
364 if(relocs & NVFX_RELOCATE_IDXBUF)
365 nvfx_idxbuf_relocate(nvfx);
366}
367
368boolean
369nvfx_state_validate(struct nvfx_context *nvfx)
370{
371 if (nvfx->render_mode != HW) {
372 /* Don't even bother trying to go back to hw if none
373 * of the states that caused swtnl previously have changed.
374 */
375 if ((nvfx->fallback_swtnl & nvfx->dirty)
376 != nvfx->fallback_swtnl)
377 return FALSE;
378
379 /* Attempt to go to hwtnl again */
380 nvfx->dirty |= (NVFX_NEW_VIEWPORT |
381 NVFX_NEW_VERTPROG |
382 NVFX_NEW_ARRAYS);
383 nvfx->render_mode = HW;
384 }
385
386 if(!nvfx_state_validate_common(nvfx))
387 return FALSE;
388
389 return TRUE;
390}
391
392boolean
393nvfx_state_validate_swtnl(struct nvfx_context *nvfx)
394{
395 struct draw_context *draw = nvfx->draw;
396
397 /* Setup for swtnl */
398 if (nvfx->render_mode == HW) {
399 static boolean warned = FALSE;
400 if(!warned) {
401 NOUVEAU_ERR("hw->swtnl 0x%08x\n", nvfx->fallback_swtnl);
402 warned = TRUE;
403 }
404 nvfx->pipe.flush(&nvfx->pipe, NULL);
405 nvfx->dirty |= (NVFX_NEW_VIEWPORT |
406 NVFX_NEW_VERTPROG |
407 NVFX_NEW_ARRAYS);
408 nvfx->render_mode = SWTNL;
409 }
410
411 if (nvfx->draw_dirty & NVFX_NEW_VERTPROG) {
412 if(!nvfx->vertprog->draw_vs)
413 nvfx->vertprog->draw_vs = draw_create_vertex_shader(draw, &nvfx->vertprog->pipe);
414 draw_bind_vertex_shader(draw, nvfx->vertprog->draw_vs);
415 }
416
417 if (nvfx->draw_dirty & NVFX_NEW_RAST)
418 draw_set_rasterizer_state(draw, &nvfx->rasterizer->pipe,
419 nvfx->rasterizer);
420
421 if (nvfx->draw_dirty & NVFX_NEW_UCP)
422 draw_set_clip_state(draw, &nvfx->clip);
423
424 if (nvfx->draw_dirty & NVFX_NEW_VIEWPORT)
425 draw_set_viewport_state(draw, &nvfx->viewport);
426
427 if (nvfx->draw_dirty & NVFX_NEW_ARRAYS) {
428 draw_set_vertex_buffers(draw, nvfx->vtxbuf_nr, nvfx->vtxbuf);
429 draw_set_vertex_elements(draw, nvfx->vtxelt->num_elements, nvfx->vtxelt->pipe);
430 }
431
432 if (nvfx->draw_dirty & NVFX_NEW_INDEX)
433 draw_set_index_buffer(draw, &nvfx->idxbuf);
434
435 nvfx_state_validate_common(nvfx);
436
437 nvfx->draw_dirty = 0;
438 return TRUE;
439}
diff --git a/src/gallium/drivers/nvfx/nvfx_state_fb.c b/src/gallium/drivers/nvfx/nvfx_state_fb.c
deleted file mode 100644
index ffc0844ea03..00000000000
--- a/src/gallium/drivers/nvfx/nvfx_state_fb.c
+++ /dev/null
@@ -1,290 +0,0 @@
1#include "nvfx_context.h"
2#include "nvfx_resource.h"
3#include "util/u_format.h"
4
5static inline boolean
6nvfx_surface_linear_target(struct pipe_surface* surf)
7{
8 return !!((struct nvfx_miptree*)surf->texture)->linear_pitch;
9}
10
11static void
12nvfx_surface_get_render_target(struct pipe_surface* surf,
13 struct nvfx_render_target* target)
14{
15 struct nvfx_surface* ns = (struct nvfx_surface*)surf;
16
17 target->bo = ((struct nvfx_miptree*)surf->texture)->base.bo;
18 target->offset = ns->offset;
19 target->pitch = align(ns->pitch, 64);
20 assert(target->pitch);
21}
22
23void
24nvfx_framebuffer_validate(struct nvfx_context *nvfx)
25{
26 struct pipe_framebuffer_state *fb = &nvfx->framebuffer;
27 struct nouveau_channel *chan = nvfx->screen->base.channel;
28 struct nouveau_grobj *eng3d = nvfx->screen->eng3d;
29 uint32_t rt_enable, rt_format;
30 int i;
31 unsigned rt_flags = NOUVEAU_BO_RDWR | NOUVEAU_BO_VRAM;
32 unsigned w = fb->width;
33 unsigned h = fb->height;
34 int all_swizzled =1 , cb_format = 0;
35
36 /* do some sanity checks on the render target state and check if the targets
37 * are swizzled
38 */
39 nvfx->is_nv4x ? assert(fb->nr_cbufs <= 4) : assert(fb->nr_cbufs <= 1);
40 if(fb->nr_cbufs && fb->zsbuf)
41 assert(util_format_get_blocksize(fb->cbufs[0]->format) ==
42 util_format_get_blocksize(fb->zsbuf->format));
43
44 for(i = 0; i < fb->nr_cbufs; i++) {
45 if(cb_format)
46 assert(cb_format == fb->cbufs[i]->format);
47 else
48 cb_format = fb->cbufs[i]->format;
49
50 if(nvfx_surface_linear_target(fb->cbufs[i]))
51 all_swizzled = 0;
52 }
53
54 if(fb->zsbuf && nvfx_surface_linear_target(fb->zsbuf))
55 all_swizzled = 0;
56
57 rt_enable = (NV30_3D_RT_ENABLE_COLOR0 << fb->nr_cbufs) - 1;
58 if(rt_enable & (NV30_3D_RT_ENABLE_COLOR1 |
59 NV40_3D_RT_ENABLE_COLOR2 | NV40_3D_RT_ENABLE_COLOR3))
60 rt_enable |= NV30_3D_RT_ENABLE_MRT;
61
62 for(i = 0; i < fb->nr_cbufs; i++)
63 nvfx_surface_get_render_target(fb->cbufs[i], &nvfx->hw_rt[i]);
64
65 for(; i < 4; ++i)
66 nvfx->hw_rt[i].bo = NULL;
67
68 nvfx->hw_zeta.bo = NULL;
69
70 if(fb->zsbuf) {
71 nvfx_surface_get_render_target(fb->zsbuf, &nvfx->hw_zeta);
72 assert(util_format_get_stride(fb->zsbuf->format, fb->width) <=
73 nvfx->hw_zeta.pitch);
74 }
75
76 if(all_swizzled) {
77 /* hardware rounds down render target offset to 64 bytes,
78 * but surfaces with a size of 2x2 pixel (16bpp) or 1x1 pixel (32bpp)
79 * have an unaligned start address, for those two important square
80 * formats we can hack around this limitation by adjusting the viewport
81 */
82 if(nvfx->hw_rt[0].offset & 63) {
83 int delta = nvfx->hw_rt[0].offset & 63;
84 h = 2;
85 w = 16;
86 nvfx->viewport.translate[0] += delta /
87 (util_format_get_blocksize(fb->cbufs[0]->format) * 2);
88 nvfx->dirty |= NVFX_NEW_VIEWPORT;
89 }
90
91 rt_format = NV30_3D_RT_FORMAT_TYPE_SWIZZLED |
92 (util_logbase2(w) << NV30_3D_RT_FORMAT_LOG2_WIDTH__SHIFT) |
93 (util_logbase2(h) << NV30_3D_RT_FORMAT_LOG2_HEIGHT__SHIFT);
94 } else {
95 rt_format = NV30_3D_RT_FORMAT_TYPE_LINEAR;
96 }
97
98 if(fb->nr_cbufs > 0) {
99 switch (fb->cbufs[0]->format) {
100 case PIPE_FORMAT_B8G8R8X8_UNORM:
101 rt_format |= NV30_3D_RT_FORMAT_COLOR_X8R8G8B8;
102 break;
103 case PIPE_FORMAT_B8G8R8A8_UNORM:
104 case 0:
105 rt_format |= NV30_3D_RT_FORMAT_COLOR_A8R8G8B8;
106 break;
107 case PIPE_FORMAT_R8G8B8X8_UNORM:
108 rt_format |= NV30_3D_RT_FORMAT_COLOR_X8B8G8R8;
109 break;
110 case PIPE_FORMAT_R8G8B8A8_UNORM:
111 rt_format |= NV30_3D_RT_FORMAT_COLOR_A8B8G8R8;
112 break;
113 case PIPE_FORMAT_B5G6R5_UNORM:
114 rt_format |= NV30_3D_RT_FORMAT_COLOR_R5G6B5;
115 break;
116 case PIPE_FORMAT_R32G32B32A32_FLOAT:
117 rt_format |= NV30_3D_RT_FORMAT_COLOR_A32B32G32R32_FLOAT;
118 break;
119 case PIPE_FORMAT_R16G16B16A16_FLOAT:
120 rt_format |= NV30_3D_RT_FORMAT_COLOR_A16B16G16R16_FLOAT;
121 break;
122 default:
123 assert(0);
124 }
125 } else if(fb->zsbuf && util_format_get_blocksize(fb->zsbuf->format) == 2)
126 rt_format |= NV30_3D_RT_FORMAT_COLOR_R5G6B5;
127 else
128 rt_format |= NV30_3D_RT_FORMAT_COLOR_A8R8G8B8;
129
130 if(fb->zsbuf) {
131 switch (fb->zsbuf->format) {
132 case PIPE_FORMAT_Z16_UNORM:
133 rt_format |= NV30_3D_RT_FORMAT_ZETA_Z16;
134 break;
135 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
136 case PIPE_FORMAT_X8Z24_UNORM:
137 case 0:
138 rt_format |= NV30_3D_RT_FORMAT_ZETA_Z24S8;
139 break;
140 default:
141 assert(0);
142 }
143 } else if(fb->nr_cbufs && util_format_get_blocksize(fb->cbufs[0]->format) == 2)
144 rt_format |= NV30_3D_RT_FORMAT_ZETA_Z16;
145 else
146 rt_format |= NV30_3D_RT_FORMAT_ZETA_Z24S8;
147
148 MARK_RING(chan, 42, 10);
149
150 if ((rt_enable & NV30_3D_RT_ENABLE_COLOR0) || fb->zsbuf) {
151 struct nvfx_render_target *rt0 = &nvfx->hw_rt[0];
152 uint32_t pitch;
153
154 if(!(rt_enable & NV30_3D_RT_ENABLE_COLOR0))
155 rt0 = &nvfx->hw_zeta;
156
157 pitch = rt0->pitch;
158
159 if(!nvfx->is_nv4x)
160 {
161 if (nvfx->hw_zeta.bo)
162 pitch |= (nvfx->hw_zeta.pitch << 16);
163 else
164 pitch |= (pitch << 16);
165 }
166
167 //printf("rendering to bo %p [%i] at offset %i with pitch %i\n", rt0->bo, rt0->bo->handle, rt0->offset, pitch);
168
169 BEGIN_RING(chan, eng3d, NV30_3D_DMA_COLOR0, 1);
170 OUT_RELOC(chan, rt0->bo, 0,
171 rt_flags | NOUVEAU_BO_OR,
172 chan->vram->handle, chan->gart->handle);
173 BEGIN_RING(chan, eng3d, NV30_3D_COLOR0_PITCH, 2);
174 OUT_RING(chan, pitch);
175 OUT_RELOC(chan, rt0->bo,
176 rt0->offset, rt_flags | NOUVEAU_BO_LOW,
177 0, 0);
178 }
179
180 if (rt_enable & NV30_3D_RT_ENABLE_COLOR1) {
181 BEGIN_RING(chan, eng3d, NV30_3D_DMA_COLOR1, 1);
182 OUT_RELOC(chan, nvfx->hw_rt[1].bo, 0,
183 rt_flags | NOUVEAU_BO_OR,
184 chan->vram->handle, chan->gart->handle);
185 BEGIN_RING(chan, eng3d, NV30_3D_COLOR1_OFFSET, 2);
186 OUT_RELOC(chan, nvfx->hw_rt[1].bo,
187 nvfx->hw_rt[1].offset, rt_flags | NOUVEAU_BO_LOW,
188 0, 0);
189 OUT_RING(chan, nvfx->hw_rt[1].pitch);
190 }
191
192 if(nvfx->is_nv4x)
193 {
194 if (rt_enable & NV40_3D_RT_ENABLE_COLOR2) {
195 BEGIN_RING(chan, eng3d, NV40_3D_DMA_COLOR2, 1);
196 OUT_RELOC(chan, nvfx->hw_rt[2].bo, 0,
197 rt_flags | NOUVEAU_BO_OR,
198 chan->vram->handle, chan->gart->handle);
199 BEGIN_RING(chan, eng3d, NV40_3D_COLOR2_OFFSET, 1);
200 OUT_RELOC(chan, nvfx->hw_rt[2].bo,
201 nvfx->hw_rt[2].offset, rt_flags | NOUVEAU_BO_LOW,
202 0, 0);
203 BEGIN_RING(chan, eng3d, NV40_3D_COLOR2_PITCH, 1);
204 OUT_RING(chan, nvfx->hw_rt[2].pitch);
205 }
206
207 if (rt_enable & NV40_3D_RT_ENABLE_COLOR3) {
208 BEGIN_RING(chan, eng3d, NV40_3D_DMA_COLOR3, 1);
209 OUT_RELOC(chan, nvfx->hw_rt[3].bo, 0,
210 rt_flags | NOUVEAU_BO_OR,
211 chan->vram->handle, chan->gart->handle);
212 BEGIN_RING(chan, eng3d, NV40_3D_COLOR3_OFFSET, 1);
213 OUT_RELOC(chan, nvfx->hw_rt[3].bo,
214 nvfx->hw_rt[3].offset, rt_flags | NOUVEAU_BO_LOW,
215 0, 0);
216 BEGIN_RING(chan, eng3d, NV40_3D_COLOR3_PITCH, 1);
217 OUT_RING(chan, nvfx->hw_rt[3].pitch);
218 }
219 }
220
221 if (fb->zsbuf) {
222 BEGIN_RING(chan, eng3d, NV30_3D_DMA_ZETA, 1);
223 OUT_RELOC(chan, nvfx->hw_zeta.bo, 0,
224 rt_flags | NOUVEAU_BO_OR,
225 chan->vram->handle, chan->gart->handle);
226 BEGIN_RING(chan, eng3d, NV30_3D_ZETA_OFFSET, 1);
227 /* TODO: reverse engineer LMA */
228 OUT_RELOC(chan, nvfx->hw_zeta.bo,
229 nvfx->hw_zeta.offset, rt_flags | NOUVEAU_BO_LOW, 0, 0);
230 if(nvfx->is_nv4x) {
231 BEGIN_RING(chan, eng3d, NV40_3D_ZETA_PITCH, 1);
232 OUT_RING(chan, nvfx->hw_zeta.pitch);
233 }
234 }
235 else if(nvfx->is_nv4x) {
236 BEGIN_RING(chan, eng3d, NV40_3D_ZETA_PITCH, 1);
237 OUT_RING(chan, 64);
238 }
239
240 BEGIN_RING(chan, eng3d, NV30_3D_RT_ENABLE, 1);
241 OUT_RING(chan, rt_enable);
242 BEGIN_RING(chan, eng3d, NV30_3D_RT_HORIZ, 3);
243 OUT_RING(chan, (w << 16) | 0);
244 OUT_RING(chan, (h << 16) | 0);
245 OUT_RING(chan, rt_format);
246 BEGIN_RING(chan, eng3d, NV30_3D_VIEWPORT_HORIZ, 2);
247 OUT_RING(chan, (w << 16) | 0);
248 OUT_RING(chan, (h << 16) | 0);
249 BEGIN_RING(chan, eng3d, NV30_3D_VIEWPORT_CLIP_HORIZ(0), 2);
250 OUT_RING(chan, ((w - 1) << 16) | 0);
251 OUT_RING(chan, ((h - 1) << 16) | 0);
252
253 if(!nvfx->is_nv4x) {
254 /* Wonder why this is needed, context should all be set to zero on init */
255 /* TODO: we can most likely remove this, after putting it in context init */
256 BEGIN_RING(chan, eng3d, NV30_3D_VIEWPORT_TX_ORIGIN, 1);
257 OUT_RING(chan, 0);
258 }
259 nvfx->relocs_needed &=~ NVFX_RELOCATE_FRAMEBUFFER;
260}
261
262void
263nvfx_framebuffer_relocate(struct nvfx_context *nvfx)
264{
265 struct nouveau_channel *chan = nvfx->screen->base.channel;
266 unsigned rt_flags = NOUVEAU_BO_RDWR | NOUVEAU_BO_VRAM;
267 rt_flags |= NOUVEAU_BO_DUMMY;
268 MARK_RING(chan, 20, 20);
269
270#define DO_(var, pfx, name) \
271 if(var.bo) { \
272 OUT_RELOC(chan, var.bo, RING_3D(pfx##_3D_DMA_##name, 1), rt_flags, 0, 0); \
273 OUT_RELOC(chan, var.bo, 0, \
274 rt_flags | NOUVEAU_BO_OR, \
275 chan->vram->handle, chan->gart->handle); \
276 OUT_RELOC(chan, var.bo, RING_3D(pfx##_3D_##name##_OFFSET, 1), rt_flags, 0, 0); \
277 OUT_RELOC(chan, var.bo, \
278 var.offset, rt_flags | NOUVEAU_BO_LOW, \
279 0, 0); \
280 }
281
282#define DO(pfx, num) DO_(nvfx->hw_rt[num], pfx, COLOR##num)
283 DO(NV30, 0);
284 DO(NV30, 1);
285 DO(NV40, 2);
286 DO(NV40, 3);
287
288 DO_(nvfx->hw_zeta, NV30, ZETA);
289 nvfx->relocs_needed &=~ NVFX_RELOCATE_FRAMEBUFFER;
290}
diff --git a/src/gallium/drivers/nvfx/nvfx_surface.c b/src/gallium/drivers/nvfx/nvfx_surface.c
deleted file mode 100644
index 4dd6ccc2599..00000000000
--- a/src/gallium/drivers/nvfx/nvfx_surface.c
+++ /dev/null
@@ -1,413 +0,0 @@
1
2/**************************************************************************
3 *
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29#include "pipe/p_context.h"
30#include "pipe/p_format.h"
31#include "util/u_format.h"
32#include "util/u_math.h"
33#include "util/u_memory.h"
34#include "util/u_pack_color.h"
35#include "util/u_blitter.h"
36#include "util/u_surface.h"
37
38#include "nouveau/nouveau_winsys.h"
39#include "nouveau/nouveau_screen.h"
40#include "nvfx_context.h"
41#include "nvfx_screen.h"
42#include "nvfx_resource.h"
43#include "nv04_2d.h"
44
45#include <nouveau/nouveau_bo.h>
46
47static INLINE void
48nvfx_region_set_format(struct nv04_region* rgn, enum pipe_format format)
49{
50 unsigned bits = util_format_get_blocksizebits(format);
51 unsigned shift = 0;
52 rgn->one_bits = 0;
53
54 switch(bits)
55 {
56 case 8:
57 rgn->bpps = 0;
58 break;
59 case 16:
60 rgn->bpps = 1;
61 if(format == PIPE_FORMAT_B5G5R5X1_UNORM)
62 rgn->one_bits = 1;
63 break;
64 case 32:
65 rgn->bpps = 2;
66 if(format == PIPE_FORMAT_R8G8B8X8_UNORM || format == PIPE_FORMAT_B8G8R8X8_UNORM)
67 rgn->one_bits = 8;
68 break;
69 case 64:
70 rgn->bpps = 2;
71 shift = 1;
72 break;
73 case 128:
74 rgn->bpps = 2;
75 shift = 2;
76 break;
77 }
78
79 if(shift) {
80 rgn->x = util_format_get_nblocksx(format, rgn->x) << shift;
81 rgn->y = util_format_get_nblocksy(format, rgn->y);
82 rgn->w <<= shift;
83 }
84}
85
86static INLINE void
87nvfx_region_init_for_surface(struct nv04_region* rgn, struct nvfx_surface* surf, unsigned x, unsigned y, boolean for_write)
88{
89 rgn->x = x;
90 rgn->y = y;
91 rgn->z = 0;
92
93 rgn->bo = ((struct nvfx_resource*)surf->base.texture)->bo;
94 rgn->offset = surf->offset;
95
96 if(surf->base.texture->flags & NOUVEAU_RESOURCE_FLAG_LINEAR)
97 rgn->pitch = surf->pitch;
98 else {
99 rgn->pitch = 0;
100 rgn->z = surf->base.u.tex.first_layer;
101 rgn->w = surf->base.width;
102 rgn->h = surf->base.height;
103 rgn->d = u_minify(surf->base.texture->depth0, surf->base.u.tex.level);
104 }
105
106 nvfx_region_set_format(rgn, surf->base.format);
107 if(!rgn->pitch)
108 nv04_region_try_to_linearize(rgn);
109}
110
111static INLINE void
112nvfx_region_init_for_subresource(struct nv04_region* rgn, struct pipe_resource* pt, unsigned level, unsigned x, unsigned y, unsigned z, boolean for_write)
113{
114 if(pt->target != PIPE_BUFFER)
115 {
116 struct nvfx_surface* ns = (struct nvfx_surface*)util_surfaces_peek(&((struct nvfx_miptree*)pt)->surfaces, pt, level, z);
117 if(ns)
118 {
119 nvfx_region_init_for_surface(rgn, ns, x, y, for_write);
120 return;
121 }
122 }
123
124 rgn->bo = ((struct nvfx_resource*)pt)->bo;
125 rgn->offset = nvfx_subresource_offset(pt, z, level, z);
126 rgn->x = x;
127 rgn->y = y;
128
129 if(pt->flags & NOUVEAU_RESOURCE_FLAG_LINEAR)
130 {
131 rgn->pitch = nvfx_subresource_pitch(pt, level);
132 rgn->z = 0;
133 }
134 else
135 {
136 rgn->pitch = 0;
137 rgn->z = z;
138 rgn->w = u_minify(pt->width0, level);
139 rgn->h = u_minify(pt->height0, level);
140 rgn->d = u_minify(pt->depth0, level);
141 }
142
143 nvfx_region_set_format(rgn, pt->format);
144 if(!rgn->pitch)
145 nv04_region_try_to_linearize(rgn);
146}
147
148// don't save index buffer because blitter doesn't setit
149static struct blitter_context*
150nvfx_get_blitter(struct pipe_context* pipe, int copy)
151{
152 struct nvfx_context* nvfx = nvfx_context(pipe);
153 struct blitter_context** pblitter;
154 struct blitter_context* blitter;
155
156 assert(nvfx->blitters_in_use < Elements(nvfx->blitter));
157
158 if(nvfx->query && !nvfx->blitters_in_use)
159 {
160 struct nouveau_channel* chan = nvfx->screen->base.channel;
161 struct nouveau_grobj *eng3d = nvfx->screen->eng3d;
162 BEGIN_RING(chan, eng3d, NV30_3D_QUERY_ENABLE, 1);
163 OUT_RING(chan, 0);
164 }
165
166 pblitter = &nvfx->blitter[nvfx->blitters_in_use++];
167 if(!*pblitter)
168 *pblitter = util_blitter_create(pipe);
169 blitter = *pblitter;
170
171 util_blitter_save_blend(blitter, nvfx->blend);
172 util_blitter_save_depth_stencil_alpha(blitter, nvfx->zsa);
173 util_blitter_save_stencil_ref(blitter, &nvfx->stencil_ref);
174 util_blitter_save_rasterizer(blitter, nvfx->rasterizer);
175 util_blitter_save_fragment_shader(blitter, nvfx->fragprog);
176 util_blitter_save_vertex_shader(blitter, nvfx->vertprog);
177 util_blitter_save_viewport(blitter, &nvfx->viewport);
178 util_blitter_save_framebuffer(blitter, &nvfx->framebuffer);
179 util_blitter_save_vertex_elements(blitter, nvfx->vtxelt);
180 util_blitter_save_vertex_buffers(blitter, nvfx->vtxbuf_nr, nvfx->vtxbuf);
181
182 if(copy)
183 {
184 util_blitter_save_fragment_sampler_states(blitter, nvfx->nr_samplers, (void**)nvfx->tex_sampler);
185 util_blitter_save_fragment_sampler_views(blitter, nvfx->nr_textures, nvfx->fragment_sampler_views);
186 }
187
188 return blitter;
189}
190
191static inline void
192nvfx_put_blitter(struct pipe_context* pipe, struct blitter_context* blitter)
193{
194 struct nvfx_context* nvfx = nvfx_context(pipe);
195 --nvfx->blitters_in_use;
196 assert(nvfx->blitters_in_use >= 0);
197
198 if(nvfx->query && !nvfx->blitters_in_use)
199 {
200 struct nouveau_channel* chan = nvfx->screen->base.channel;
201 struct nouveau_grobj *eng3d = nvfx->screen->eng3d;
202 BEGIN_RING(chan, eng3d, NV30_3D_QUERY_ENABLE, 1);
203 OUT_RING(chan, 1);
204 }
205}
206
207static unsigned
208nvfx_region_clone(struct nv04_2d_context* ctx, struct nv04_region* rgn, unsigned w, unsigned h, boolean for_read)
209{
210 unsigned begin = nv04_region_begin(rgn, w, h);
211 unsigned end = nv04_region_end(rgn, w, h);
212 unsigned size = end - begin;
213 struct nouveau_bo* bo = 0;
214 nouveau_bo_new(rgn->bo->device, NOUVEAU_BO_MAP | NOUVEAU_BO_GART, 256, size, &bo);
215
216 if(for_read || (size > ((w * h) << rgn->bpps)))
217 nv04_memcpy(ctx, bo, 0, rgn->bo, rgn->offset + begin, size);
218
219 rgn->bo = bo;
220 rgn->offset = -begin;
221 return begin;
222}
223
224static void
225nvfx_resource_copy_region(struct pipe_context *pipe,
226 struct pipe_resource *dstr, unsigned dst_level,
227 unsigned dstx, unsigned dsty, unsigned dstz,
228 struct pipe_resource *srcr, unsigned src_level,
229 const struct pipe_box *src_box)
230{
231 static int copy_threshold = -1;
232 struct nv04_2d_context *ctx = nvfx_screen(pipe->screen)->eng2d;
233 struct nv04_region dst, src;
234 int dst_to_gpu;
235 int src_on_gpu;
236 boolean small;
237 int ret;
238 unsigned w = src_box->width;
239 unsigned h = src_box->height;
240
241 if(!w || !h)
242 return;
243
244 /* Fallback for buffers. */
245 if (dstr->target == PIPE_BUFFER && srcr->target == PIPE_BUFFER) {
246 util_resource_copy_region(pipe, dstr, dst_level, dstx, dsty, dstz,
247 srcr, src_level, src_box);
248 return;
249 }
250
251 if(copy_threshold < 0)
252 copy_threshold = debug_get_num_option("NOUVEAU_COPY_THRESHOLD", 4);
253
254 dst_to_gpu = dstr->usage != PIPE_USAGE_DYNAMIC && dstr->usage != PIPE_USAGE_STAGING;
255 src_on_gpu = nvfx_resource_on_gpu(srcr);
256
257 nvfx_region_init_for_subresource(&dst, dstr, dst_level, dstx, dsty, dstz, TRUE);
258 nvfx_region_init_for_subresource(&src, srcr, src_level, src_box->x, src_box->y, src_box->z, FALSE);
259 w = util_format_get_stride(dstr->format, w) >> dst.bpps;
260 h = util_format_get_nblocksy(dstr->format, h);
261
262 small = (w * h <= copy_threshold);
263 if((!dst_to_gpu || !src_on_gpu) && small)
264 ret = -1; /* use the CPU */
265 else
266 ret = nv04_region_copy_2d(ctx, &dst, &src, w, h, dst_to_gpu, src_on_gpu);
267 if(!ret)
268 {}
269 else if(ret > 0
270 && dstr->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)
271 && srcr->bind & PIPE_BIND_SAMPLER_VIEW)
272 {
273 /* this currently works because we hack the bind flags on resource creation to be
274 * the maximum set that the resource type actually supports
275 *
276 * TODO: perhaps support reinterpreting the formats
277 */
278 struct blitter_context* blitter = nvfx_get_blitter(pipe, 1);
279 util_blitter_copy_texture(blitter, dstr, dst_level, dstx, dsty, dstz, srcr, src_level, src_box, TRUE);
280 nvfx_put_blitter(pipe, blitter);
281 }
282 else
283 {
284 struct nv04_region dstt = dst;
285 struct nv04_region srct = src;
286 unsigned dstbegin = 0;
287
288 if(!small)
289 {
290 if(src_on_gpu)
291 nvfx_region_clone(ctx, &srct, w, h, TRUE);
292
293 if(dst_to_gpu)
294 dstbegin = nvfx_region_clone(ctx, &dstt, w, h, FALSE);
295 }
296
297 nv04_region_copy_cpu(&dstt, &srct, w, h);
298
299 if(srct.bo != src.bo)
300 nouveau_screen_bo_release(pipe->screen, srct.bo);
301
302 if(dstt.bo != dst.bo)
303 {
304 nv04_memcpy(ctx, dst.bo, dst.offset + dstbegin, dstt.bo, 0, dstt.bo->size);
305 nouveau_screen_bo_release(pipe->screen, dstt.bo);
306 }
307 }
308}
309
310static int
311nvfx_surface_fill(struct pipe_context* pipe, struct pipe_surface *dsts,
312 unsigned dx, unsigned dy, unsigned w, unsigned h, unsigned value)
313{
314 struct nv04_2d_context *ctx = nvfx_screen(pipe->screen)->eng2d;
315 struct nv04_region dst;
316 int ret;
317 /* Always try to use the GPU right now, if possible
318 * If the user wanted the surface data on the CPU, he would have cleared with memset (hopefully) */
319
320 // we don't care about interior pixel order since we set all them to the same value
321 nvfx_region_init_for_surface(&dst, (struct nvfx_surface*)dsts, dx, dy, TRUE);
322
323 w = util_format_get_stride(dsts->format, w) >> dst.bpps;
324 h = util_format_get_nblocksy(dsts->format, h);
325
326 ret = nv04_region_fill_2d(ctx, &dst, w, h, value);
327 if(ret > 0 && dsts->texture->bind & PIPE_BIND_RENDER_TARGET)
328 return 1;
329 else if(ret)
330 {
331 struct nv04_region dstt = dst;
332 unsigned dstbegin = 0;
333
334 if(nvfx_resource_on_gpu(dsts->texture))
335 dstbegin = nvfx_region_clone(ctx, &dstt, w, h, FALSE);
336
337 nv04_region_fill_cpu(&dstt, w, h, value);
338
339 if(dstt.bo != dst.bo)
340 {
341 nv04_memcpy(ctx, dst.bo, dst.offset + dstbegin, dstt.bo, 0, dstt.bo->size);
342 nouveau_screen_bo_release(pipe->screen, dstt.bo);
343 }
344 }
345
346 return 0;
347}
348
349
350void
351nvfx_screen_surface_takedown(struct pipe_screen *pscreen)
352{
353 nv04_2d_context_takedown(nvfx_screen(pscreen)->eng2d);
354 nvfx_screen(pscreen)->eng2d = 0;
355}
356
357int
358nvfx_screen_surface_init(struct pipe_screen *pscreen)
359{
360 struct nv04_2d_context* ctx = nv04_2d_context_init(nouveau_screen(pscreen)->channel);
361 if(!ctx)
362 return -1;
363 nvfx_screen(pscreen)->eng2d = ctx;
364 return 0;
365}
366
367static void
368nvfx_clear_render_target(struct pipe_context *pipe,
369 struct pipe_surface *dst,
370 const union pipe_color_union *color,
371 unsigned dstx, unsigned dsty,
372 unsigned width, unsigned height)
373{
374 union util_color uc;
375 util_pack_color(color->f, dst->format, &uc);
376
377 if(util_format_get_blocksizebits(dst->format) > 32
378 || nvfx_surface_fill(pipe, dst, dstx, dsty, width, height, uc.ui))
379 {
380 // TODO: probably should use hardware clear here instead if possible
381 struct blitter_context* blitter = nvfx_get_blitter(pipe, 0);
382 util_blitter_clear_render_target(blitter, dst, color, dstx, dsty, width, height);
383 nvfx_put_blitter(pipe, blitter);
384 }
385}
386
387static void
388nvfx_clear_depth_stencil(struct pipe_context *pipe,
389 struct pipe_surface *dst,
390 unsigned clear_flags,
391 double depth,
392 unsigned stencil,
393 unsigned dstx, unsigned dsty,
394 unsigned width, unsigned height)
395{
396 if(util_format_get_blocksizebits(dst->format) > 32
397 || nvfx_surface_fill(pipe, dst, dstx, dsty, width, height, util_pack_z_stencil(dst->format, depth, stencil)))
398 {
399 // TODO: probably should use hardware clear here instead if possible
400 struct blitter_context* blitter = nvfx_get_blitter(pipe, 0);
401 util_blitter_clear_depth_stencil(blitter, dst, clear_flags, depth, stencil, dstx, dsty, width, height);
402 nvfx_put_blitter(pipe, blitter);
403 }
404}
405
406
407void
408nvfx_init_surface_functions(struct nvfx_context *nvfx)
409{
410 nvfx->pipe.resource_copy_region = nvfx_resource_copy_region;
411 nvfx->pipe.clear_render_target = nvfx_clear_render_target;
412 nvfx->pipe.clear_depth_stencil = nvfx_clear_depth_stencil;
413}
diff --git a/src/gallium/drivers/nvfx/nvfx_surface.h b/src/gallium/drivers/nvfx/nvfx_surface.h
deleted file mode 100644
index e69de29bb2d..00000000000
--- a/src/gallium/drivers/nvfx/nvfx_surface.h
+++ /dev/null
diff --git a/src/gallium/drivers/nvfx/nvfx_tex.h b/src/gallium/drivers/nvfx/nvfx_tex.h
deleted file mode 100644
index 2f2d7378085..00000000000
--- a/src/gallium/drivers/nvfx/nvfx_tex.h
+++ /dev/null
@@ -1,175 +0,0 @@
1#ifndef NVFX_TEX_H_
2#define NVFX_TEX_H_
3
4#include "util/u_math.h"
5#include "pipe/p_defines.h"
6#include "pipe/p_state.h"
7
8
9static inline unsigned
10nvfx_tex_wrap_mode(unsigned wrap) {
11 unsigned ret;
12
13 switch (wrap) {
14 case PIPE_TEX_WRAP_REPEAT:
15 ret = NV30_3D_TEX_WRAP_S_REPEAT;
16 break;
17 case PIPE_TEX_WRAP_MIRROR_REPEAT:
18 ret = NV30_3D_TEX_WRAP_S_MIRRORED_REPEAT;
19 break;
20 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
21 ret = NV30_3D_TEX_WRAP_S_CLAMP_TO_EDGE;
22 break;
23 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
24 ret = NV30_3D_TEX_WRAP_S_CLAMP_TO_BORDER;
25 break;
26 case PIPE_TEX_WRAP_CLAMP:
27 ret = NV30_3D_TEX_WRAP_S_CLAMP;
28 break;
29 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
30 ret = NV40_3D_TEX_WRAP_S_MIRROR_CLAMP_TO_EDGE;
31 break;
32 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
33 ret = NV40_3D_TEX_WRAP_S_MIRROR_CLAMP_TO_BORDER;
34 break;
35 case PIPE_TEX_WRAP_MIRROR_CLAMP:
36 ret = NV40_3D_TEX_WRAP_S_MIRROR_CLAMP;
37 break;
38 default:
39 assert(0);
40 ret = NV30_3D_TEX_WRAP_S_REPEAT;
41 break;
42 }
43
44 return ret >> NV30_3D_TEX_WRAP_S__SHIFT;
45}
46
47static inline unsigned
48nvfx_tex_wrap_compare_mode(unsigned func)
49{
50 switch (func) {
51 case PIPE_FUNC_NEVER:
52 return NV30_3D_TEX_WRAP_RCOMP_NEVER;
53 case PIPE_FUNC_GREATER:
54 return NV30_3D_TEX_WRAP_RCOMP_GREATER;
55 case PIPE_FUNC_EQUAL:
56 return NV30_3D_TEX_WRAP_RCOMP_EQUAL;
57 case PIPE_FUNC_GEQUAL:
58 return NV30_3D_TEX_WRAP_RCOMP_GEQUAL;
59 case PIPE_FUNC_LESS:
60 return NV30_3D_TEX_WRAP_RCOMP_LESS;
61 case PIPE_FUNC_NOTEQUAL:
62 return NV30_3D_TEX_WRAP_RCOMP_NOTEQUAL;
63 case PIPE_FUNC_LEQUAL:
64 return NV30_3D_TEX_WRAP_RCOMP_LEQUAL;
65 case PIPE_FUNC_ALWAYS:
66 return NV30_3D_TEX_WRAP_RCOMP_ALWAYS;
67 default:
68 assert(0);
69 return 0;
70 }
71}
72
73static inline unsigned nvfx_tex_filter(const struct pipe_sampler_state* cso)
74{
75 unsigned filter = 0;
76 switch (cso->mag_img_filter) {
77 case PIPE_TEX_FILTER_LINEAR:
78 filter |= NV30_3D_TEX_FILTER_MAG_LINEAR;
79 break;
80 case PIPE_TEX_FILTER_NEAREST:
81 default:
82 filter |= NV30_3D_TEX_FILTER_MAG_NEAREST;
83 break;
84 }
85
86 switch (cso->min_img_filter) {
87 case PIPE_TEX_FILTER_LINEAR:
88 switch (cso->min_mip_filter) {
89 case PIPE_TEX_MIPFILTER_NEAREST:
90 filter |= NV30_3D_TEX_FILTER_MIN_LINEAR_MIPMAP_NEAREST;
91 break;
92 case PIPE_TEX_MIPFILTER_LINEAR:
93 filter |= NV30_3D_TEX_FILTER_MIN_LINEAR_MIPMAP_LINEAR;
94 break;
95 case PIPE_TEX_MIPFILTER_NONE:
96 default:
97 filter |= NV30_3D_TEX_FILTER_MIN_LINEAR;
98 break;
99 }
100 break;
101 case PIPE_TEX_FILTER_NEAREST:
102 default:
103 switch (cso->min_mip_filter) {
104 case PIPE_TEX_MIPFILTER_NEAREST:
105 filter |= NV30_3D_TEX_FILTER_MIN_NEAREST_MIPMAP_NEAREST;
106 break;
107 case PIPE_TEX_MIPFILTER_LINEAR:
108 filter |= NV30_3D_TEX_FILTER_MIN_NEAREST_MIPMAP_LINEAR;
109 break;
110 case PIPE_TEX_MIPFILTER_NONE:
111 default:
112 filter |= NV30_3D_TEX_FILTER_MIN_NEAREST;
113 break;
114 }
115 break;
116 }
117 return filter;
118}
119
120static inline unsigned nvfx_tex_border_color(const float* border_color)
121{
122 return ((float_to_ubyte(border_color[3]) << 24) |
123 (float_to_ubyte(border_color[0]) << 16) |
124 (float_to_ubyte(border_color[1]) << 8) |
125 (float_to_ubyte(border_color[2]) << 0));
126}
127
128struct nvfx_sampler_state {
129 uint32_t fmt;
130 uint32_t wrap;
131 uint32_t en;
132 uint32_t filt;
133 uint32_t bcol;
134 uint32_t min_lod;
135 uint32_t max_lod;
136 boolean compare;
137};
138
139struct nvfx_sampler_view {
140 struct pipe_sampler_view base;
141 int offset;
142 uint32_t swizzle;
143 uint32_t npot_size;
144 uint32_t filt;
145 uint32_t wrap_mask;
146 uint32_t wrap;
147 uint32_t lod_offset;
148 uint32_t max_lod_limit;
149 union
150 {
151 struct
152 {
153 uint32_t fmt[4]; /* nv30 has 4 entries, nv40 one */
154 int rect;
155 } nv30;
156 struct
157 {
158 uint32_t fmt[2]; /* nv30 has 4 entries, nv40 one */
159 uint32_t npot_size2; /* nv40 only */
160 } nv40;
161 uint32_t init_fmt;
162 } u;
163};
164
165struct nvfx_texture_format {
166 int fmt[6];
167 unsigned sign;
168 unsigned wrap;
169 unsigned char src[6];
170 unsigned char comp[6];
171};
172
173extern struct nvfx_texture_format nvfx_texture_formats[PIPE_FORMAT_COUNT];
174
175#endif /* NVFX_TEX_H_ */
diff --git a/src/gallium/drivers/nvfx/nvfx_transfer.c b/src/gallium/drivers/nvfx/nvfx_transfer.c
deleted file mode 100644
index 7a218b18c64..00000000000
--- a/src/gallium/drivers/nvfx/nvfx_transfer.c
+++ /dev/null
@@ -1,221 +0,0 @@
1#include "pipe/p_state.h"
2#include "pipe/p_defines.h"
3#include "util/u_inlines.h"
4#include "util/u_format.h"
5#include "util/u_memory.h"
6#include "util/u_math.h"
7#include "util/u_staging.h"
8#include "nvfx_context.h"
9#include "nvfx_screen.h"
10#include "nvfx_state.h"
11#include "nvfx_resource.h"
12#include "nvfx_transfer.h"
13
14struct nvfx_staging_transfer
15{
16 struct util_staging_transfer base;
17
18 unsigned offset;
19 unsigned map_count;
20};
21
22struct pipe_transfer *
23nvfx_transfer_new(struct pipe_context *pipe,
24 struct pipe_resource *pt,
25 unsigned level,
26 unsigned usage,
27 const struct pipe_box *box)
28{
29 if((usage & (PIPE_TRANSFER_UNSYNCHRONIZED | PIPE_TRANSFER_DONTBLOCK)) == PIPE_TRANSFER_DONTBLOCK)
30 {
31 struct nouveau_bo* bo = ((struct nvfx_resource*)pt)->bo;
32 if(bo && nouveau_bo_busy(bo, NOUVEAU_BO_WR))
33 return NULL;
34 }
35
36 if(pt->target == PIPE_BUFFER)
37 {
38 // it would be nice if we could avoid all this ridiculous overhead...
39 struct pipe_transfer* tx;
40 struct nvfx_buffer* buffer = nvfx_buffer(pt);
41
42 tx = CALLOC_STRUCT(pipe_transfer);
43 if (!tx)
44 return NULL;
45
46 pipe_resource_reference(&tx->resource, pt);
47 tx->level = level;
48 tx->usage = usage;
49 tx->box = *box;
50
51 tx->layer_stride = tx->stride = util_format_get_stride(pt->format, box->width);
52 tx->data = buffer->data + util_format_get_stride(pt->format, box->x);
53
54 return tx;
55 }
56 else
57 {
58 struct nvfx_staging_transfer* tx;
59 boolean direct = !nvfx_resource_on_gpu(pt) && pt->flags & NOUVEAU_RESOURCE_FLAG_LINEAR;
60
61 tx = CALLOC_STRUCT(nvfx_staging_transfer);
62 if(!tx)
63 return NULL;
64
65 util_staging_transfer_init(pipe, pt, level, usage, box, direct, &tx->base);
66
67 if(direct)
68 {
69 tx->base.base.stride = nvfx_subresource_pitch(pt, level);
70 tx->base.base.layer_stride = tx->base.base.stride * u_minify(pt->height0, level);
71 tx->offset = nvfx_subresource_offset(pt, box->z, level, box->z)
72 + util_format_get_2d_size(pt->format, tx->base.base.stride, box->y)
73 + util_format_get_stride(pt->format, box->x);
74 }
75 else
76 {
77 tx->base.base.stride = nvfx_subresource_pitch(tx->base.staging_resource, 0);
78 tx->base.base.layer_stride = tx->base.base.stride * tx->base.staging_resource->height0;
79 tx->offset = 0;
80 }
81
82 assert(tx->base.base.stride);
83
84 return &tx->base.base;
85 }
86}
87
88static void nvfx_buffer_dirty_interval(struct nvfx_buffer* buffer, unsigned begin, unsigned size, boolean unsynchronized)
89{
90 struct nvfx_screen* screen = nvfx_screen(buffer->base.base.screen);
91 buffer->last_update_static = buffer->bytes_to_draw_until_static < 0;
92 if(buffer->dirty_begin == buffer->dirty_end)
93 {
94 buffer->dirty_begin = begin;
95 buffer->dirty_end = begin + size;
96 buffer->dirty_unsynchronized = unsynchronized;
97 }
98 else
99 {
100 buffer->dirty_begin = MIN2(buffer->dirty_begin, begin);
101 buffer->dirty_end = MAX2(buffer->dirty_end, begin + size);
102 buffer->dirty_unsynchronized &= unsynchronized;
103 }
104
105 if(unsynchronized)
106 {
107 // TODO: revisit this, it doesn't seem quite right
108 //printf("UNSYNC UPDATE %p %u %u\n", buffer, begin, size);
109 buffer->bytes_to_draw_until_static += size * screen->static_reuse_threshold;
110 }
111 else
112 buffer->bytes_to_draw_until_static = buffer->size * screen->static_reuse_threshold;
113}
114
115static void nvfx_transfer_flush_region( struct pipe_context *pipe,
116 struct pipe_transfer *ptx,
117 const struct pipe_box *box)
118{
119 if(ptx->resource->target == PIPE_BUFFER && (ptx->usage & PIPE_TRANSFER_FLUSH_EXPLICIT))
120 {
121 struct nvfx_buffer* buffer = nvfx_buffer(ptx->resource);
122 nvfx_buffer_dirty_interval(buffer,
123 (uint8_t*)ptx->data - buffer->data + util_format_get_stride(buffer->base.base.format, box->x),
124 util_format_get_stride(buffer->base.base.format, box->width),
125 !!(ptx->usage & PIPE_TRANSFER_UNSYNCHRONIZED));
126 }
127}
128
129static void
130nvfx_transfer_destroy(struct pipe_context *pipe, struct pipe_transfer *ptx)
131{
132 if(ptx->resource->target == PIPE_BUFFER)
133 {
134 struct nvfx_buffer* buffer = nvfx_buffer(ptx->resource);
135 if((ptx->usage & (PIPE_TRANSFER_WRITE | PIPE_TRANSFER_FLUSH_EXPLICIT)) == PIPE_TRANSFER_WRITE)
136 nvfx_buffer_dirty_interval(buffer,
137 (uint8_t*)ptx->data - buffer->data,
138 ptx->stride,
139 !!(ptx->usage & PIPE_TRANSFER_UNSYNCHRONIZED));
140 pipe_resource_reference(&ptx->resource, 0);
141 FREE(ptx);
142 }
143 else
144 {
145 struct nouveau_channel* chan = nvfx_context(pipe)->screen->base.channel;
146 util_staging_transfer_destroy(pipe, ptx);
147
148 FIRE_RING(chan);
149 }
150}
151
152void *
153nvfx_transfer_map(struct pipe_context *pipe, struct pipe_transfer *ptx)
154{
155 if(ptx->resource->target == PIPE_BUFFER)
156 return ptx->data;
157 else
158 {
159 struct nvfx_staging_transfer *tx = (struct nvfx_staging_transfer *)ptx;
160 if(!ptx->data)
161 {
162 struct nvfx_miptree *mt = (struct nvfx_miptree *)tx->base.staging_resource;
163 uint8_t *map = nouveau_screen_bo_map(pipe->screen, mt->base.bo, nouveau_screen_transfer_flags(ptx->usage));
164 ptx->data = map + tx->offset;
165 }
166
167 ++tx->map_count;
168 return ptx->data;
169 }
170}
171
172void
173nvfx_transfer_unmap(struct pipe_context *pipe, struct pipe_transfer *ptx)
174{
175 if(ptx->resource->target != PIPE_BUFFER)
176 {
177 struct nvfx_staging_transfer *tx = (struct nvfx_staging_transfer *)ptx;
178 struct nvfx_miptree *mt = (struct nvfx_miptree *)tx->base.staging_resource;
179
180 if(!--tx->map_count)
181 {
182 nouveau_screen_bo_unmap(pipe->screen, mt->base.bo);
183 ptx->data = 0;
184 }
185 }
186}
187
188static void nvfx_transfer_inline_write( struct pipe_context *pipe,
189 struct pipe_resource *pr,
190 unsigned level,
191 unsigned usage,
192 const struct pipe_box *box,
193 const void *data,
194 unsigned stride,
195 unsigned slice_stride)
196{
197 if(pr->target != PIPE_BUFFER)
198 {
199 u_default_transfer_inline_write(pipe, pr, level, usage, box, data, stride, slice_stride);
200 }
201 else
202 {
203 struct nvfx_buffer* buffer = nvfx_buffer(pr);
204 unsigned begin = util_format_get_stride(pr->format, box->x);
205 unsigned size = util_format_get_stride(pr->format, box->width);
206 memcpy(buffer->data + begin, data, size);
207 nvfx_buffer_dirty_interval(buffer, begin, size,
208 !!(pr->flags & PIPE_TRANSFER_UNSYNCHRONIZED));
209 }
210}
211
212void
213nvfx_init_transfer_functions(struct pipe_context *pipe)
214{
215 pipe->get_transfer = nvfx_transfer_new;
216 pipe->transfer_map = nvfx_transfer_map;
217 pipe->transfer_flush_region = nvfx_transfer_flush_region;
218 pipe->transfer_unmap = nvfx_transfer_unmap;
219 pipe->transfer_destroy = nvfx_transfer_destroy;
220 pipe->transfer_inline_write = nvfx_transfer_inline_write;
221}
diff --git a/src/gallium/drivers/nvfx/nvfx_transfer.h b/src/gallium/drivers/nvfx/nvfx_transfer.h
deleted file mode 100644
index 682f428b793..00000000000
--- a/src/gallium/drivers/nvfx/nvfx_transfer.h
+++ /dev/null
@@ -1,24 +0,0 @@
1
2#ifndef NVFX_TRANSFER_H
3#define NVFX_TRANSFER_H
4
5#include "util/u_transfer.h"
6#include "pipe/p_state.h"
7
8
9struct pipe_transfer *
10nvfx_transfer_new(struct pipe_context *pcontext,
11 struct pipe_resource *pt,
12 unsigned level,
13 unsigned usage,
14 const struct pipe_box *box);
15
16void *
17nvfx_transfer_map(struct pipe_context *pcontext,
18 struct pipe_transfer *ptx);
19void
20nvfx_transfer_unmap(struct pipe_context *pcontext,
21 struct pipe_transfer *ptx);
22
23
24#endif
diff --git a/src/gallium/drivers/nvfx/nvfx_vbo.c b/src/gallium/drivers/nvfx/nvfx_vbo.c
deleted file mode 100644
index b72379d6536..00000000000
--- a/src/gallium/drivers/nvfx/nvfx_vbo.c
+++ /dev/null
@@ -1,637 +0,0 @@
1#include "pipe/p_context.h"
2#include "pipe/p_state.h"
3#include "util/u_inlines.h"
4#include "util/u_format.h"
5#include "util/u_transfer.h"
6#include "translate/translate.h"
7
8#include "nvfx_context.h"
9#include "nvfx_state.h"
10#include "nvfx_resource.h"
11
12#include "nouveau/nouveau_channel.h"
13#include "nouveau/nv04_pushbuf.h"
14
15static inline unsigned
16util_guess_unique_indices_count(unsigned mode, unsigned indices)
17{
18 /* Euler's formula gives V =
19 * = E - F + 2 =
20 * = F * (polygon_edges / 2 - 1) + 2 =
21 * = F * (polygon_edges - 2) / 2 + 2 =
22 * = indices * (polygon_edges - 2) / (2 * indices_per_face) + 2
23 * = indices * (1 / 2 - 1 / polygon_edges) + 2
24 */
25 switch(mode)
26 {
27 case PIPE_PRIM_LINES:
28 return indices >> 1;
29 case PIPE_PRIM_TRIANGLES:
30 {
31 // avoid an expensive division by 3 using the multiplicative inverse mod 2^32
32 unsigned q;
33 unsigned inv3 = 2863311531;
34 indices >>= 1;
35 q = indices * inv3;
36 if(unlikely(q >= indices))
37 {
38 q += inv3;
39 if(q >= indices)
40 q += inv3;
41 }
42 return indices + 2;
43 //return indices / 6 + 2;
44 }
45 // guess that indexed quads are created by successive connections, since a closed mesh seems unlikely
46 case PIPE_PRIM_QUADS:
47 return (indices >> 1) + 2;
48 // return (indices >> 2) + 2; // if it is a closed mesh
49 default:
50 return indices;
51 }
52}
53
54static unsigned nvfx_decide_upload_mode(struct pipe_context *pipe, const struct pipe_draw_info *info)
55{
56 struct nvfx_context* nvfx = nvfx_context(pipe);
57 unsigned hardware_cost = 0;
58 unsigned inline_cost = 0;
59 unsigned unique_vertices;
60 unsigned upload_mode;
61 float best_index_cost_for_hardware_vertices_as_inline_cost;
62 boolean prefer_hardware_indices;
63 unsigned index_inline_cost;
64 unsigned index_hardware_cost;
65 if (info->indexed)
66 unique_vertices = util_guess_unique_indices_count(info->mode, info->count);
67 else
68 unique_vertices = info->count;
69
70 /* Here we try to figure out if we are better off writing vertex data directly on the FIFO,
71 * or create hardware buffer objects and pointing the hardware to them.
72 *
73 * This is done by computing the total memcpy cost of each option, ignoring uploads
74 * if we think that the buffer is static and thus the upload cost will be amortized over
75 * future draw calls.
76 *
77 * For instance, if everything looks static, we will always create buffer objects, while if
78 * everything is a user buffer and we are not doing indexed drawing, we never do.
79 *
80 * Other interesting cases are where a small user vertex buffer, but a huge user index buffer,
81 * where we will upload the vertex buffer, so that we can use hardware index lookup, and
82 * the opposite case, where we instead do index lookup in software to avoid uploading
83 * a huge amount of vertex data that is not going to be used.
84 *
85 * Otherwise, we generally move to the GPU the after it has been pushed
86 * NVFX_STATIC_BUFFER_MIN_REUSE_TIMES times to the GPU without having
87 * been updated with a transfer (or just the buffer having been destroyed).
88 *
89 * There is no special handling for user buffers, since applications can use
90 * OpenGL VBOs in a one-shot fashion. OpenGL 3/4 core profile forces this
91 * by the way.
92 *
93 * Note that currently we don't support only putting some data on the FIFO, and
94 * some on vertex buffers (constant and instanced data is independent from this).
95 *
96 * nVidia doesn't seem to do this either, even though it should be at least
97 * doable with VTX_ATTR and possibly with VERTEX_DATA too if not indexed.
98 */
99
100 for (unsigned i = 0; i < nvfx->vtxelt->num_per_vertex_buffer_infos; i++)
101 {
102 struct nvfx_per_vertex_buffer_info* vbi = &nvfx->vtxelt->per_vertex_buffer_info[i];
103 struct pipe_vertex_buffer *vb = &nvfx->vtxbuf[vbi->vertex_buffer_index];
104 struct nvfx_buffer* buffer = nvfx_buffer(vb->buffer);
105 buffer->bytes_to_draw_until_static -= vbi->per_vertex_size * unique_vertices;
106 if (!nvfx_buffer_seems_static(buffer))
107 {
108 hardware_cost += buffer->dirty_end - buffer->dirty_begin;
109 if (!buffer->base.bo)
110 hardware_cost += nvfx->screen->buffer_allocation_cost;
111 }
112 inline_cost += vbi->per_vertex_size * info->count;
113 }
114
115 best_index_cost_for_hardware_vertices_as_inline_cost = 0.0f;
116 prefer_hardware_indices = FALSE;
117 index_inline_cost = 0;
118 index_hardware_cost = 0;
119
120 if (info->indexed)
121 {
122 index_inline_cost = nvfx->idxbuf.index_size * info->count;
123 if (nvfx->screen->index_buffer_reloc_flags
124 && (nvfx->idxbuf.index_size == 2 || nvfx->idxbuf.index_size == 4)
125 && !(nvfx->idxbuf.offset & (nvfx->idxbuf.index_size - 1)))
126 {
127 struct nvfx_buffer* buffer = nvfx_buffer(nvfx->idxbuf.buffer);
128 buffer->bytes_to_draw_until_static -= index_inline_cost;
129
130 prefer_hardware_indices = TRUE;
131
132 if (!nvfx_buffer_seems_static(buffer))
133 {
134 index_hardware_cost = buffer->dirty_end - buffer->dirty_begin;
135 if (!buffer->base.bo)
136 index_hardware_cost += nvfx->screen->buffer_allocation_cost;
137 }
138
139 if ((float) index_inline_cost < (float) index_hardware_cost * nvfx->screen->inline_cost_per_hardware_cost)
140 {
141 best_index_cost_for_hardware_vertices_as_inline_cost = (float) index_inline_cost;
142 }
143 else
144 {
145 best_index_cost_for_hardware_vertices_as_inline_cost = (float) index_hardware_cost * nvfx->screen->inline_cost_per_hardware_cost;
146 prefer_hardware_indices = TRUE;
147 }
148 }
149 }
150
151 /* let's finally figure out which of the 3 paths we want to take */
152 if ((float) (inline_cost + index_inline_cost) > ((float) hardware_cost * nvfx->screen->inline_cost_per_hardware_cost + best_index_cost_for_hardware_vertices_as_inline_cost))
153 upload_mode = 1 + prefer_hardware_indices;
154 else
155 upload_mode = 0;
156
157#ifdef DEBUG
158 if (unlikely(nvfx->screen->trace_draw))
159 {
160 fprintf(stderr, "DRAW");
161 if (info->indexed)
162 {
163 fprintf(stderr, "_IDX%u", nvfx->idxbuf.index_size);
164 if (info->index_bias)
165 fprintf(stderr, " biased %u", info->index_bias);
166 fprintf(stderr, " idxrange %u -> %u", info->min_index, info->max_index);
167 }
168 if (info->instance_count > 1)
169 fprintf(stderr, " %u instances from %u", info->instance_count, info->indexed);
170 fprintf(stderr, " start %u count %u prim %u", info->start, info->count, info->mode);
171 if (!upload_mode)
172 fprintf(stderr, " -> inline vertex data");
173 else if (upload_mode == 2 || !info->indexed)
174 fprintf(stderr, " -> buffer range");
175 else
176 fprintf(stderr, " -> inline indices");
177 fprintf(stderr, " [ivtx %u hvtx %u iidx %u hidx %u bidx %f] <", inline_cost, hardware_cost, index_inline_cost, index_hardware_cost, best_index_cost_for_hardware_vertices_as_inline_cost);
178 for (unsigned i = 0; i < nvfx->vtxelt->num_per_vertex_buffer_infos; ++i)
179 {
180 struct nvfx_per_vertex_buffer_info* vbi = &nvfx->vtxelt->per_vertex_buffer_info[i];
181 struct pipe_vertex_buffer *vb = &nvfx->vtxbuf[vbi->vertex_buffer_index];
182 struct nvfx_buffer* buffer = nvfx_buffer(vb->buffer);
183 if (i)
184 fprintf(stderr, ", ");
185 fprintf(stderr, "%p%s left %Li", buffer, buffer->last_update_static ? " static" : "", buffer->bytes_to_draw_until_static);
186 }
187 fprintf(stderr, ">\n");
188 }
189#endif
190
191 return upload_mode;
192}
193
194void nvfx_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
195{
196 struct nvfx_context *nvfx = nvfx_context(pipe);
197 unsigned upload_mode = 0;
198
199 if (!nvfx->vtxelt->needs_translate)
200 upload_mode = nvfx_decide_upload_mode(pipe, info);
201
202 nvfx->use_index_buffer = upload_mode > 1;
203
204 if ((upload_mode > 0) != nvfx->use_vertex_buffers)
205 {
206 nvfx->use_vertex_buffers = (upload_mode > 0);
207 nvfx->dirty |= NVFX_NEW_ARRAYS;
208 nvfx->draw_dirty |= NVFX_NEW_ARRAYS;
209 }
210
211 if (upload_mode > 0)
212 {
213 for (unsigned i = 0; i < nvfx->vtxelt->num_per_vertex_buffer_infos; i++)
214 {
215 struct nvfx_per_vertex_buffer_info* vbi = &nvfx->vtxelt->per_vertex_buffer_info[i];
216 struct pipe_vertex_buffer *vb = &nvfx->vtxbuf[vbi->vertex_buffer_index];
217 nvfx_buffer_upload(nvfx_buffer(vb->buffer));
218 }
219
220 if (upload_mode > 1)
221 {
222 nvfx_buffer_upload(nvfx_buffer(nvfx->idxbuf.buffer));
223
224 if (unlikely(info->index_bias != nvfx->base_vertex))
225 {
226 nvfx->base_vertex = info->index_bias;
227 nvfx->dirty |= NVFX_NEW_ARRAYS;
228 }
229 }
230 else
231 {
232 if (unlikely(info->start < nvfx->base_vertex && nvfx->base_vertex))
233 {
234 nvfx->base_vertex = 0;
235 nvfx->dirty |= NVFX_NEW_ARRAYS;
236 }
237 }
238 }
239
240 if (nvfx->screen->force_swtnl || !nvfx_state_validate(nvfx))
241 nvfx_draw_vbo_swtnl(pipe, info);
242 else
243 nvfx_push_vbo(pipe, info);
244}
245
246boolean
247nvfx_vbo_validate(struct nvfx_context *nvfx)
248{
249 struct nouveau_channel* chan = nvfx->screen->base.channel;
250 struct nouveau_grobj *eng3d = nvfx->screen->eng3d;
251 int i;
252 int elements = MAX2(nvfx->vtxelt->num_elements, nvfx->hw_vtxelt_nr);
253 unsigned vb_flags = nvfx->screen->vertex_buffer_reloc_flags | NOUVEAU_BO_RD;
254
255 if (!elements)
256 return TRUE;
257
258 MARK_RING(chan, (5 + 2) * 16 + 2 + 11, 16 + 2);
259 for(unsigned i = 0; i < nvfx->vtxelt->num_constant; ++i)
260 {
261 struct nvfx_low_frequency_element *ve = &nvfx->vtxelt->constant[i];
262 struct pipe_vertex_buffer *vb = &nvfx->vtxbuf[ve->vertex_buffer_index];
263 struct nvfx_buffer* buffer = nvfx_buffer(vb->buffer);
264 float v[4];
265 ve->fetch_rgba_float(v, buffer->data + vb->buffer_offset + ve->src_offset, 0, 0);
266 nvfx_emit_vtx_attr(chan, eng3d, ve->idx, v, ve->ncomp);
267 }
268
269
270 BEGIN_RING(chan, eng3d, NV30_3D_VTXFMT(0), elements);
271 if(nvfx->use_vertex_buffers)
272 {
273 unsigned idx = 0;
274 for (i = 0; i < nvfx->vtxelt->num_per_vertex; i++) {
275 struct nvfx_per_vertex_element *ve = &nvfx->vtxelt->per_vertex[i];
276 struct pipe_vertex_buffer *vb = &nvfx->vtxbuf[ve->vertex_buffer_index];
277
278 if(idx != ve->idx)
279 {
280 assert(idx < ve->idx);
281 OUT_RINGp(chan, &nvfx->vtxelt->vtxfmt[idx], ve->idx - idx);
282 idx = ve->idx;
283 }
284
285 OUT_RING(chan, nvfx->vtxelt->vtxfmt[idx] | (vb->stride << NV30_3D_VTXFMT_STRIDE__SHIFT));
286 ++idx;
287 }
288 if(idx != nvfx->vtxelt->num_elements)
289 OUT_RINGp(chan, &nvfx->vtxelt->vtxfmt[idx], nvfx->vtxelt->num_elements - idx);
290 }
291 else
292 OUT_RINGp(chan, nvfx->vtxelt->vtxfmt, nvfx->vtxelt->num_elements);
293
294 for(i = nvfx->vtxelt->num_elements; i < elements; ++i)
295 OUT_RING(chan, NV30_3D_VTXFMT_TYPE_V32_FLOAT);
296
297 if(nvfx->is_nv4x) {
298 unsigned i;
299 /* seems to be some kind of cache flushing */
300 for(i = 0; i < 3; ++i) {
301 BEGIN_RING(chan, eng3d, 0x1718, 1);
302 OUT_RING(chan, 0);
303 }
304 }
305
306 BEGIN_RING(chan, eng3d, NV30_3D_VTXBUF(0), elements);
307 if(nvfx->use_vertex_buffers)
308 {
309 unsigned idx = 0;
310 for (i = 0; i < nvfx->vtxelt->num_per_vertex; i++) {
311 struct nvfx_per_vertex_element *ve = &nvfx->vtxelt->per_vertex[i];
312 struct pipe_vertex_buffer *vb = &nvfx->vtxbuf[ve->vertex_buffer_index];
313 struct nouveau_bo* bo = nvfx_resource(vb->buffer)->bo;
314
315 for(; idx < ve->idx; ++idx)
316 OUT_RING(chan, 0);
317
318 OUT_RELOC(chan, bo,
319 vb->buffer_offset + ve->src_offset + nvfx->base_vertex * vb->stride,
320 vb_flags | NOUVEAU_BO_LOW | NOUVEAU_BO_OR,
321 0, NV30_3D_VTXBUF_DMA1);
322 ++idx;
323 }
324
325 for(; idx < elements; ++idx)
326 OUT_RING(chan, 0);
327 }
328 else
329 {
330 for (i = 0; i < elements; i++)
331 OUT_RING(chan, 0);
332 }
333
334 BEGIN_RING(chan, eng3d, 0x1710, 1);
335 OUT_RING(chan, 0);
336
337 nvfx->hw_vtxelt_nr = nvfx->vtxelt->num_elements;
338 nvfx->relocs_needed &=~ NVFX_RELOCATE_VTXBUF;
339 return TRUE;
340}
341
342void
343nvfx_vbo_swtnl_validate(struct nvfx_context *nvfx)
344{
345 struct nouveau_channel* chan = nvfx->screen->base.channel;
346 struct nouveau_grobj *eng3d = nvfx->screen->eng3d;
347 unsigned num_outputs = nvfx->vertprog->draw_elements;
348 int elements = MAX2(num_outputs, nvfx->hw_vtxelt_nr);
349
350 if (!elements)
351 return;
352
353 BEGIN_RING(chan, eng3d, NV30_3D_VTXFMT(0), elements);
354 for(unsigned i = 0; i < num_outputs; ++i)
355 OUT_RING(chan, (4 << NV30_3D_VTXFMT_SIZE__SHIFT) | NV30_3D_VTXFMT_TYPE_V32_FLOAT);
356 for(unsigned i = num_outputs; i < elements; ++i)
357 OUT_RING(chan, NV30_3D_VTXFMT_TYPE_V32_FLOAT);
358
359 if(nvfx->is_nv4x) {
360 unsigned i;
361 /* seems to be some kind of cache flushing */
362 for(i = 0; i < 3; ++i) {
363 BEGIN_RING(chan, eng3d, 0x1718, 1);
364 OUT_RING(chan, 0);
365 }
366 }
367
368 BEGIN_RING(chan, eng3d, NV30_3D_VTXBUF(0), elements);
369 for (unsigned i = 0; i < elements; i++)
370 OUT_RING(chan, 0);
371
372 BEGIN_RING(chan, eng3d, 0x1710, 1);
373 OUT_RING(chan, 0);
374
375 nvfx->hw_vtxelt_nr = num_outputs;
376 nvfx->relocs_needed &=~ NVFX_RELOCATE_VTXBUF;
377}
378
379void
380nvfx_vbo_relocate(struct nvfx_context *nvfx)
381{
382 struct nouveau_channel* chan;
383 unsigned vb_flags;
384 int i;
385
386 if(!nvfx->use_vertex_buffers)
387 return;
388
389 chan = nvfx->screen->base.channel;
390 vb_flags = nvfx->screen->vertex_buffer_reloc_flags | NOUVEAU_BO_RD | NOUVEAU_BO_DUMMY;
391
392 MARK_RING(chan, 2 * 16 + 3, 2 * 16 + 3);
393 for (i = 0; i < nvfx->vtxelt->num_per_vertex; i++) {
394 struct nvfx_per_vertex_element *ve = &nvfx->vtxelt->per_vertex[i];
395 struct pipe_vertex_buffer *vb = &nvfx->vtxbuf[ve->vertex_buffer_index];
396 struct nouveau_bo* bo = nvfx_resource(vb->buffer)->bo;
397
398 OUT_RELOC(chan, bo, RING_3D(NV30_3D_VTXBUF(ve->idx), 1),
399 vb_flags, 0, 0);
400 OUT_RELOC(chan, bo, vb->buffer_offset + ve->src_offset + nvfx->base_vertex * vb->stride,
401 vb_flags | NOUVEAU_BO_LOW | NOUVEAU_BO_OR,
402 0, NV30_3D_VTXBUF_DMA1);
403 }
404 nvfx->relocs_needed &=~ NVFX_RELOCATE_VTXBUF;
405}
406
407static void
408nvfx_idxbuf_emit(struct nvfx_context* nvfx, unsigned ib_flags)
409{
410 struct nouveau_channel* chan = nvfx->screen->base.channel;
411 unsigned ib_format = (nvfx->idxbuf.index_size == 2) ? NV30_3D_IDXBUF_FORMAT_TYPE_U16 : NV30_3D_IDXBUF_FORMAT_TYPE_U32;
412 struct nouveau_bo* bo = nvfx_resource(nvfx->idxbuf.buffer)->bo;
413 ib_flags |= nvfx->screen->index_buffer_reloc_flags | NOUVEAU_BO_RD;
414
415 assert(nvfx->screen->index_buffer_reloc_flags);
416
417 MARK_RING(chan, 3, 3);
418 if(ib_flags & NOUVEAU_BO_DUMMY)
419 OUT_RELOC(chan, bo, RING_3D(NV30_3D_IDXBUF_OFFSET, 2), ib_flags, 0, 0);
420 else
421 OUT_RING(chan, RING_3D(NV30_3D_IDXBUF_OFFSET, 2));
422 OUT_RELOC(chan, bo, nvfx->idxbuf.offset + 1, ib_flags | NOUVEAU_BO_LOW, 0, 0);
423 OUT_RELOC(chan, bo, ib_format, ib_flags | NOUVEAU_BO_OR,
424 0, NV30_3D_IDXBUF_FORMAT_DMA1);
425 nvfx->relocs_needed &=~ NVFX_RELOCATE_IDXBUF;
426}
427
428void
429nvfx_idxbuf_validate(struct nvfx_context* nvfx)
430{
431 nvfx_idxbuf_emit(nvfx, 0);
432}
433
434void
435nvfx_idxbuf_relocate(struct nvfx_context* nvfx)
436{
437 nvfx_idxbuf_emit(nvfx, NOUVEAU_BO_DUMMY);
438}
439
440unsigned nvfx_vertex_formats[PIPE_FORMAT_COUNT] =
441{
442 [PIPE_FORMAT_R32_FLOAT] = NV30_3D_VTXFMT_TYPE_V32_FLOAT,
443 [PIPE_FORMAT_R32G32_FLOAT] = NV30_3D_VTXFMT_TYPE_V32_FLOAT,
444 [PIPE_FORMAT_R32G32B32_FLOAT] = NV30_3D_VTXFMT_TYPE_V32_FLOAT,
445 [PIPE_FORMAT_R32G32B32A32_FLOAT] = NV30_3D_VTXFMT_TYPE_V32_FLOAT,
446 [PIPE_FORMAT_R16_FLOAT] = NV30_3D_VTXFMT_TYPE_V16_FLOAT,
447 [PIPE_FORMAT_R16G16_FLOAT] = NV30_3D_VTXFMT_TYPE_V16_FLOAT,
448 [PIPE_FORMAT_R16G16B16_FLOAT] = NV30_3D_VTXFMT_TYPE_V16_FLOAT,
449 [PIPE_FORMAT_R16G16B16A16_FLOAT] = NV30_3D_VTXFMT_TYPE_V16_FLOAT,
450 [PIPE_FORMAT_R8_UNORM] = NV30_3D_VTXFMT_TYPE_U8_UNORM,
451 [PIPE_FORMAT_R8G8_UNORM] = NV30_3D_VTXFMT_TYPE_U8_UNORM,
452 [PIPE_FORMAT_R8G8B8_UNORM] = NV30_3D_VTXFMT_TYPE_U8_UNORM,
453 [PIPE_FORMAT_R8G8B8A8_UNORM] = NV30_3D_VTXFMT_TYPE_U8_UNORM,
454 [PIPE_FORMAT_R8G8B8A8_USCALED] = NV30_3D_VTXFMT_TYPE_U8_USCALED,
455 [PIPE_FORMAT_R16_SNORM] = NV30_3D_VTXFMT_TYPE_V16_SNORM,
456 [PIPE_FORMAT_R16G16_SNORM] = NV30_3D_VTXFMT_TYPE_V16_SNORM,
457 [PIPE_FORMAT_R16G16B16_SNORM] = NV30_3D_VTXFMT_TYPE_V16_SNORM,
458 [PIPE_FORMAT_R16G16B16A16_SNORM] = NV30_3D_VTXFMT_TYPE_V16_SNORM,
459 [PIPE_FORMAT_R16_SSCALED] = NV30_3D_VTXFMT_TYPE_V16_SSCALED,
460 [PIPE_FORMAT_R16G16_SSCALED] = NV30_3D_VTXFMT_TYPE_V16_SSCALED,
461 [PIPE_FORMAT_R16G16B16_SSCALED] = NV30_3D_VTXFMT_TYPE_V16_SSCALED,
462 [PIPE_FORMAT_R16G16B16A16_SSCALED] = NV30_3D_VTXFMT_TYPE_V16_SSCALED,
463};
464
465static void *
466nvfx_vtxelts_state_create(struct pipe_context *pipe,
467 unsigned num_elements,
468 const struct pipe_vertex_element *elements)
469{
470 struct nvfx_vtxelt_state *cso = CALLOC_STRUCT(nvfx_vtxelt_state);
471 struct translate_key transkey;
472 unsigned per_vertex_size[16];
473 unsigned vb_compacted_index[16];
474
475 if(num_elements > 16)
476 {
477 _debug_printf("Error: application attempted to use %u vertex elements, but only 16 are supported: ignoring the rest\n", num_elements);
478 num_elements = 16;
479 }
480
481 memset(per_vertex_size, 0, sizeof(per_vertex_size));
482 memcpy(cso->pipe, elements, num_elements * sizeof(elements[0]));
483 cso->num_elements = num_elements;
484 cso->needs_translate = FALSE;
485
486 transkey.nr_elements = 0;
487 transkey.output_stride = 0;
488
489 for(unsigned i = 0; i < num_elements; ++i)
490 {
491 const struct pipe_vertex_element* ve = &elements[i];
492 if(!ve->instance_divisor)
493 per_vertex_size[ve->vertex_buffer_index] += util_format_get_stride(ve->src_format, 1);
494 }
495
496 for(unsigned i = 0; i < 16; ++i)
497 {
498 if(per_vertex_size[i])
499 {
500 unsigned idx = cso->num_per_vertex_buffer_infos++;
501 cso->per_vertex_buffer_info[idx].vertex_buffer_index = i;
502 cso->per_vertex_buffer_info[idx].per_vertex_size = per_vertex_size[i];
503 vb_compacted_index[i] = idx;
504 }
505 }
506
507 for(unsigned i = 0; i < num_elements; ++i)
508 {
509 const struct pipe_vertex_element* ve = &elements[i];
510 unsigned type = nvfx_vertex_formats[ve->src_format];
511 unsigned ncomp = util_format_get_nr_components(ve->src_format);
512
513 //if(ve->frequency != PIPE_ELEMENT_FREQUENCY_PER_VERTEX)
514 if(ve->instance_divisor)
515 {
516 struct nvfx_low_frequency_element* lfve;
517 cso->vtxfmt[i] = NV30_3D_VTXFMT_TYPE_V32_FLOAT;
518
519 //if(ve->frequency == PIPE_ELEMENT_FREQUENCY_CONSTANT)
520 if(0)
521 lfve = &cso->constant[cso->num_constant++];
522 else
523 {
524 lfve = &cso->per_instance[cso->num_per_instance++].base;
525 ((struct nvfx_per_instance_element*)lfve)->instance_divisor = ve->instance_divisor;
526 }
527
528 lfve->idx = i;
529 lfve->vertex_buffer_index = ve->vertex_buffer_index;
530 lfve->src_offset = ve->src_offset;
531 lfve->fetch_rgba_float = util_format_description(ve->src_format)->fetch_rgba_float;
532 lfve->ncomp = ncomp;
533 }
534 else
535 {
536 unsigned idx;
537
538 idx = cso->num_per_vertex++;
539 cso->per_vertex[idx].idx = i;
540 cso->per_vertex[idx].vertex_buffer_index = ve->vertex_buffer_index;
541 cso->per_vertex[idx].src_offset = ve->src_offset;
542
543 idx = transkey.nr_elements++;
544 transkey.element[idx].input_format = ve->src_format;
545 transkey.element[idx].input_buffer = vb_compacted_index[ve->vertex_buffer_index];
546 transkey.element[idx].input_offset = ve->src_offset;
547 transkey.element[idx].instance_divisor = 0;
548 transkey.element[idx].type = TRANSLATE_ELEMENT_NORMAL;
549 if(type)
550 {
551 transkey.element[idx].output_format = ve->src_format;
552 cso->vtxfmt[i] = (ncomp << NV30_3D_VTXFMT_SIZE__SHIFT) | type;
553 }
554 else
555 {
556 unsigned float32[4] = {PIPE_FORMAT_R32_FLOAT, PIPE_FORMAT_R32G32_FLOAT, PIPE_FORMAT_R32G32B32_FLOAT, PIPE_FORMAT_R32G32B32A32_FLOAT};
557 transkey.element[idx].output_format = float32[ncomp - 1];
558 cso->needs_translate = TRUE;
559 cso->vtxfmt[i] = (ncomp << NV30_3D_VTXFMT_SIZE__SHIFT) | NV30_3D_VTXFMT_TYPE_V32_FLOAT;
560 }
561 transkey.element[idx].output_offset = transkey.output_stride;
562 transkey.output_stride += (util_format_get_stride(transkey.element[idx].output_format, 1) + 3) & ~3;
563 }
564 }
565
566 cso->translate = translate_create(&transkey);
567 cso->vertex_length = transkey.output_stride >> 2;
568 cso->max_vertices_per_packet = 2047 / MAX2(cso->vertex_length, 1);
569
570 return (void *)cso;
571}
572
573static void
574nvfx_vtxelts_state_delete(struct pipe_context *pipe, void *hwcso)
575{
576 FREE(hwcso);
577}
578
579static void
580nvfx_vtxelts_state_bind(struct pipe_context *pipe, void *hwcso)
581{
582 struct nvfx_context *nvfx = nvfx_context(pipe);
583
584 nvfx->vtxelt = hwcso;
585 nvfx->use_vertex_buffers = -1;
586 nvfx->draw_dirty |= NVFX_NEW_ARRAYS;
587}
588
589static void
590nvfx_set_vertex_buffers(struct pipe_context *pipe, unsigned count,
591 const struct pipe_vertex_buffer *vb)
592{
593 struct nvfx_context *nvfx = nvfx_context(pipe);
594
595 util_copy_vertex_buffers(nvfx->vtxbuf,
596 &nvfx->vtxbuf_nr,
597 vb, count);
598
599 nvfx->use_vertex_buffers = -1;
600 nvfx->draw_dirty |= NVFX_NEW_ARRAYS;
601}
602
603static void
604nvfx_set_index_buffer(struct pipe_context *pipe,
605 const struct pipe_index_buffer *ib)
606{
607 struct nvfx_context *nvfx = nvfx_context(pipe);
608
609 if(ib)
610 {
611 pipe_resource_reference(&nvfx->idxbuf.buffer, ib->buffer);
612 nvfx->idxbuf.index_size = ib->index_size;
613 nvfx->idxbuf.offset = ib->offset;
614 }
615 else
616 {
617 pipe_resource_reference(&nvfx->idxbuf.buffer, 0);
618 nvfx->idxbuf.index_size = 0;
619 nvfx->idxbuf.offset = 0;
620 }
621
622 nvfx->dirty |= NVFX_NEW_INDEX;
623 nvfx->draw_dirty |= NVFX_NEW_INDEX;
624}
625
626void
627nvfx_init_vbo_functions(struct nvfx_context *nvfx)
628{
629 nvfx->pipe.set_vertex_buffers = nvfx_set_vertex_buffers;
630 nvfx->pipe.set_index_buffer = nvfx_set_index_buffer;
631
632 nvfx->pipe.create_vertex_elements_state = nvfx_vtxelts_state_create;
633 nvfx->pipe.delete_vertex_elements_state = nvfx_vtxelts_state_delete;
634 nvfx->pipe.bind_vertex_elements_state = nvfx_vtxelts_state_bind;
635
636 nvfx->pipe.redefine_user_buffer = u_default_redefine_user_buffer;
637}
diff --git a/src/gallium/drivers/nvfx/nvfx_vertprog.c b/src/gallium/drivers/nvfx/nvfx_vertprog.c
deleted file mode 100644
index a11941f3d51..00000000000
--- a/src/gallium/drivers/nvfx/nvfx_vertprog.c
+++ /dev/null
@@ -1,1453 +0,0 @@
1#include "pipe/p_context.h"
2#include "pipe/p_defines.h"
3#include "pipe/p_state.h"
4#include "util/u_linkage.h"
5#include "util/u_debug.h"
6
7#include "pipe/p_shader_tokens.h"
8#include "tgsi/tgsi_parse.h"
9#include "tgsi/tgsi_dump.h"
10#include "tgsi/tgsi_util.h"
11#include "tgsi/tgsi_ureg.h"
12
13#include "draw/draw_context.h"
14
15#include "nvfx_context.h"
16#include "nvfx_state.h"
17#include "nvfx_resource.h"
18
19/* TODO (at least...):
20 * 1. Indexed consts + ARL
21 * 3. NV_vp11, NV_vp2, NV_vp3 features
22 * - extra arith opcodes
23 * - branching
24 * - texture sampling
25 * - indexed attribs
26 * - indexed results
27 * 4. bugs
28 */
29
30#include "nv30_vertprog.h"
31#include "nv40_vertprog.h"
32
33struct nvfx_loop_entry
34{
35 unsigned brk_target;
36 unsigned cont_target;
37};
38
39struct nvfx_vpc {
40 struct nvfx_context* nvfx;
41 struct pipe_shader_state pipe;
42 struct nvfx_vertex_program *vp;
43 struct tgsi_shader_info* info;
44
45 struct nvfx_vertex_program_exec *vpi;
46
47 unsigned r_temps;
48 unsigned r_temps_discard;
49 struct nvfx_reg r_result[PIPE_MAX_SHADER_OUTPUTS];
50 struct nvfx_reg *r_address;
51 struct nvfx_reg *r_temp;
52 struct nvfx_reg *r_const;
53 struct nvfx_reg r_0_1;
54
55 struct nvfx_reg *imm;
56 unsigned nr_imm;
57
58 unsigned hpos_idx;
59
60 struct util_dynarray label_relocs;
61 struct util_dynarray loop_stack;
62};
63
64static struct nvfx_reg
65temp(struct nvfx_vpc *vpc)
66{
67 int idx = ffs(~vpc->r_temps) - 1;
68
69 if (idx < 0) {
70 NOUVEAU_ERR("out of temps!!\n");
71 assert(0);
72 return nvfx_reg(NVFXSR_TEMP, 0);
73 }
74
75 vpc->r_temps |= (1 << idx);
76 vpc->r_temps_discard |= (1 << idx);
77 return nvfx_reg(NVFXSR_TEMP, idx);
78}
79
80static inline void
81release_temps(struct nvfx_vpc *vpc)
82{
83 vpc->r_temps &= ~vpc->r_temps_discard;
84 vpc->r_temps_discard = 0;
85}
86
87static struct nvfx_reg
88constant(struct nvfx_vpc *vpc, int pipe, float x, float y, float z, float w)
89{
90 struct nvfx_vertex_program *vp = vpc->vp;
91 struct nvfx_vertex_program_data *vpd;
92 int idx;
93
94 if (pipe >= 0) {
95 for (idx = 0; idx < vp->nr_consts; idx++) {
96 if (vp->consts[idx].index == pipe)
97 return nvfx_reg(NVFXSR_CONST, idx);
98 }
99 }
100
101 idx = vp->nr_consts++;
102 vp->consts = realloc(vp->consts, sizeof(*vpd) * vp->nr_consts);
103 vpd = &vp->consts[idx];
104
105 vpd->index = pipe;
106 vpd->value[0] = x;
107 vpd->value[1] = y;
108 vpd->value[2] = z;
109 vpd->value[3] = w;
110 return nvfx_reg(NVFXSR_CONST, idx);
111}
112
113#define arith(s,t,o,d,m,s0,s1,s2) \
114 nvfx_insn((s), (NVFX_VP_INST_SLOT_##t << 7) | NVFX_VP_INST_##t##_OP_##o, -1, (d), (m), (s0), (s1), (s2))
115
116static void
117emit_src(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int pos, struct nvfx_src src)
118{
119 struct nvfx_vertex_program *vp = vpc->vp;
120 uint32_t sr = 0;
121 struct nvfx_relocation reloc;
122
123 switch (src.reg.type) {
124 case NVFXSR_TEMP:
125 sr |= (NVFX_VP(SRC_REG_TYPE_TEMP) << NVFX_VP(SRC_REG_TYPE_SHIFT));
126 sr |= (src.reg.index << NVFX_VP(SRC_TEMP_SRC_SHIFT));
127 break;
128 case NVFXSR_INPUT:
129 sr |= (NVFX_VP(SRC_REG_TYPE_INPUT) <<
130 NVFX_VP(SRC_REG_TYPE_SHIFT));
131 vp->ir |= (1 << src.reg.index);
132 hw[1] |= (src.reg.index << NVFX_VP(INST_INPUT_SRC_SHIFT));
133 break;
134 case NVFXSR_CONST:
135 sr |= (NVFX_VP(SRC_REG_TYPE_CONST) <<
136 NVFX_VP(SRC_REG_TYPE_SHIFT));
137 reloc.location = vp->nr_insns - 1;
138 reloc.target = src.reg.index;
139 util_dynarray_append(&vp->const_relocs, struct nvfx_relocation, reloc);
140 break;
141 case NVFXSR_NONE:
142 sr |= (NVFX_VP(SRC_REG_TYPE_INPUT) <<
143 NVFX_VP(SRC_REG_TYPE_SHIFT));
144 break;
145 default:
146 assert(0);
147 }
148
149 if (src.negate)
150 sr |= NVFX_VP(SRC_NEGATE);
151
152 if (src.abs)
153 hw[0] |= (1 << (21 + pos));
154
155 sr |= ((src.swz[0] << NVFX_VP(SRC_SWZ_X_SHIFT)) |
156 (src.swz[1] << NVFX_VP(SRC_SWZ_Y_SHIFT)) |
157 (src.swz[2] << NVFX_VP(SRC_SWZ_Z_SHIFT)) |
158 (src.swz[3] << NVFX_VP(SRC_SWZ_W_SHIFT)));
159
160 if(src.indirect) {
161 if(src.reg.type == NVFXSR_CONST)
162 hw[3] |= NVFX_VP(INST_INDEX_CONST);
163 else if(src.reg.type == NVFXSR_INPUT)
164 hw[0] |= NVFX_VP(INST_INDEX_INPUT);
165 else
166 assert(0);
167 if(src.indirect_reg)
168 hw[0] |= NVFX_VP(INST_ADDR_REG_SELECT_1);
169 hw[0] |= src.indirect_swz << NVFX_VP(INST_ADDR_SWZ_SHIFT);
170 }
171
172 switch (pos) {
173 case 0:
174 hw[1] |= ((sr & NVFX_VP(SRC0_HIGH_MASK)) >>
175 NVFX_VP(SRC0_HIGH_SHIFT)) << NVFX_VP(INST_SRC0H_SHIFT);
176 hw[2] |= (sr & NVFX_VP(SRC0_LOW_MASK)) <<
177 NVFX_VP(INST_SRC0L_SHIFT);
178 break;
179 case 1:
180 hw[2] |= sr << NVFX_VP(INST_SRC1_SHIFT);
181 break;
182 case 2:
183 hw[2] |= ((sr & NVFX_VP(SRC2_HIGH_MASK)) >>
184 NVFX_VP(SRC2_HIGH_SHIFT)) << NVFX_VP(INST_SRC2H_SHIFT);
185 hw[3] |= (sr & NVFX_VP(SRC2_LOW_MASK)) <<
186 NVFX_VP(INST_SRC2L_SHIFT);
187 break;
188 default:
189 assert(0);
190 }
191}
192
193static void
194emit_dst(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int slot, struct nvfx_reg dst)
195{
196 struct nvfx_vertex_program *vp = vpc->vp;
197
198 switch (dst.type) {
199 case NVFXSR_NONE:
200 if(!nvfx->is_nv4x)
201 hw[0] |= NV30_VP_INST_DEST_TEMP_ID_MASK;
202 else {
203 hw[3] |= NV40_VP_INST_DEST_MASK;
204 if (slot == 0)
205 hw[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK;
206 else
207 hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;
208 }
209 break;
210 case NVFXSR_TEMP:
211 if(!nvfx->is_nv4x)
212 hw[0] |= (dst.index << NV30_VP_INST_DEST_TEMP_ID_SHIFT);
213 else {
214 hw[3] |= NV40_VP_INST_DEST_MASK;
215 if (slot == 0)
216 hw[0] |= (dst.index << NV40_VP_INST_VEC_DEST_TEMP_SHIFT);
217 else
218 hw[3] |= (dst.index << NV40_VP_INST_SCA_DEST_TEMP_SHIFT);
219 }
220 break;
221 case NVFXSR_OUTPUT:
222 /* TODO: this may be wrong because on nv30 COL0 and BFC0 are swapped */
223 if(nvfx->is_nv4x) {
224 switch (dst.index) {
225 case NV30_VP_INST_DEST_CLP(0):
226 dst.index = NVFX_VP(INST_DEST_FOGC);
227 break;
228 case NV30_VP_INST_DEST_CLP(1):
229 dst.index = NVFX_VP(INST_DEST_FOGC);
230 break;
231 case NV30_VP_INST_DEST_CLP(2):
232 dst.index = NVFX_VP(INST_DEST_FOGC);
233 break;
234 case NV30_VP_INST_DEST_CLP(3):
235 dst.index = NVFX_VP(INST_DEST_PSZ);
236 break;
237 case NV30_VP_INST_DEST_CLP(4):
238 dst.index = NVFX_VP(INST_DEST_PSZ);
239 break;
240 case NV30_VP_INST_DEST_CLP(5):
241 dst.index = NVFX_VP(INST_DEST_PSZ);
242 break;
243 case NV40_VP_INST_DEST_COL0 : vp->or |= (1 << 0); break;
244 case NV40_VP_INST_DEST_COL1 : vp->or |= (1 << 1); break;
245 case NV40_VP_INST_DEST_BFC0 : vp->or |= (1 << 2); break;
246 case NV40_VP_INST_DEST_BFC1 : vp->or |= (1 << 3); break;
247 case NV40_VP_INST_DEST_FOGC: vp->or |= (1 << 4); break;
248 case NV40_VP_INST_DEST_PSZ : vp->or |= (1 << 5); break;
249 }
250 }
251
252 if(!nvfx->is_nv4x) {
253 hw[3] |= (dst.index << NV30_VP_INST_DEST_SHIFT);
254 hw[0] |= NV30_VP_INST_VEC_DEST_TEMP_MASK;
255
256 /*XXX: no way this is entirely correct, someone needs to
257 * figure out what exactly it is.
258 */
259 hw[3] |= 0x800;
260 } else {
261 hw[3] |= (dst.index << NV40_VP_INST_DEST_SHIFT);
262 if (slot == 0) {
263 hw[0] |= NV40_VP_INST_VEC_RESULT;
264 hw[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK;
265 } else {
266 hw[3] |= NV40_VP_INST_SCA_RESULT;
267 hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;
268 }
269 }
270 break;
271 default:
272 assert(0);
273 }
274}
275
276static void
277nvfx_vp_emit(struct nvfx_vpc *vpc, struct nvfx_insn insn)
278{
279 struct nvfx_context* nvfx = vpc->nvfx;
280 struct nvfx_vertex_program *vp = vpc->vp;
281 unsigned slot = insn.op >> 7;
282 unsigned op = insn.op & 0x7f;
283 uint32_t *hw;
284
285 vp->insns = realloc(vp->insns, ++vp->nr_insns * sizeof(*vpc->vpi));
286 vpc->vpi = &vp->insns[vp->nr_insns - 1];
287 memset(vpc->vpi, 0, sizeof(*vpc->vpi));
288
289 hw = vpc->vpi->data;
290
291 hw[0] |= (insn.cc_test << NVFX_VP(INST_COND_SHIFT));
292 hw[0] |= ((insn.cc_swz[0] << NVFX_VP(INST_COND_SWZ_X_SHIFT)) |
293 (insn.cc_swz[1] << NVFX_VP(INST_COND_SWZ_Y_SHIFT)) |
294 (insn.cc_swz[2] << NVFX_VP(INST_COND_SWZ_Z_SHIFT)) |
295 (insn.cc_swz[3] << NVFX_VP(INST_COND_SWZ_W_SHIFT)));
296 if(insn.cc_update)
297 hw[0] |= NVFX_VP(INST_COND_UPDATE_ENABLE);
298
299 if(insn.sat)
300 {
301 assert(nvfx->use_nv4x);
302 if(nvfx->use_nv4x)
303 hw[0] |= NV40_VP_INST_SATURATE;
304 }
305
306 if(!nvfx->is_nv4x) {
307 if(slot == 0)
308 hw[1] |= (op << NV30_VP_INST_VEC_OPCODE_SHIFT);
309 else
310 {
311 hw[0] |= ((op >> 4) << NV30_VP_INST_SCA_OPCODEH_SHIFT);
312 hw[1] |= ((op & 0xf) << NV30_VP_INST_SCA_OPCODEL_SHIFT);
313 }
314// hw[3] |= NVFX_VP(INST_SCA_DEST_TEMP_MASK);
315// hw[3] |= (mask << NVFX_VP(INST_VEC_WRITEMASK_SHIFT));
316
317 if (insn.dst.type == NVFXSR_OUTPUT) {
318 if (slot)
319 hw[3] |= (insn.mask << NV30_VP_INST_SDEST_WRITEMASK_SHIFT);
320 else
321 hw[3] |= (insn.mask << NV30_VP_INST_VDEST_WRITEMASK_SHIFT);
322 } else {
323 if (slot)
324 hw[3] |= (insn.mask << NV30_VP_INST_STEMP_WRITEMASK_SHIFT);
325 else
326 hw[3] |= (insn.mask << NV30_VP_INST_VTEMP_WRITEMASK_SHIFT);
327 }
328 } else {
329 if (slot == 0) {
330 hw[1] |= (op << NV40_VP_INST_VEC_OPCODE_SHIFT);
331 hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;
332 hw[3] |= (insn.mask << NV40_VP_INST_VEC_WRITEMASK_SHIFT);
333 } else {
334 hw[1] |= (op << NV40_VP_INST_SCA_OPCODE_SHIFT);
335 hw[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK ;
336 hw[3] |= (insn.mask << NV40_VP_INST_SCA_WRITEMASK_SHIFT);
337 }
338 }
339
340 emit_dst(nvfx, vpc, hw, slot, insn.dst);
341 emit_src(nvfx, vpc, hw, 0, insn.src[0]);
342 emit_src(nvfx, vpc, hw, 1, insn.src[1]);
343 emit_src(nvfx, vpc, hw, 2, insn.src[2]);
344
345// if(insn.src[0].indirect || op == NVFX_VP_INST_VEC_OP_ARL)
346// hw[3] |= NV40_VP_INST_SCA_RESULT;
347}
348
349static inline struct nvfx_src
350tgsi_src(struct nvfx_vpc *vpc, const struct tgsi_full_src_register *fsrc) {
351 struct nvfx_src src;
352
353 switch (fsrc->Register.File) {
354 case TGSI_FILE_INPUT:
355 src.reg = nvfx_reg(NVFXSR_INPUT, fsrc->Register.Index);
356 break;
357 case TGSI_FILE_CONSTANT:
358 src.reg = vpc->r_const[fsrc->Register.Index];
359 break;
360 case TGSI_FILE_IMMEDIATE:
361 src.reg = vpc->imm[fsrc->Register.Index];
362 break;
363 case TGSI_FILE_TEMPORARY:
364 src.reg = vpc->r_temp[fsrc->Register.Index];
365 break;
366 default:
367 NOUVEAU_ERR("bad src file\n");
368 src.reg.index = 0;
369 src.reg.type = -1;
370 break;
371 }
372
373 src.abs = fsrc->Register.Absolute;
374 src.negate = fsrc->Register.Negate;
375 src.swz[0] = fsrc->Register.SwizzleX;
376 src.swz[1] = fsrc->Register.SwizzleY;
377 src.swz[2] = fsrc->Register.SwizzleZ;
378 src.swz[3] = fsrc->Register.SwizzleW;
379 src.indirect = 0;
380 src.indirect_reg = 0;
381 src.indirect_swz = 0;
382
383 if(fsrc->Register.Indirect) {
384 if(fsrc->Indirect.File == TGSI_FILE_ADDRESS &&
385 (fsrc->Register.File == TGSI_FILE_CONSTANT || fsrc->Register.File == TGSI_FILE_INPUT))
386 {
387 src.indirect = 1;
388 src.indirect_reg = fsrc->Indirect.Index;
389 src.indirect_swz = fsrc->Indirect.SwizzleX;
390 }
391 else
392 {
393 src.reg.index = 0;
394 src.reg.type = -1;
395 }
396 }
397 return src;
398}
399
400static INLINE struct nvfx_reg
401tgsi_dst(struct nvfx_vpc *vpc, const struct tgsi_full_dst_register *fdst) {
402 struct nvfx_reg dst;
403
404 switch (fdst->Register.File) {
405 case TGSI_FILE_NULL:
406 dst = nvfx_reg(NVFXSR_NONE, 0);
407 break;
408 case TGSI_FILE_OUTPUT:
409 dst = vpc->r_result[fdst->Register.Index];
410 break;
411 case TGSI_FILE_TEMPORARY:
412 dst = vpc->r_temp[fdst->Register.Index];
413 break;
414 case TGSI_FILE_ADDRESS:
415 dst = vpc->r_address[fdst->Register.Index];
416 break;
417 default:
418 NOUVEAU_ERR("bad dst file %i\n", fdst->Register.File);
419 dst.index = 0;
420 dst.type = 0;
421 break;
422 }
423
424 return dst;
425}
426
427static inline int
428tgsi_mask(uint tgsi)
429{
430 int mask = 0;
431
432 if (tgsi & TGSI_WRITEMASK_X) mask |= NVFX_VP_MASK_X;
433 if (tgsi & TGSI_WRITEMASK_Y) mask |= NVFX_VP_MASK_Y;
434 if (tgsi & TGSI_WRITEMASK_Z) mask |= NVFX_VP_MASK_Z;
435 if (tgsi & TGSI_WRITEMASK_W) mask |= NVFX_VP_MASK_W;
436 return mask;
437}
438
439static boolean
440nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
441 unsigned idx, const struct tgsi_full_instruction *finst)
442{
443 struct nvfx_src src[3], tmp;
444 struct nvfx_reg dst;
445 struct nvfx_reg final_dst;
446 struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0));
447 struct nvfx_insn insn;
448 struct nvfx_relocation reloc;
449 struct nvfx_loop_entry loop;
450 boolean sat = FALSE;
451 int mask;
452 int ai = -1, ci = -1, ii = -1;
453 int i;
454 unsigned sub_depth = 0;
455
456 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
457 const struct tgsi_full_src_register *fsrc;
458
459 fsrc = &finst->Src[i];
460 if (fsrc->Register.File == TGSI_FILE_TEMPORARY) {
461 src[i] = tgsi_src(vpc, fsrc);
462 }
463 }
464
465 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
466 const struct tgsi_full_src_register *fsrc;
467
468 fsrc = &finst->Src[i];
469
470 switch (fsrc->Register.File) {
471 case TGSI_FILE_INPUT:
472 if (ai == -1 || ai == fsrc->Register.Index) {
473 ai = fsrc->Register.Index;
474 src[i] = tgsi_src(vpc, fsrc);
475 } else {
476 src[i] = nvfx_src(temp(vpc));
477 nvfx_vp_emit(vpc, arith(0, VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, tgsi_src(vpc, fsrc), none, none));
478 }
479 break;
480 case TGSI_FILE_CONSTANT:
481 if ((ci == -1 && ii == -1) ||
482 ci == fsrc->Register.Index) {
483 ci = fsrc->Register.Index;
484 src[i] = tgsi_src(vpc, fsrc);
485 } else {
486 src[i] = nvfx_src(temp(vpc));
487 nvfx_vp_emit(vpc, arith(0, VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, tgsi_src(vpc, fsrc), none, none));
488 }
489 break;
490 case TGSI_FILE_IMMEDIATE:
491 if ((ci == -1 && ii == -1) ||
492 ii == fsrc->Register.Index) {
493 ii = fsrc->Register.Index;
494 src[i] = tgsi_src(vpc, fsrc);
495 } else {
496 src[i] = nvfx_src(temp(vpc));
497 nvfx_vp_emit(vpc, arith(0, VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, tgsi_src(vpc, fsrc), none, none));
498 }
499 break;
500 case TGSI_FILE_TEMPORARY:
501 /* handled above */
502 break;
503 default:
504 NOUVEAU_ERR("bad src file\n");
505 return FALSE;
506 }
507 }
508
509 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
510 if(src[i].reg.type < 0)
511 return FALSE;
512 }
513
514 if(finst->Dst[0].Register.File == TGSI_FILE_ADDRESS &&
515 finst->Instruction.Opcode != TGSI_OPCODE_ARL)
516 return FALSE;
517
518 final_dst = dst = tgsi_dst(vpc, &finst->Dst[0]);
519 mask = tgsi_mask(finst->Dst[0].Register.WriteMask);
520 if(finst->Instruction.Saturate == TGSI_SAT_ZERO_ONE)
521 {
522 assert(finst->Instruction.Opcode != TGSI_OPCODE_ARL);
523 if(nvfx->use_nv4x)
524 sat = TRUE;
525 else if(dst.type != NVFXSR_TEMP)
526 dst = temp(vpc);
527 }
528
529 switch (finst->Instruction.Opcode) {
530 case TGSI_OPCODE_ABS:
531 nvfx_vp_emit(vpc, arith(sat, VEC, MOV, dst, mask, abs(src[0]), none, none));
532 break;
533 case TGSI_OPCODE_ADD:
534 nvfx_vp_emit(vpc, arith(sat, VEC, ADD, dst, mask, src[0], none, src[1]));
535 break;
536 case TGSI_OPCODE_ARL:
537 nvfx_vp_emit(vpc, arith(0, VEC, ARL, dst, mask, src[0], none, none));
538 break;
539 case TGSI_OPCODE_CMP:
540 insn = arith(0, VEC, MOV, none.reg, mask, src[0], none, none);
541 insn.cc_update = 1;
542 nvfx_vp_emit(vpc, insn);
543
544 insn = arith(sat, VEC, MOV, dst, mask, src[2], none, none);
545 insn.cc_test = NVFX_COND_GE;
546 nvfx_vp_emit(vpc, insn);
547
548 insn = arith(sat, VEC, MOV, dst, mask, src[1], none, none);
549 insn.cc_test = NVFX_COND_LT;
550 nvfx_vp_emit(vpc, insn);
551 break;
552 case TGSI_OPCODE_COS:
553 nvfx_vp_emit(vpc, arith(sat, SCA, COS, dst, mask, none, none, src[0]));
554 break;
555 case TGSI_OPCODE_DP2:
556 tmp = nvfx_src(temp(vpc));
557 nvfx_vp_emit(vpc, arith(0, VEC, MUL, tmp.reg, NVFX_VP_MASK_X | NVFX_VP_MASK_Y, src[0], src[1], none));
558 nvfx_vp_emit(vpc, arith(sat, VEC, ADD, dst, mask, swz(tmp, X, X, X, X), none, swz(tmp, Y, Y, Y, Y)));
559 break;
560 case TGSI_OPCODE_DP3:
561 nvfx_vp_emit(vpc, arith(sat, VEC, DP3, dst, mask, src[0], src[1], none));
562 break;
563 case TGSI_OPCODE_DP4:
564 nvfx_vp_emit(vpc, arith(sat, VEC, DP4, dst, mask, src[0], src[1], none));
565 break;
566 case TGSI_OPCODE_DPH:
567 nvfx_vp_emit(vpc, arith(sat, VEC, DPH, dst, mask, src[0], src[1], none));
568 break;
569 case TGSI_OPCODE_DST:
570 nvfx_vp_emit(vpc, arith(sat, VEC, DST, dst, mask, src[0], src[1], none));
571 break;
572 case TGSI_OPCODE_EX2:
573 nvfx_vp_emit(vpc, arith(sat, SCA, EX2, dst, mask, none, none, src[0]));
574 break;
575 case TGSI_OPCODE_EXP:
576 nvfx_vp_emit(vpc, arith(sat, SCA, EXP, dst, mask, none, none, src[0]));
577 break;
578 case TGSI_OPCODE_FLR:
579 nvfx_vp_emit(vpc, arith(sat, VEC, FLR, dst, mask, src[0], none, none));
580 break;
581 case TGSI_OPCODE_FRC:
582 nvfx_vp_emit(vpc, arith(sat, VEC, FRC, dst, mask, src[0], none, none));
583 break;
584 case TGSI_OPCODE_LG2:
585 nvfx_vp_emit(vpc, arith(sat, SCA, LG2, dst, mask, none, none, src[0]));
586 break;
587 case TGSI_OPCODE_LIT:
588 nvfx_vp_emit(vpc, arith(sat, SCA, LIT, dst, mask, none, none, src[0]));
589 break;
590 case TGSI_OPCODE_LOG:
591 nvfx_vp_emit(vpc, arith(sat, SCA, LOG, dst, mask, none, none, src[0]));
592 break;
593 case TGSI_OPCODE_LRP:
594 tmp = nvfx_src(temp(vpc));
595 nvfx_vp_emit(vpc, arith(0, VEC, MAD, tmp.reg, mask, neg(src[0]), src[2], src[2]));
596 nvfx_vp_emit(vpc, arith(sat, VEC, MAD, dst, mask, src[0], src[1], tmp));
597 break;
598 case TGSI_OPCODE_MAD:
599 nvfx_vp_emit(vpc, arith(sat, VEC, MAD, dst, mask, src[0], src[1], src[2]));
600 break;
601 case TGSI_OPCODE_MAX:
602 nvfx_vp_emit(vpc, arith(sat, VEC, MAX, dst, mask, src[0], src[1], none));
603 break;
604 case TGSI_OPCODE_MIN:
605 nvfx_vp_emit(vpc, arith(sat, VEC, MIN, dst, mask, src[0], src[1], none));
606 break;
607 case TGSI_OPCODE_MOV:
608 nvfx_vp_emit(vpc, arith(sat, VEC, MOV, dst, mask, src[0], none, none));
609 break;
610 case TGSI_OPCODE_MUL:
611 nvfx_vp_emit(vpc, arith(sat, VEC, MUL, dst, mask, src[0], src[1], none));
612 break;
613 case TGSI_OPCODE_NOP:
614 break;
615 case TGSI_OPCODE_POW:
616 tmp = nvfx_src(temp(vpc));
617 nvfx_vp_emit(vpc, arith(0, SCA, LG2, tmp.reg, NVFX_VP_MASK_X, none, none, swz(src[0], X, X, X, X)));
618 nvfx_vp_emit(vpc, arith(0, VEC, MUL, tmp.reg, NVFX_VP_MASK_X, swz(tmp, X, X, X, X), swz(src[1], X, X, X, X), none));
619 nvfx_vp_emit(vpc, arith(sat, SCA, EX2, dst, mask, none, none, swz(tmp, X, X, X, X)));
620 break;
621 case TGSI_OPCODE_RCP:
622 nvfx_vp_emit(vpc, arith(sat, SCA, RCP, dst, mask, none, none, src[0]));
623 break;
624 case TGSI_OPCODE_RSQ:
625 nvfx_vp_emit(vpc, arith(sat, SCA, RSQ, dst, mask, none, none, abs(src[0])));
626 break;
627 case TGSI_OPCODE_SEQ:
628 nvfx_vp_emit(vpc, arith(sat, VEC, SEQ, dst, mask, src[0], src[1], none));
629 break;
630 case TGSI_OPCODE_SFL:
631 nvfx_vp_emit(vpc, arith(sat, VEC, SFL, dst, mask, src[0], src[1], none));
632 break;
633 case TGSI_OPCODE_SGE:
634 nvfx_vp_emit(vpc, arith(sat, VEC, SGE, dst, mask, src[0], src[1], none));
635 break;
636 case TGSI_OPCODE_SGT:
637 nvfx_vp_emit(vpc, arith(sat, VEC, SGT, dst, mask, src[0], src[1], none));
638 break;
639 case TGSI_OPCODE_SIN:
640 nvfx_vp_emit(vpc, arith(sat, SCA, SIN, dst, mask, none, none, src[0]));
641 break;
642 case TGSI_OPCODE_SLE:
643 nvfx_vp_emit(vpc, arith(sat, VEC, SLE, dst, mask, src[0], src[1], none));
644 break;
645 case TGSI_OPCODE_SLT:
646 nvfx_vp_emit(vpc, arith(sat, VEC, SLT, dst, mask, src[0], src[1], none));
647 break;
648 case TGSI_OPCODE_SNE:
649 nvfx_vp_emit(vpc, arith(sat, VEC, SNE, dst, mask, src[0], src[1], none));
650 break;
651 case TGSI_OPCODE_SSG:
652 nvfx_vp_emit(vpc, arith(sat, VEC, SSG, dst, mask, src[0], src[1], none));
653 break;
654 case TGSI_OPCODE_STR:
655 nvfx_vp_emit(vpc, arith(sat, VEC, STR, dst, mask, src[0], src[1], none));
656 break;
657 case TGSI_OPCODE_SUB:
658 nvfx_vp_emit(vpc, arith(sat, VEC, ADD, dst, mask, src[0], none, neg(src[1])));
659 break;
660 case TGSI_OPCODE_TRUNC:
661 tmp = nvfx_src(temp(vpc));
662 insn = arith(0, VEC, MOV, none.reg, mask, src[0], none, none);
663 insn.cc_update = 1;
664 nvfx_vp_emit(vpc, insn);
665
666 nvfx_vp_emit(vpc, arith(0, VEC, FLR, tmp.reg, mask, abs(src[0]), none, none));
667 nvfx_vp_emit(vpc, arith(sat, VEC, MOV, dst, mask, tmp, none, none));
668
669 insn = arith(sat, VEC, MOV, dst, mask, neg(tmp), none, none);
670 insn.cc_test = NVFX_COND_LT;
671 nvfx_vp_emit(vpc, insn);
672 break;
673 case TGSI_OPCODE_XPD:
674 tmp = nvfx_src(temp(vpc));
675 nvfx_vp_emit(vpc, arith(0, VEC, MUL, tmp.reg, mask, swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none));
676 nvfx_vp_emit(vpc, arith(sat, VEC, MAD, dst, (mask & ~NVFX_VP_MASK_W), swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y), neg(tmp)));
677 break;
678
679 case TGSI_OPCODE_IF:
680 insn = arith(0, VEC, MOV, none.reg, NVFX_VP_MASK_X, src[0], none, none);
681 insn.cc_update = 1;
682 nvfx_vp_emit(vpc, insn);
683
684 reloc.location = vpc->vp->nr_insns;
685 reloc.target = finst->Label.Label + 1;
686 util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc);
687
688 insn = arith(0, SCA, BRA, none.reg, 0, none, none, none);
689 insn.cc_test = NVFX_COND_EQ;
690 insn.cc_swz[0] = insn.cc_swz[1] = insn.cc_swz[2] = insn.cc_swz[3] = 0;
691 nvfx_vp_emit(vpc, insn);
692 break;
693
694 case TGSI_OPCODE_ELSE:
695 case TGSI_OPCODE_BRA:
696 case TGSI_OPCODE_CAL:
697 reloc.location = vpc->vp->nr_insns;
698 reloc.target = finst->Label.Label;
699 util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc);
700
701 if(finst->Instruction.Opcode == TGSI_OPCODE_CAL)
702 insn = arith(0, SCA, CAL, none.reg, 0, none, none, none);
703 else
704 insn = arith(0, SCA, BRA, none.reg, 0, none, none, none);
705 nvfx_vp_emit(vpc, insn);
706 break;
707
708 case TGSI_OPCODE_RET:
709 if(sub_depth || !nvfx->use_vp_clipping) {
710 tmp = none;
711 tmp.swz[0] = tmp.swz[1] = tmp.swz[2] = tmp.swz[3] = 0;
712 nvfx_vp_emit(vpc, arith(0, SCA, RET, none.reg, 0, none, none, tmp));
713 } else {
714 reloc.location = vpc->vp->nr_insns;
715 reloc.target = vpc->info->num_instructions;
716 util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc);
717 nvfx_vp_emit(vpc, arith(0, SCA, BRA, none.reg, 0, none, none, none));
718 }
719 break;
720
721 case TGSI_OPCODE_BGNSUB:
722 ++sub_depth;
723 break;
724 case TGSI_OPCODE_ENDSUB:
725 --sub_depth;
726 break;
727 case TGSI_OPCODE_ENDIF:
728 /* nothing to do here */
729 break;
730
731 case TGSI_OPCODE_BGNLOOP:
732 loop.cont_target = idx;
733 loop.brk_target = finst->Label.Label + 1;
734 util_dynarray_append(&vpc->loop_stack, struct nvfx_loop_entry, loop);
735 break;
736
737 case TGSI_OPCODE_ENDLOOP:
738 loop = util_dynarray_pop(&vpc->loop_stack, struct nvfx_loop_entry);
739
740 reloc.location = vpc->vp->nr_insns;
741 reloc.target = loop.cont_target;
742 util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc);
743
744 nvfx_vp_emit(vpc, arith(0, SCA, BRA, none.reg, 0, none, none, none));
745 break;
746
747 case TGSI_OPCODE_CONT:
748 loop = util_dynarray_top(&vpc->loop_stack, struct nvfx_loop_entry);
749
750 reloc.location = vpc->vp->nr_insns;
751 reloc.target = loop.cont_target;
752 util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc);
753
754 nvfx_vp_emit(vpc, arith(0, SCA, BRA, none.reg, 0, none, none, none));
755 break;
756
757 case TGSI_OPCODE_BRK:
758 loop = util_dynarray_top(&vpc->loop_stack, struct nvfx_loop_entry);
759
760 reloc.location = vpc->vp->nr_insns;
761 reloc.target = loop.brk_target;
762 util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc);
763
764 nvfx_vp_emit(vpc, arith(0, SCA, BRA, none.reg, 0, none, none, none));
765 break;
766
767 case TGSI_OPCODE_END:
768 assert(!sub_depth);
769 if(nvfx->use_vp_clipping) {
770 if(idx != (vpc->info->num_instructions - 1)) {
771 reloc.location = vpc->vp->nr_insns;
772 reloc.target = vpc->info->num_instructions;
773 util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc);
774 nvfx_vp_emit(vpc, arith(0, SCA, BRA, none.reg, 0, none, none, none));
775 }
776 } else {
777 if(vpc->vp->nr_insns)
778 vpc->vp->insns[vpc->vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST;
779 nvfx_vp_emit(vpc, arith(0, VEC, NOP, none.reg, 0, none, none, none));
780 vpc->vp->insns[vpc->vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST;
781 }
782 break;
783
784 default:
785 NOUVEAU_ERR("invalid opcode %d\n", finst->Instruction.Opcode);
786 return FALSE;
787 }
788
789 if(finst->Instruction.Saturate == TGSI_SAT_ZERO_ONE && !nvfx->use_nv4x)
790 {
791 if(!vpc->r_0_1.type)
792 vpc->r_0_1 = constant(vpc, -1, 0, 1, 0, 0);
793 nvfx_vp_emit(vpc, arith(0, VEC, MAX, dst, mask, nvfx_src(dst), swz(nvfx_src(vpc->r_0_1), X, X, X, X), none));
794 nvfx_vp_emit(vpc, arith(0, VEC, MIN, final_dst, mask, nvfx_src(dst), swz(nvfx_src(vpc->r_0_1), Y, Y, Y, Y), none));
795 }
796
797 release_temps(vpc);
798 return TRUE;
799}
800
801static boolean
802nvfx_vertprog_parse_decl_output(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
803 const struct tgsi_full_declaration *fdec)
804{
805 unsigned idx = fdec->Range.First;
806 int hw;
807
808 switch (fdec->Semantic.Name) {
809 case TGSI_SEMANTIC_POSITION:
810 hw = NVFX_VP(INST_DEST_POS);
811 vpc->hpos_idx = idx;
812 break;
813 case TGSI_SEMANTIC_COLOR:
814 if (fdec->Semantic.Index == 0) {
815 hw = NVFX_VP(INST_DEST_COL0);
816 } else
817 if (fdec->Semantic.Index == 1) {
818 hw = NVFX_VP(INST_DEST_COL1);
819 } else {
820 NOUVEAU_ERR("bad colour semantic index\n");
821 return FALSE;
822 }
823 break;
824 case TGSI_SEMANTIC_BCOLOR:
825 if (fdec->Semantic.Index == 0) {
826 hw = NVFX_VP(INST_DEST_BFC0);
827 } else
828 if (fdec->Semantic.Index == 1) {
829 hw = NVFX_VP(INST_DEST_BFC1);
830 } else {
831 NOUVEAU_ERR("bad bcolour semantic index\n");
832 return FALSE;
833 }
834 break;
835 case TGSI_SEMANTIC_FOG:
836 hw = NVFX_VP(INST_DEST_FOGC);
837 break;
838 case TGSI_SEMANTIC_PSIZE:
839 hw = NVFX_VP(INST_DEST_PSZ);
840 break;
841 case TGSI_SEMANTIC_GENERIC:
842 hw = (vpc->vp->generic_to_fp_input[fdec->Semantic.Index] & 0xf) - NVFX_FP_OP_INPUT_SRC_TC(0);
843 if(hw <= 8)
844 hw = NVFX_VP(INST_DEST_TC(hw));
845 else if(hw == 9) /* TODO: this is correct, but how does this overlapping work exactly? */
846 hw = NV40_VP_INST_DEST_PSZ;
847 else
848 assert(0);
849 break;
850 case TGSI_SEMANTIC_EDGEFLAG:
851 /* not really an error just a fallback */
852 NOUVEAU_ERR("cannot handle edgeflag output\n");
853 return FALSE;
854 default:
855 NOUVEAU_ERR("bad output semantic\n");
856 return FALSE;
857 }
858
859 vpc->r_result[idx] = nvfx_reg(NVFXSR_OUTPUT, hw);
860 return TRUE;
861}
862
863static boolean
864nvfx_vertprog_prepare(struct nvfx_context* nvfx, struct nvfx_vpc *vpc)
865{
866 struct tgsi_parse_context p;
867 int high_const = -1, high_temp = -1, high_addr = -1, nr_imm = 0, i;
868 struct util_semantic_set set;
869 unsigned char sem_layout[10];
870 unsigned num_outputs;
871 unsigned num_texcoords = nvfx->is_nv4x ? 10 : 8;
872
873 num_outputs = util_semantic_set_from_program_file(&set, vpc->pipe.tokens, TGSI_FILE_OUTPUT);
874
875 if(num_outputs > num_texcoords) {
876 NOUVEAU_ERR("too many vertex program outputs: %i\n", num_outputs);
877 return FALSE;
878 }
879 util_semantic_layout_from_set(sem_layout, &set, num_texcoords, num_texcoords);
880
881 /* hope 0xf is (0, 0, 0, 1) initialized; otherwise, we are _probably_ not required to do this */
882 memset(vpc->vp->generic_to_fp_input, 0x0f, sizeof(vpc->vp->generic_to_fp_input));
883 for(int i = 0; i < num_texcoords; ++i) {
884 if(sem_layout[i] == 0xff)
885 continue;
886 //printf("vp: GENERIC[%i] to fpreg %i\n", sem_layout[i], NVFX_FP_OP_INPUT_SRC_TC(0) + i);
887 vpc->vp->generic_to_fp_input[sem_layout[i]] = 0xf0 | NVFX_FP_OP_INPUT_SRC_TC(i);
888 }
889
890 vpc->vp->sprite_fp_input = -1;
891 for(int i = 0; i < num_texcoords; ++i)
892 {
893 if(sem_layout[i] == 0xff)
894 {
895 vpc->vp->sprite_fp_input = NVFX_FP_OP_INPUT_SRC_TC(i);
896 break;
897 }
898 }
899
900 tgsi_parse_init(&p, vpc->pipe.tokens);
901 while (!tgsi_parse_end_of_tokens(&p)) {
902 const union tgsi_full_token *tok = &p.FullToken;
903
904 tgsi_parse_token(&p);
905 switch(tok->Token.Type) {
906 case TGSI_TOKEN_TYPE_IMMEDIATE:
907 nr_imm++;
908 break;
909 case TGSI_TOKEN_TYPE_DECLARATION:
910 {
911 const struct tgsi_full_declaration *fdec;
912
913 fdec = &p.FullToken.FullDeclaration;
914 switch (fdec->Declaration.File) {
915 case TGSI_FILE_TEMPORARY:
916 if (fdec->Range.Last > high_temp) {
917 high_temp =
918 fdec->Range.Last;
919 }
920 break;
921 case TGSI_FILE_ADDRESS:
922 if (fdec->Range.Last > high_addr) {
923 high_addr =
924 fdec->Range.Last;
925 }
926 break;
927 case TGSI_FILE_CONSTANT:
928 if (fdec->Range.Last > high_const) {
929 high_const =
930 fdec->Range.Last;
931 }
932 break;
933 case TGSI_FILE_OUTPUT:
934 if (!nvfx_vertprog_parse_decl_output(nvfx, vpc, fdec))
935 return FALSE;
936 break;
937 default:
938 break;
939 }
940 }
941 break;
942 default:
943 break;
944 }
945 }
946 tgsi_parse_free(&p);
947
948 if (nr_imm) {
949 vpc->imm = CALLOC(nr_imm, sizeof(struct nvfx_reg));
950 assert(vpc->imm);
951 }
952
953 if (++high_temp) {
954 vpc->r_temp = CALLOC(high_temp, sizeof(struct nvfx_reg));
955 for (i = 0; i < high_temp; i++)
956 vpc->r_temp[i] = temp(vpc);
957 }
958
959 if (++high_addr) {
960 vpc->r_address = CALLOC(high_addr, sizeof(struct nvfx_reg));
961 for (i = 0; i < high_addr; i++)
962 vpc->r_address[i] = nvfx_reg(NVFXSR_TEMP, i);
963 }
964
965 if(++high_const) {
966 vpc->r_const = CALLOC(high_const, sizeof(struct nvfx_reg));
967 for (i = 0; i < high_const; i++)
968 vpc->r_const[i] = constant(vpc, i, 0, 0, 0, 0);
969 }
970
971 vpc->r_temps_discard = 0;
972 return TRUE;
973}
974
975DEBUG_GET_ONCE_BOOL_OPTION(nvfx_dump_vp, "NVFX_DUMP_VP", FALSE)
976
977static struct nvfx_vertex_program*
978nvfx_vertprog_translate(struct nvfx_context *nvfx, const struct pipe_shader_state* vps, struct tgsi_shader_info* info)
979{
980 struct tgsi_parse_context parse;
981 struct nvfx_vertex_program* vp = NULL;
982 struct nvfx_vpc *vpc = NULL;
983 struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0));
984 struct util_dynarray insns;
985 int i;
986
987 tgsi_parse_init(&parse, vps->tokens);
988
989 vp = CALLOC_STRUCT(nvfx_vertex_program);
990 if(!vp)
991 goto out_err;
992
993 vpc = CALLOC_STRUCT(nvfx_vpc);
994 if (!vpc)
995 goto out_err;
996
997 vpc->nvfx = nvfx;
998 vpc->vp = vp;
999 vpc->pipe = *vps;
1000 vpc->info = info;
1001
1002 {
1003 // TODO: use a 64-bit atomic here!
1004 static unsigned long long id = 0;
1005 vp->id = ++id;
1006 }
1007
1008 /* reserve space for ucps */
1009 if(nvfx->use_vp_clipping)
1010 {
1011 for(i = 0; i < 6; ++i)
1012 constant(vpc, -1, 0, 0, 0, 0);
1013 }
1014
1015 if (!nvfx_vertprog_prepare(nvfx, vpc)) {
1016 FREE(vpc);
1017 return NULL;
1018 }
1019
1020 /* Redirect post-transform vertex position to a temp if user clip
1021 * planes are enabled. We need to append code to the vtxprog
1022 * to handle clip planes later.
1023 */
1024 /* TODO: maybe support patching this depending on whether there are ucps: not sure if it is really matters much */
1025 if (nvfx->use_vp_clipping) {
1026 vpc->r_result[vpc->hpos_idx] = temp(vpc);
1027 vpc->r_temps_discard = 0;
1028 }
1029
1030 util_dynarray_init(&insns);
1031 while (!tgsi_parse_end_of_tokens(&parse)) {
1032 tgsi_parse_token(&parse);
1033
1034 switch (parse.FullToken.Token.Type) {
1035 case TGSI_TOKEN_TYPE_IMMEDIATE:
1036 {
1037 const struct tgsi_full_immediate *imm;
1038
1039 imm = &parse.FullToken.FullImmediate;
1040 assert(imm->Immediate.DataType == TGSI_IMM_FLOAT32);
1041 assert(imm->Immediate.NrTokens == 4 + 1);
1042 vpc->imm[vpc->nr_imm++] =
1043 constant(vpc, -1,
1044 imm->u[0].Float,
1045 imm->u[1].Float,
1046 imm->u[2].Float,
1047 imm->u[3].Float);
1048 }
1049 break;
1050 case TGSI_TOKEN_TYPE_INSTRUCTION:
1051 {
1052 const struct tgsi_full_instruction *finst;
1053 unsigned idx = insns.size >> 2;
1054 util_dynarray_append(&insns, unsigned, vp->nr_insns);
1055 finst = &parse.FullToken.FullInstruction;
1056 if (!nvfx_vertprog_parse_instruction(nvfx, vpc, idx, finst))
1057 goto out_err;
1058 }
1059 break;
1060 default:
1061 break;
1062 }
1063 }
1064
1065 util_dynarray_append(&insns, unsigned, vp->nr_insns);
1066
1067 for(unsigned i = 0; i < vpc->label_relocs.size; i += sizeof(struct nvfx_relocation))
1068 {
1069 struct nvfx_relocation* label_reloc = (struct nvfx_relocation*)((char*)vpc->label_relocs.data + i);
1070 struct nvfx_relocation hw_reloc;
1071
1072 hw_reloc.location = label_reloc->location;
1073 hw_reloc.target = ((unsigned*)insns.data)[label_reloc->target];
1074
1075 //debug_printf("hw %u -> tgsi %u = hw %u\n", hw_reloc.location, label_reloc->target, hw_reloc.target);
1076
1077 util_dynarray_append(&vp->branch_relocs, struct nvfx_relocation, hw_reloc);
1078 }
1079 util_dynarray_fini(&insns);
1080 util_dynarray_trim(&vp->branch_relocs);
1081
1082 /* XXX: what if we add a RET before?! make sure we jump here...*/
1083
1084 /* Write out HPOS if it was redirected to a temp earlier */
1085 if (vpc->r_result[vpc->hpos_idx].type != NVFXSR_OUTPUT) {
1086 struct nvfx_reg hpos = nvfx_reg(NVFXSR_OUTPUT,
1087 NVFX_VP(INST_DEST_POS));
1088 struct nvfx_src htmp = nvfx_src(vpc->r_result[vpc->hpos_idx]);
1089
1090 nvfx_vp_emit(vpc, arith(0, VEC, MOV, hpos, NVFX_VP_MASK_ALL, htmp, none, none));
1091 }
1092
1093 /* Insert code to handle user clip planes */
1094 if(nvfx->use_vp_clipping)
1095 {
1096 for (i = 0; i < 6; i++) {
1097 struct nvfx_reg cdst = nvfx_reg(NVFXSR_OUTPUT, NV30_VP_INST_DEST_CLP(i));
1098 struct nvfx_src ceqn = nvfx_src(nvfx_reg(NVFXSR_CONST, i));
1099 struct nvfx_src htmp = nvfx_src(vpc->r_result[vpc->hpos_idx]);
1100 unsigned mask;
1101
1102 if(nvfx->is_nv4x)
1103 {
1104 switch (i) {
1105 case 0: case 3: mask = NVFX_VP_MASK_Y; break;
1106 case 1: case 4: mask = NVFX_VP_MASK_Z; break;
1107 case 2: case 5: mask = NVFX_VP_MASK_W; break;
1108 default:
1109 NOUVEAU_ERR("invalid clip dist #%d\n", i);
1110 goto out_err;
1111 }
1112 }
1113 else
1114 mask = NVFX_VP_MASK_X;
1115
1116 nvfx_vp_emit(vpc, arith(0, VEC, DP4, cdst, mask, htmp, ceqn, none));
1117 }
1118 }
1119
1120 if(debug_get_option_nvfx_dump_vp())
1121 {
1122 debug_printf("\n");
1123 tgsi_dump(vpc->pipe.tokens, 0);
1124
1125 debug_printf("\n%s vertex program:\n", nvfx->is_nv4x ? "nv4x" : "nv3x");
1126 for (i = 0; i < vp->nr_insns; i++)
1127 debug_printf("%3u: %08x %08x %08x %08x\n", i, vp->insns[i].data[0], vp->insns[i].data[1], vp->insns[i].data[2], vp->insns[i].data[3]);
1128 debug_printf("\n");
1129 }
1130
1131 vp->clip_nr = -1;
1132 vp->exec_start = -1;
1133
1134out:
1135 tgsi_parse_free(&parse);
1136 if(vpc) {
1137 util_dynarray_fini(&vpc->label_relocs);
1138 util_dynarray_fini(&vpc->loop_stack);
1139 FREE(vpc->r_temp);
1140 FREE(vpc->r_address);
1141 FREE(vpc->r_const);
1142 FREE(vpc->imm);
1143 FREE(vpc);
1144 }
1145 return vp;
1146
1147out_err:
1148 FREE(vp);
1149 vp = NULL;
1150 goto out;
1151}
1152
1153static struct nvfx_vertex_program*
1154nvfx_vertprog_translate_draw_vp(struct nvfx_context *nvfx, struct nvfx_pipe_vertex_program* pvp)
1155{
1156 struct nvfx_vertex_program* vp = NULL;
1157 struct pipe_shader_state vps;
1158 struct tgsi_shader_info info;
1159 struct ureg_program *ureg = NULL;
1160 unsigned num_outputs = MIN2(pvp->info.num_outputs, 16);
1161
1162 ureg = ureg_create( TGSI_PROCESSOR_VERTEX );
1163 if(ureg == NULL)
1164 return 0;
1165
1166 for (unsigned i = 0; i < num_outputs; i++)
1167 ureg_MOV(ureg, ureg_DECL_output(ureg, pvp->info.output_semantic_name[i], pvp->info.output_semantic_index[i]), ureg_DECL_vs_input(ureg, i));
1168
1169 ureg_END( ureg );
1170
1171 vps.tokens = ureg_get_tokens(ureg, 0);
1172 tgsi_scan_shader(vps.tokens, &info);
1173 vp = nvfx_vertprog_translate(nvfx, &vps, &info);
1174 ureg_free_tokens(vps.tokens);
1175 ureg_destroy(ureg);
1176
1177 return vp;
1178}
1179
1180boolean
1181nvfx_vertprog_validate(struct nvfx_context *nvfx)
1182{
1183 struct nvfx_screen *screen = nvfx->screen;
1184 struct nouveau_channel *chan = screen->base.channel;
1185 struct nouveau_grobj *eng3d = screen->eng3d;
1186 struct nvfx_pipe_vertex_program *pvp = nvfx->vertprog;
1187 struct nvfx_vertex_program* vp;
1188 struct pipe_resource *constbuf;
1189 boolean upload_code = FALSE, upload_data = FALSE;
1190 int i;
1191
1192 if (nvfx->render_mode == HW) {
1193 nvfx->fallback_swtnl &= ~NVFX_NEW_VERTPROG;
1194 vp = pvp->vp;
1195
1196 if(!vp) {
1197 vp = nvfx_vertprog_translate(nvfx, &pvp->pipe, &pvp->info);
1198 if(!vp)
1199 vp = NVFX_VP_FAILED;
1200 pvp->vp = vp;
1201 }
1202
1203 if(vp == NVFX_VP_FAILED) {
1204 nvfx->fallback_swtnl |= NVFX_NEW_VERTPROG;
1205 return FALSE;
1206 }
1207
1208 constbuf = nvfx->constbuf[PIPE_SHADER_VERTEX];
1209 } else {
1210 vp = pvp->draw_vp;
1211 if(!vp)
1212 {
1213 pvp->draw_vp = vp = nvfx_vertprog_translate_draw_vp(nvfx, pvp);
1214 if(!vp) {
1215 _debug_printf("Error: unable to create a swtnl passthrough vertex shader: aborting.");
1216 abort();
1217 }
1218 }
1219 constbuf = NULL;
1220 }
1221
1222 nvfx->hw_vertprog = vp;
1223
1224 /* Allocate hw vtxprog exec slots */
1225 if (!vp->exec) {
1226 struct nouveau_resource *heap = nvfx->screen->vp_exec_heap;
1227 uint vplen = vp->nr_insns;
1228
1229 if (nouveau_resource_alloc(heap, vplen, vp, &vp->exec)) {
1230 while (heap->next && heap->size < vplen) {
1231 struct nvfx_vertex_program *evict;
1232
1233 evict = heap->next->priv;
1234 nouveau_resource_free(&evict->exec);
1235 }
1236
1237 if (nouveau_resource_alloc(heap, vplen, vp, &vp->exec))
1238 {
1239 debug_printf("Vertex shader too long: %u instructions\n", vplen);
1240 nvfx->fallback_swtnl |= NVFX_NEW_VERTPROG;
1241 return FALSE;
1242 }
1243 }
1244
1245 upload_code = TRUE;
1246 }
1247
1248 /* Allocate hw vtxprog const slots */
1249 if (vp->nr_consts && !vp->data) {
1250 struct nouveau_resource *heap = nvfx->screen->vp_data_heap;
1251
1252 if (nouveau_resource_alloc(heap, vp->nr_consts, vp, &vp->data)) {
1253 while (heap->next && heap->size < vp->nr_consts) {
1254 struct nvfx_vertex_program *evict;
1255
1256 evict = heap->next->priv;
1257 nouveau_resource_free(&evict->data);
1258 }
1259
1260 if (nouveau_resource_alloc(heap, vp->nr_consts, vp, &vp->data))
1261 {
1262 debug_printf("Vertex shader uses too many constants: %u constants\n", vp->nr_consts);
1263 nvfx->fallback_swtnl |= NVFX_NEW_VERTPROG;
1264 return FALSE;
1265 }
1266 }
1267
1268 //printf("start at %u nc %u\n", vp->data->start, vp->nr_consts);
1269
1270 /*XXX: handle this some day */
1271 assert(vp->data->start >= vp->data_start_min);
1272
1273 upload_data = TRUE;
1274 if (vp->data_start != vp->data->start)
1275 upload_code = TRUE;
1276 }
1277
1278 /* If exec or data segments moved we need to patch the program to
1279 * fixup offsets and register IDs.
1280 */
1281 if (vp->exec_start != vp->exec->start) {
1282 //printf("vp_relocs %u -> %u\n", vp->exec_start, vp->exec->start);
1283 for(unsigned i = 0; i < vp->branch_relocs.size; i += sizeof(struct nvfx_relocation))
1284 {
1285 struct nvfx_relocation* reloc = (struct nvfx_relocation*)((char*)vp->branch_relocs.data + i);
1286 uint32_t* hw = vp->insns[reloc->location].data;
1287 unsigned target = vp->exec->start + reloc->target;
1288
1289 //debug_printf("vp_reloc hw %u -> hw %u\n", reloc->location, target);
1290
1291 if(!nvfx->is_nv4x)
1292 {
1293 hw[2] &=~ NV30_VP_INST_IADDR_MASK;
1294 hw[2] |= (target & 0x1ff) << NV30_VP_INST_IADDR_SHIFT;
1295 }
1296 else
1297 {
1298 hw[3] &=~ NV40_VP_INST_IADDRL_MASK;
1299 hw[3] |= (target & 7) << NV40_VP_INST_IADDRL_SHIFT;
1300
1301 hw[2] &=~ NV40_VP_INST_IADDRH_MASK;
1302 hw[2] |= ((target >> 3) & 0x3f) << NV40_VP_INST_IADDRH_SHIFT;
1303 }
1304 }
1305
1306 vp->exec_start = vp->exec->start;
1307 }
1308
1309 if (vp->data_start != vp->data->start) {
1310 for(unsigned i = 0; i < vp->const_relocs.size; i += sizeof(struct nvfx_relocation))
1311 {
1312 struct nvfx_relocation* reloc = (struct nvfx_relocation*)((char*)vp->const_relocs.data + i);
1313 struct nvfx_vertex_program_exec *vpi = &vp->insns[reloc->location];
1314
1315 //printf("reloc %i to %i + %i\n", reloc->location, vp->data->start, reloc->target);
1316
1317 vpi->data[1] &= ~NVFX_VP(INST_CONST_SRC_MASK);
1318 vpi->data[1] |=
1319 (reloc->target + vp->data->start) <<
1320 NVFX_VP(INST_CONST_SRC_SHIFT);
1321 }
1322
1323 vp->data_start = vp->data->start;
1324 upload_code = TRUE;
1325 }
1326
1327 /* Update + Upload constant values */
1328 if (vp->nr_consts) {
1329 float *map = NULL;
1330
1331 if (constbuf)
1332 map = (float*)nvfx_buffer(constbuf)->data;
1333
1334 /*
1335 * WAIT_RING(chan, 512 * 6);
1336 for (i = 0; i < 512; i++) {
1337 float v[4] = {0.1, 0,2, 0.3, 0.4};
1338 OUT_RING(chan, RING_3D(NV30_3D_VP_UPLOAD_CONST_ID, 5));
1339 OUT_RING(chan, i);
1340 OUT_RINGp(chan, (uint32_t *)v, 4);
1341 printf("frob %i\n", i);
1342 }
1343 */
1344
1345 for (i = nvfx->use_vp_clipping ? 6 : 0; i < vp->nr_consts; i++) {
1346 struct nvfx_vertex_program_data *vpd = &vp->consts[i];
1347
1348 if (vpd->index >= 0) {
1349 if (!upload_data &&
1350 !memcmp(vpd->value, &map[vpd->index * 4],
1351 4 * sizeof(float)))
1352 continue;
1353 memcpy(vpd->value, &map[vpd->index * 4],
1354 4 * sizeof(float));
1355 }
1356
1357 //printf("upload into %i + %i: %f %f %f %f\n", vp->data->start, i, vpd->value[0], vpd->value[1], vpd->value[2], vpd->value[3]);
1358
1359 BEGIN_RING(chan, eng3d, NV30_3D_VP_UPLOAD_CONST_ID, 5);
1360 OUT_RING(chan, i + vp->data->start);
1361 OUT_RINGp(chan, (uint32_t *)vpd->value, 4);
1362 }
1363 }
1364
1365 /* Upload vtxprog */
1366 if (upload_code) {
1367 BEGIN_RING(chan, eng3d, NV30_3D_VP_UPLOAD_FROM_ID, 1);
1368 OUT_RING(chan, vp->exec->start);
1369 for (i = 0; i < vp->nr_insns; i++) {
1370 BEGIN_RING(chan, eng3d, NV30_3D_VP_UPLOAD_INST(0), 4);
1371 //printf("%08x %08x %08x %08x\n", vp->insns[i].data[0], vp->insns[i].data[1], vp->insns[i].data[2], vp->insns[i].data[3]);
1372 OUT_RINGp(chan, vp->insns[i].data, 4);
1373 }
1374 vp->clip_nr = -1;
1375 }
1376
1377 if(nvfx->dirty & (NVFX_NEW_VERTPROG))
1378 {
1379 BEGIN_RING(chan, eng3d, NV30_3D_VP_START_FROM_ID, 1);
1380 OUT_RING(chan, vp->exec->start);
1381 if(nvfx->is_nv4x) {
1382 BEGIN_RING(chan, eng3d, NV40_3D_VP_ATTRIB_EN, 1);
1383 OUT_RING(chan, vp->ir);
1384 }
1385 }
1386
1387 return TRUE;
1388}
1389
1390void
1391nvfx_vertprog_destroy(struct nvfx_context *nvfx, struct nvfx_vertex_program *vp)
1392{
1393 if (vp->nr_insns)
1394 FREE(vp->insns);
1395
1396 if (vp->nr_consts)
1397 FREE(vp->consts);
1398
1399 nouveau_resource_free(&vp->exec);
1400 nouveau_resource_free(&vp->data);
1401
1402 util_dynarray_fini(&vp->branch_relocs);
1403 util_dynarray_fini(&vp->const_relocs);
1404 FREE(vp);
1405}
1406
1407static void *
1408nvfx_vp_state_create(struct pipe_context *pipe, const struct pipe_shader_state *cso)
1409{
1410 struct nvfx_pipe_vertex_program *pvp;
1411
1412 pvp = CALLOC(1, sizeof(struct nvfx_pipe_vertex_program));
1413 pvp->pipe.tokens = tgsi_dup_tokens(cso->tokens);
1414 tgsi_scan_shader(pvp->pipe.tokens, &pvp->info);
1415 pvp->draw_elements = MAX2(1, MIN2(pvp->info.num_outputs, 16));
1416 pvp->draw_no_elements = pvp->info.num_outputs == 0;
1417
1418 return (void *)pvp;
1419}
1420
1421static void
1422nvfx_vp_state_bind(struct pipe_context *pipe, void *hwcso)
1423{
1424 struct nvfx_context *nvfx = nvfx_context(pipe);
1425
1426 nvfx->vertprog = hwcso;
1427 nvfx->dirty |= NVFX_NEW_VERTPROG;
1428 nvfx->draw_dirty |= NVFX_NEW_VERTPROG;
1429}
1430
1431static void
1432nvfx_vp_state_delete(struct pipe_context *pipe, void *hwcso)
1433{
1434 struct nvfx_context *nvfx = nvfx_context(pipe);
1435 struct nvfx_pipe_vertex_program *pvp = hwcso;
1436
1437 if(pvp->draw_vs)
1438 draw_delete_vertex_shader(nvfx->draw, pvp->draw_vs);
1439 if(pvp->vp && pvp->vp != NVFX_VP_FAILED)
1440 nvfx_vertprog_destroy(nvfx, pvp->vp);
1441 if(pvp->draw_vp)
1442 nvfx_vertprog_destroy(nvfx, pvp->draw_vp);
1443 FREE((void*)pvp->pipe.tokens);
1444 FREE(pvp);
1445}
1446
1447void
1448nvfx_init_vertprog_functions(struct nvfx_context *nvfx)
1449{
1450 nvfx->pipe.create_vs_state = nvfx_vp_state_create;
1451 nvfx->pipe.bind_vs_state = nvfx_vp_state_bind;
1452 nvfx->pipe.delete_vs_state = nvfx_vp_state_delete;
1453}
diff --git a/src/gallium/targets/dri-nouveau/Makefile b/src/gallium/targets/dri-nouveau/Makefile
index dacb85ced82..03279aad88e 100644
--- a/src/gallium/targets/dri-nouveau/Makefile
+++ b/src/gallium/targets/dri-nouveau/Makefile
@@ -8,7 +8,6 @@ PIPE_DRIVERS = \
8 $(TOP)/src/gallium/winsys/nouveau/drm/libnouveaudrm.a \ 8 $(TOP)/src/gallium/winsys/nouveau/drm/libnouveaudrm.a \
9 $(TOP)/src/gallium/drivers/trace/libtrace.a \ 9 $(TOP)/src/gallium/drivers/trace/libtrace.a \
10 $(TOP)/src/gallium/drivers/rbug/librbug.a \ 10 $(TOP)/src/gallium/drivers/rbug/librbug.a \
11 $(TOP)/src/gallium/drivers/nvfx/libnvfx.a \
12 $(TOP)/src/gallium/drivers/nv50/libnv50.a \ 11 $(TOP)/src/gallium/drivers/nv50/libnv50.a \
13 $(TOP)/src/gallium/drivers/nvc0/libnvc0.a \ 12 $(TOP)/src/gallium/drivers/nvc0/libnvc0.a \
14 $(TOP)/src/gallium/drivers/nouveau/libnouveau.a 13 $(TOP)/src/gallium/drivers/nouveau/libnouveau.a
diff --git a/src/gallium/targets/vdpau-nouveau/Makefile b/src/gallium/targets/vdpau-nouveau/Makefile
index d3f1c7df8db..b5be875ede1 100644
--- a/src/gallium/targets/vdpau-nouveau/Makefile
+++ b/src/gallium/targets/vdpau-nouveau/Makefile
@@ -7,7 +7,6 @@ DRIVER_INCLUDES = $(shell $(PKG_CONFIG) libdrm --cflags-only-I)
7 7
8PIPE_DRIVERS = \ 8PIPE_DRIVERS = \
9 $(TOP)/src/gallium/winsys/nouveau/drm/libnouveaudrm.a \ 9 $(TOP)/src/gallium/winsys/nouveau/drm/libnouveaudrm.a \
10 $(TOP)/src/gallium/drivers/nvfx/libnvfx.a \
11 $(TOP)/src/gallium/drivers/nv50/libnv50.a \ 10 $(TOP)/src/gallium/drivers/nv50/libnv50.a \
12 $(TOP)/src/gallium/drivers/nvc0/libnvc0.a \ 11 $(TOP)/src/gallium/drivers/nvc0/libnvc0.a \
13 $(TOP)/src/gallium/drivers/nouveau/libnouveau.a \ 12 $(TOP)/src/gallium/drivers/nouveau/libnouveau.a \
diff --git a/src/gallium/targets/xorg-nouveau/Makefile b/src/gallium/targets/xorg-nouveau/Makefile
index 72899db98cd..f8334111bf6 100644
--- a/src/gallium/targets/xorg-nouveau/Makefile
+++ b/src/gallium/targets/xorg-nouveau/Makefile
@@ -13,7 +13,6 @@ DRIVER_DEFINES = \
13DRIVER_PIPES = \ 13DRIVER_PIPES = \
14 $(TOP)/src/gallium/state_trackers/xorg/libxorgtracker.a \ 14 $(TOP)/src/gallium/state_trackers/xorg/libxorgtracker.a \
15 $(TOP)/src/gallium/winsys/nouveau/drm/libnouveaudrm.a \ 15 $(TOP)/src/gallium/winsys/nouveau/drm/libnouveaudrm.a \
16 $(TOP)/src/gallium/drivers/nvfx/libnvfx.a \
17 $(TOP)/src/gallium/drivers/nv50/libnv50.a \ 16 $(TOP)/src/gallium/drivers/nv50/libnv50.a \
18 $(TOP)/src/gallium/drivers/nvc0/libnvc0.a \ 17 $(TOP)/src/gallium/drivers/nvc0/libnvc0.a \
19 $(TOP)/src/gallium/drivers/nouveau/libnouveau.a \ 18 $(TOP)/src/gallium/drivers/nouveau/libnouveau.a \
diff --git a/src/gallium/targets/xvmc-nouveau/Makefile b/src/gallium/targets/xvmc-nouveau/Makefile
index 06727f1c9f8..1d687e35643 100644
--- a/src/gallium/targets/xvmc-nouveau/Makefile
+++ b/src/gallium/targets/xvmc-nouveau/Makefile
@@ -5,7 +5,6 @@ LIBBASENAME = XvMCnouveau
5 5
6PIPE_DRIVERS = \ 6PIPE_DRIVERS = \
7 $(TOP)/src/gallium/winsys/nouveau/drm/libnouveaudrm.a \ 7 $(TOP)/src/gallium/winsys/nouveau/drm/libnouveaudrm.a \
8 $(TOP)/src/gallium/drivers/nvfx/libnvfx.a \
9 $(TOP)/src/gallium/drivers/nv50/libnv50.a \ 8 $(TOP)/src/gallium/drivers/nv50/libnv50.a \
10 $(TOP)/src/gallium/drivers/nvc0/libnvc0.a \ 9 $(TOP)/src/gallium/drivers/nvc0/libnvc0.a \
11 $(TOP)/src/gallium/drivers/nouveau/libnouveau.a \ 10 $(TOP)/src/gallium/drivers/nouveau/libnouveau.a \
diff --git a/src/gallium/winsys/nouveau/drm/nouveau_drm_winsys.c b/src/gallium/winsys/nouveau/drm/nouveau_drm_winsys.c
index 084eda96b2a..0cbcc4b2a93 100644
--- a/src/gallium/winsys/nouveau/drm/nouveau_drm_winsys.c
+++ b/src/gallium/winsys/nouveau/drm/nouveau_drm_winsys.c
@@ -25,11 +25,13 @@ nouveau_drm_screen_create(int fd)
25 return NULL; 25 return NULL;
26 26
27 switch (dev->chipset & 0xf0) { 27 switch (dev->chipset & 0xf0) {
28#if 0
28 case 0x30: 29 case 0x30:
29 case 0x40: 30 case 0x40:
30 case 0x60: 31 case 0x60:
31 init = nvfx_screen_create; 32 init = nv30_screen_create;
32 break; 33 break;
34#endif
33 case 0x50: 35 case 0x50:
34 case 0x80: 36 case 0x80:
35 case 0x90: 37 case 0x90:
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-27 00:28:40 +0000