diff options
author | Dave Airlie <airlied@redhat.com> | 2011-12-05 15:41:24 +0000 |
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committer | Dave Airlie <airlied@redhat.com> | 2011-12-05 15:41:24 +0000 |
commit | 5c666bdfdb7681c2250b801ff286c4837ea36893 (patch) | |
tree | 7d0b8a346dfebd04b90b2ec39dfbe5c995e2c02a | |
parent | b2596c36c8f73e8bb7a0b1679b491662aeb2f9d9 (diff) |
radeon: add some tiling support for r100.
This sets up the tiling flags on the blitter.
Fixes some piglit tests with tiling enabled.
Signed-off-by: Dave Airlie <airlied@redhat.com>
-rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_blit.c | 11 | ||||
-rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_state_init.c | 2 |
2 files changed, 13 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/radeon/radeon_blit.c b/src/mesa/drivers/dri/radeon/radeon_blit.c index b84f2fa9f2b..4233221165f 100644 --- a/src/mesa/drivers/dri/radeon/radeon_blit.c +++ b/src/mesa/drivers/dri/radeon/radeon_blit.c @@ -136,12 +136,17 @@ static void inline emit_tx_setup(struct r100_context *r100, case MESA_FORMAT_AL88: txformat |= RADEON_TXFORMAT_AI88 | RADEON_TXFORMAT_ALPHA_IN_MAP; break; default: break; } + + if (bo->flags & RADEON_BO_FLAGS_MACRO_TILE) + offset |= RADEON_TXO_MACRO_TILE; + if (bo->flags & RADEON_BO_FLAGS_MICRO_TILE) + offset |= RADEON_TXO_MICRO_TILE_X2; BEGIN_BATCH(18); OUT_BATCH_REGVAL(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE); OUT_BATCH_REGVAL(RADEON_PP_TXCBLEND_0, (RADEON_COLOR_ARG_A_ZERO | RADEON_COLOR_ARG_B_ZERO | RADEON_COLOR_ARG_C_T0_COLOR | @@ -200,12 +205,18 @@ static inline void emit_cb_setup(struct r100_context *r100, dst_format = RADEON_COLOR_FORMAT_RGB8; break; default: break; } + if (bo->flags & RADEON_BO_FLAGS_MACRO_TILE) + dst_pitch |= RADEON_COLOR_TILE_ENABLE; + + if (bo->flags & RADEON_BO_FLAGS_MICRO_TILE) + dst_pitch |= RADEON_COLOR_MICROTILE_ENABLE; + BEGIN_BATCH_NO_AUTOSTATE(18); OUT_BATCH_REGVAL(RADEON_RE_TOP_LEFT, 0); OUT_BATCH_REGVAL(RADEON_RE_WIDTH_HEIGHT, ((width << RADEON_RE_WIDTH_SHIFT) | (height << RADEON_RE_HEIGHT_SHIFT))); OUT_BATCH_REGVAL(RADEON_RB3D_PLANEMASK, 0xffffffff); OUT_BATCH_REGVAL(RADEON_RB3D_BLENDCNTL, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO); diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index eb31fe895cf..8edba6ec9de 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -348,12 +348,14 @@ static void ctx_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) _mesa_problem(ctx, "unexpected format in ctx_emit_cs()"); } cbpitch = (rrb->pitch / rrb->cpp); if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) cbpitch |= R200_COLOR_TILE_ENABLE; + if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE) + cbpitch |= RADEON_COLOR_MICROTILE_ENABLE; drb = radeon_get_depthbuffer(&r100->radeon); if (drb) { zbpitch = (drb->pitch / drb->cpp); if (drb->cpp == 4) depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; |