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| author | Zhigang Gong <zhigang.gong@intel.com> | 2015-05-04 15:15:11 +0800 |
|---|---|---|
| committer | Zhigang Gong <zhigang.gong@intel.com> | 2015-05-04 15:15:11 +0800 |
| commit | 83f8739b6fc4893fac60145326052ccb5cf653dc (patch) | |
| tree | a72fe4399f2b97100ec04ba904fd8da4097b62da | |
| parent | 0bbe78f4676a7e268153b71d26bde2d4365ffd23 (diff) | |
Revert "CL/Driver: enable atomics in L3 for HSW."
This issue should be fixed in KMD in the future. Let's revert it
here.
This reverts commit ef7127c03bd533277afc443b335c37a69927250a.
| -rw-r--r-- | src/intel/intel_defines.h | 4 | ||||
| -rw-r--r-- | src/intel/intel_gpgpu.c | 11 |
2 files changed, 1 insertions, 14 deletions
diff --git a/src/intel/intel_defines.h b/src/intel/intel_defines.h index 651e2854..1080a91a 100644 --- a/src/intel/intel_defines.h +++ b/src/intel/intel_defines.h @@ -305,10 +305,6 @@ #define URB_SIZE(intel) (IS_IGDNG(intel->device_id) ? 1024 : \ IS_G4X(intel->device_id) ? 384 : 256) -// HSW -#define HSW_SCRATCH1_OFFSET (0xB038) -#define HSW_ROW_CHICKEN3_HDC_OFFSET (0xE49C) - // L3 cache stuff #define GEN7_L3_SQC_REG1_ADDRESS_OFFSET (0XB010) #define GEN7_L3_CNTL_REG2_ADDRESS_OFFSET (0xB020) diff --git a/src/intel/intel_gpgpu.c b/src/intel/intel_gpgpu.c index ab4545e0..b083dab5 100644 --- a/src/intel/intel_gpgpu.c +++ b/src/intel/intel_gpgpu.c @@ -719,16 +719,7 @@ static void intel_gpgpu_set_L3_gen75(intel_gpgpu_t *gpgpu, uint32_t use_slm) { /* still set L3 in batch buffer for fulsim. */ - BEGIN_BATCH(gpgpu->batch, 15); - OUT_BATCH(gpgpu->batch, CMD_LOAD_REGISTER_IMM | 1); /* length - 2 */ - /* FIXME: KMD always disable the atomic in L3 for some reason. - I checked the spec, and don't think we need that workaround now. - Before I send a patch to kernel, let's just enable it here. */ - OUT_BATCH(gpgpu->batch, HSW_SCRATCH1_OFFSET); - OUT_BATCH(gpgpu->batch, 0); /* enable atomic in L3 */ - OUT_BATCH(gpgpu->batch, CMD_LOAD_REGISTER_IMM | 1); /* length - 2 */ - OUT_BATCH(gpgpu->batch, HSW_ROW_CHICKEN3_HDC_OFFSET); - OUT_BATCH(gpgpu->batch, (1 << 6ul) << 16); /* enable atomic in L3 */ + BEGIN_BATCH(gpgpu->batch, 9); OUT_BATCH(gpgpu->batch, CMD_LOAD_REGISTER_IMM | 1); /* length - 2 */ OUT_BATCH(gpgpu->batch, GEN7_L3_SQC_REG1_ADDRESS_OFFSET); OUT_BATCH(gpgpu->batch, 0x08800000); |