summaryrefslogtreecommitdiff
path: root/src/i965_render.c
AgeCommit message (Collapse)AuthorFilesLines
2013-09-06Enable the Bay Trail platform.Zhao Halley1-1/+1
This patch adds PCI IDs for Bay Trail (sometimes called Valley View). As far as the video driver is concerned, it's very similar to Ivybridge GT1 except VP8 decoding support. (cherry picked from commit b3afeef8092dc4eb7cb73fce672ddf7a55205f34)
2013-06-21Update the supported render target format and pixel formatXiang, Haihao1-2/+2
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2013-06-09Update max_wm_threads on HaswellXiang, Haihao1-6/+8
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit c31f6130793c68a83d1cb1116da60489d5e4a1d4)
2013-06-09Fix Haswell GT3Xiang, Haihao1-0/+2
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit 3c9e778718cb4d24695a880afb45e32cdf43a434)
2013-04-03Merge branch 'master' into stagingXiang, Haihao1-0/+1
Conflicts: NEWS configure.ac src/Makefile.am src/gen6_mfc.c src/gen6_mfd.c src/gen6_vme.c src/gen6_vme.h src/gen75_mfc.c src/gen75_mfd.c src/gen75_vme.c src/gen75_vpp_vebox.c src/gen75_vpp_vebox.h src/gen7_mfd.c src/i965_avc_bsd.c src/i965_decoder.h src/i965_decoder_utils.c src/i965_defines.h src/i965_drv_video.c src/i965_drv_video.h src/i965_encoder.c src/i965_encoder.h src/i965_output_dri.c src/i965_post_processing.c src/i965_post_processing.h src/i965_render.c src/i965_structs.h src/intel_driver.c src/object_heap.c src/shaders/post_processing/Common/AYUV_Load_16x8.asm src/shaders/post_processing/Common/AYUV_Load_16x8.inc src/shaders/post_processing/Common/Init_All_Regs.asm src/shaders/post_processing/Makefile.am src/shaders/post_processing/gen5_6/Common/AYUV_Load_16x8.asm src/shaders/post_processing/gen5_6/Common/AYUV_Load_16x8.inc src/shaders/post_processing/gen5_6/Common/Init_All_Regs.asm src/shaders/post_processing/gen5_6/Common/NV12_Load_8x4.asm src/shaders/post_processing/gen5_6/Common/RGBX_Load_16x8.asm src/shaders/post_processing/gen5_6/Common/RGBX_Load_16x8.inc src/shaders/post_processing/gen5_6/Makefile.am src/shaders/post_processing/gen5_6/nv12_avs_nv12.g4b.gen5 src/shaders/post_processing/gen5_6/nv12_avs_nv12.g6b src/shaders/post_processing/gen5_6/nv12_dn_nv12.g4b.gen5 src/shaders/post_processing/gen5_6/nv12_dn_nv12.g6b src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5 src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b src/shaders/post_processing/gen5_6/nv12_load_save_nv12.g4b.gen5 src/shaders/post_processing/gen5_6/nv12_load_save_nv12.g6b src/shaders/post_processing/gen5_6/nv12_load_save_pa.g4b.gen5 src/shaders/post_processing/gen5_6/nv12_load_save_pa.g6b src/shaders/post_processing/gen5_6/nv12_load_save_pl3.g4b.gen5 src/shaders/post_processing/gen5_6/nv12_load_save_pl3.g6b src/shaders/post_processing/gen5_6/pa_load_save_nv12.g4b.gen5 src/shaders/post_processing/gen5_6/pa_load_save_nv12.g6b src/shaders/post_processing/gen5_6/pa_load_save_pl3.g4b.gen5 src/shaders/post_processing/gen5_6/pa_load_save_pl3.g6b src/shaders/post_processing/gen5_6/pl3_load_save_nv12.g4b.gen5 src/shaders/post_processing/gen5_6/pl3_load_save_nv12.g6b src/shaders/post_processing/gen5_6/pl3_load_save_pa.g4b.gen5 src/shaders/post_processing/gen5_6/pl3_load_save_pa.g6b src/shaders/post_processing/gen5_6/pl3_load_save_pl3.g4b.gen5 src/shaders/post_processing/gen5_6/pl3_load_save_pl3.g6b src/shaders/post_processing/gen7/EOT.g4a src/shaders/post_processing/gen7/Makefile.am src/shaders/post_processing/gen7/PA_AVS_Buf_0.g4a src/shaders/post_processing/gen7/PA_AVS_Buf_1.g4a src/shaders/post_processing/gen7/PA_AVS_Buf_2.g4a src/shaders/post_processing/gen7/PA_AVS_Buf_3.g4a src/shaders/post_processing/gen7/PL2_AVS_Buf_0.g4a src/shaders/post_processing/gen7/PL2_AVS_Buf_1.g4a src/shaders/post_processing/gen7/PL2_AVS_Buf_2.g4a src/shaders/post_processing/gen7/PL2_AVS_Buf_3.g4a src/shaders/post_processing/gen7/PL3_AVS_Buf_0.g4a src/shaders/post_processing/gen7/PL3_AVS_Buf_1.g4a src/shaders/post_processing/gen7/PL3_AVS_Buf_2.g4a src/shaders/post_processing/gen7/PL3_AVS_Buf_3.g4a src/shaders/post_processing/gen7/Save_AVS_NV12.g4a src/shaders/post_processing/gen7/Save_AVS_PA.g4a src/shaders/post_processing/gen7/Save_AVS_PL3.g4a src/shaders/post_processing/gen7/Save_AVS_RGB.g4a src/shaders/post_processing/gen7/Set_AVS_Buf_0123_BGRA.g4a src/shaders/post_processing/gen7/Set_AVS_Buf_0123_PL2.g4a src/shaders/post_processing/gen7/Set_AVS_Buf_0123_PL3.g4a src/shaders/post_processing/gen7/Set_AVS_Buf_0123_VUYA.g4a src/shaders/post_processing/gen7/Set_AVS_Buf_0123_VYUA.g4a src/shaders/post_processing/gen7/Set_Layer_0.g4a src/shaders/post_processing/gen7/VP_Setup.g4a src/shaders/vme/Makefile.am src/shaders/vme/inter_frame_haswell.asm src/shaders/vme/inter_frame_haswell.g75b src/shaders/vme/intra_frame_haswell.asm src/shaders/vme/intra_frame_haswell.g75b src/shaders/vme/vme75.inc src/shaders/vme/vme7_mpeg2.inc
2013-03-15Check the object instance instead of the id for subpicture and imageXiang, Haihao1-20/+18
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2013-03-15VPP: check the backing store bufferXiang, Haihao1-2/+6
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2013-03-15Render: directly use the backing store bufferXiang, Haihao1-70/+61
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2013-03-15Fix the initilization path and the termination path in reverseXiang, Haihao1-5/+3
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2013-01-08render: fix rotation vertices for Ironlake.Gwenole Beauchesne1-14/+14
Ironlake requires the vertex buffer to be ordered in a particular way. More specifically, the correct order is bottom-right, bottom-left and top-left vertices in "output" view, i.e. transformed. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com> (cherry picked from commit dc4d4005d0f3de59b7218506cf5b20bcef61323f)
2012-12-28Render: Update the maximum number of WM threadsXiang, Haihao1-6/+23
The number is stolen from Mesa. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=57323 Signe-off-by: Xiang, Haihao <haihao.xiang@intel.com> Tested-by: zaverel <zaverel@free.fr> (cherry picked from commit a140c632046e50a41bf75da097834fd9954b9561)
2012-12-28Render: Update the maximum number of WM threadsXiang, Haihao1-6/+23
The number is stolen from Mesa. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=57323 Signe-off-by: Xiang, Haihao <haihao.xiang@intel.com> Tested-by: zaverel <zaverel@free.fr>
2012-12-14Render: Add four subpicture supportLi,Xiaowei1-7/+13
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com> (cherry picked from commit a7c42530c312bdb1c53cce49b6a86f47de2ccb65) Conflicts: src/i965_drv_video.c
2012-12-14Render: Add global alpha support for subpictureLi,Xiaowei1-0/+29
Signed-off-by: Li Xiaowei A <xiaowei.a.li@intel.com> (cherry picked from commit 06998b16f470ba49c2af0372e2ef7fee74b1d5b6)
2012-12-14Render: Add four subpicture supportLi,Xiaowei1-7/+13
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
2012-12-14Render: Add global alpha support for subpictureLi,Xiaowei1-0/+29
Signed-off-by: Li Xiaowei A <xiaowei.a.li@intel.com>
2012-11-01Warning fixesXiang, Haihao1-5/+0
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2012-10-31VPP: haswell: fix video post-processing setup.Gwenole Beauchesne1-1/+1
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2012-10-23haswell: fix render kernels.Gwenole Beauchesne1-1/+36
Regenerate render kernels for Haswell because JMPI instruction semantics changed there. In particular, the offset is now expressed in bytes instead of 64-bit units. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2012-10-23haswell: set "Shader Channel Select" fields in surface state.Gwenole Beauchesne1-0/+14
For normal behaviour, each Shader Channel Select should be set to the value indicating that same channel. i.e. Shader Channel Select Red is set to SCS_RED, Shader Channel Select Green is set to SCS_GREEN, etc. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2012-10-23haswell: fix 3DSTATE_PS to fill in number of samples.Gwenole Beauchesne1-1/+3
The sample mask value must match what is set for 3DSTATE_SAMPLE_MASK, through gen7_emit_invarient_states(). Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2012-10-23haswell: fix max PS threads shift value.Gwenole Beauchesne1-1/+6
The maximum number of threads is now a 9-bit value. Thus, one more bit towards LSB was re-used. i.e. bit position is now 23 instead of 24 on Ivy Bridge. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2012-10-23haswell: use at least 64 URB entries for GT2+.Gwenole Beauchesne1-1/+5
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2012-10-23haswell: fix video post-processing setup.Gwenole Beauchesne1-1/+1
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2012-10-23haswell: fix render kernels.Gwenole Beauchesne1-1/+36
Regenerate render kernels for Haswell because JMPI instruction semantics changed there. In particular, the offset is now expressed in bytes instead of 64-bit units. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2012-10-23haswell: set "Shader Channel Select" fields in surface state.Gwenole Beauchesne1-0/+14
For normal behaviour, each Shader Channel Select should be set to the value indicating that same channel. i.e. Shader Channel Select Red is set to SCS_RED, Shader Channel Select Green is set to SCS_GREEN, etc. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2012-10-23haswell: fix 3DSTATE_PS to fill in number of samples.Gwenole Beauchesne1-1/+3
The sample mask value must match what is set for 3DSTATE_SAMPLE_MASK, through gen7_emit_invarient_states(). Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2012-10-23haswell: fix max PS threads shift value.Gwenole Beauchesne1-1/+6
The maximum number of threads is now a 9-bit value. Thus, one more bit towards LSB was re-used. i.e. bit position is now 23 instead of 24 on Ivy Bridge. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2012-10-23haswell: use at least 64 URB entries for GT2+.Gwenole Beauchesne1-1/+5
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2012-10-08Fix build with VA-API 0.32.0.Gwenole Beauchesne1-2/+0
Add new <va/va_backend_compat.h> glue file with various utility functions and definitions to help building the driver against a previous version of libva (1.0.x for VA-API 0.32.x in particular). Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2012-10-04render: fix rotation vertices for Ironlake.Gwenole Beauchesne1-14/+14
Ironlake requires the vertex buffer to be ordered in a particular way. More specifically, the correct order is bottom-right, bottom-left and top-left vertices in "output" view, i.e. transformed. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2012-09-26Add raw DRM support.Dmitry Ermilov1-1/+1
Signed-off-by: Dmitry Ermilov <dmitry.ermilov@intel.com> Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2012-09-20render: add support for display rotation attribute.Gwenole Beauchesne1-63/+63
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com> (cherry picked from commit 8098e75a2a7d1dab08819e851a0eeb884f8e7f69)
2012-09-20render: add support for display rotation attribute.Gwenole Beauchesne1-63/+63
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2012-08-06Add raw DRM support.Dmitry Ermilov1-1/+1
Signed-off-by: Dmitry Ermilov <dmitry.ermilov@intel.com> Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2012-04-04render: fix rendering of interlaced surfaces.Gwenole Beauchesne1-39/+84
Handle bob-deinterlacing flags passed to vaPutSurface(). i.e. VA_TOP_FIELD|VA_BOTTOM_FIELD. Avoid advanced deinterlacing kernels as they allocate extra temporary surfaces, which are useless for such simple tasks. i.e. display either field of an interlaced surface. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2012-03-14render: fix rendering of interlaced surfaces.Gwenole Beauchesne1-39/+84
Handle bob-deinterlacing flags passed to vaPutSurface(). i.e. VA_TOP_FIELD|VA_BOTTOM_FIELD. Avoid advanced deinterlacing kernels as they allocate extra temporary surfaces, which are useless for such simple tasks. i.e. display either field of an interlaced surface. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2012-02-07Render YUV400 image on IvybridgeXiang, Haihao1-4/+10
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2012-02-07Fix graphics memory allocation for VA surfaceXiang, Haihao1-36/+30
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2012-02-07i965_drv_video: support JPEG decoding on IvybridgeXiang, Haihao1-11/+23
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2012-01-19Render YUV400 image on IvybridgeXiang, Haihao1-4/+10
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2012-01-18Fix graphics memory allocation for VA surfaceXiang, Haihao1-36/+30
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2012-01-12Merge branch 'master' into vaapi-extXiang, Haihao1-1/+0
Conflicts: .gitignore src/i965_drv_video.c src/shaders/post_processing/Makefile.am Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2012-01-10Avoid depending on va_backend.h for some filesXiang, Haihao1-1/+0
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2011-12-21i965_drv_video: check the internal format of a surface before renderingXiang, Haihao1-10/+7
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2011-09-19silence compiler warningXiang, Haihao1-5/+0
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2011-09-08i965_drv_video: support JPEG decoding on IvybridgeXiang, Haihao1-11/+23
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2011-08-25i965_drv_video: check the internal format of a surface before renderingXiang, Haihao1-10/+7
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2011-08-25New project build rules and files.Gwenole Beauchesne1-1/+1
2011-08-22Moved files around.Gwenole Beauchesne1-0/+3037