Age | Commit message (Collapse) | Author | Files | Lines |
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This patch adds PCI IDs for Bay Trail (sometimes called Valley View).
As far as the video driver is concerned, it's very similar to
Ivybridge GT1 except VP8 decoding support.
(cherry picked from commit b3afeef8092dc4eb7cb73fce672ddf7a55205f34)
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit c31f6130793c68a83d1cb1116da60489d5e4a1d4)
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit 3c9e778718cb4d24695a880afb45e32cdf43a434)
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Conflicts:
NEWS
configure.ac
src/Makefile.am
src/gen6_mfc.c
src/gen6_mfd.c
src/gen6_vme.c
src/gen6_vme.h
src/gen75_mfc.c
src/gen75_mfd.c
src/gen75_vme.c
src/gen75_vpp_vebox.c
src/gen75_vpp_vebox.h
src/gen7_mfd.c
src/i965_avc_bsd.c
src/i965_decoder.h
src/i965_decoder_utils.c
src/i965_defines.h
src/i965_drv_video.c
src/i965_drv_video.h
src/i965_encoder.c
src/i965_encoder.h
src/i965_output_dri.c
src/i965_post_processing.c
src/i965_post_processing.h
src/i965_render.c
src/i965_structs.h
src/intel_driver.c
src/object_heap.c
src/shaders/post_processing/Common/AYUV_Load_16x8.asm
src/shaders/post_processing/Common/AYUV_Load_16x8.inc
src/shaders/post_processing/Common/Init_All_Regs.asm
src/shaders/post_processing/Makefile.am
src/shaders/post_processing/gen5_6/Common/AYUV_Load_16x8.asm
src/shaders/post_processing/gen5_6/Common/AYUV_Load_16x8.inc
src/shaders/post_processing/gen5_6/Common/Init_All_Regs.asm
src/shaders/post_processing/gen5_6/Common/NV12_Load_8x4.asm
src/shaders/post_processing/gen5_6/Common/RGBX_Load_16x8.asm
src/shaders/post_processing/gen5_6/Common/RGBX_Load_16x8.inc
src/shaders/post_processing/gen5_6/Makefile.am
src/shaders/post_processing/gen5_6/nv12_avs_nv12.g4b.gen5
src/shaders/post_processing/gen5_6/nv12_avs_nv12.g6b
src/shaders/post_processing/gen5_6/nv12_dn_nv12.g4b.gen5
src/shaders/post_processing/gen5_6/nv12_dn_nv12.g6b
src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5
src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b
src/shaders/post_processing/gen5_6/nv12_load_save_nv12.g4b.gen5
src/shaders/post_processing/gen5_6/nv12_load_save_nv12.g6b
src/shaders/post_processing/gen5_6/nv12_load_save_pa.g4b.gen5
src/shaders/post_processing/gen5_6/nv12_load_save_pa.g6b
src/shaders/post_processing/gen5_6/nv12_load_save_pl3.g4b.gen5
src/shaders/post_processing/gen5_6/nv12_load_save_pl3.g6b
src/shaders/post_processing/gen5_6/pa_load_save_nv12.g4b.gen5
src/shaders/post_processing/gen5_6/pa_load_save_nv12.g6b
src/shaders/post_processing/gen5_6/pa_load_save_pl3.g4b.gen5
src/shaders/post_processing/gen5_6/pa_load_save_pl3.g6b
src/shaders/post_processing/gen5_6/pl3_load_save_nv12.g4b.gen5
src/shaders/post_processing/gen5_6/pl3_load_save_nv12.g6b
src/shaders/post_processing/gen5_6/pl3_load_save_pa.g4b.gen5
src/shaders/post_processing/gen5_6/pl3_load_save_pa.g6b
src/shaders/post_processing/gen5_6/pl3_load_save_pl3.g4b.gen5
src/shaders/post_processing/gen5_6/pl3_load_save_pl3.g6b
src/shaders/post_processing/gen7/EOT.g4a
src/shaders/post_processing/gen7/Makefile.am
src/shaders/post_processing/gen7/PA_AVS_Buf_0.g4a
src/shaders/post_processing/gen7/PA_AVS_Buf_1.g4a
src/shaders/post_processing/gen7/PA_AVS_Buf_2.g4a
src/shaders/post_processing/gen7/PA_AVS_Buf_3.g4a
src/shaders/post_processing/gen7/PL2_AVS_Buf_0.g4a
src/shaders/post_processing/gen7/PL2_AVS_Buf_1.g4a
src/shaders/post_processing/gen7/PL2_AVS_Buf_2.g4a
src/shaders/post_processing/gen7/PL2_AVS_Buf_3.g4a
src/shaders/post_processing/gen7/PL3_AVS_Buf_0.g4a
src/shaders/post_processing/gen7/PL3_AVS_Buf_1.g4a
src/shaders/post_processing/gen7/PL3_AVS_Buf_2.g4a
src/shaders/post_processing/gen7/PL3_AVS_Buf_3.g4a
src/shaders/post_processing/gen7/Save_AVS_NV12.g4a
src/shaders/post_processing/gen7/Save_AVS_PA.g4a
src/shaders/post_processing/gen7/Save_AVS_PL3.g4a
src/shaders/post_processing/gen7/Save_AVS_RGB.g4a
src/shaders/post_processing/gen7/Set_AVS_Buf_0123_BGRA.g4a
src/shaders/post_processing/gen7/Set_AVS_Buf_0123_PL2.g4a
src/shaders/post_processing/gen7/Set_AVS_Buf_0123_PL3.g4a
src/shaders/post_processing/gen7/Set_AVS_Buf_0123_VUYA.g4a
src/shaders/post_processing/gen7/Set_AVS_Buf_0123_VYUA.g4a
src/shaders/post_processing/gen7/Set_Layer_0.g4a
src/shaders/post_processing/gen7/VP_Setup.g4a
src/shaders/vme/Makefile.am
src/shaders/vme/inter_frame_haswell.asm
src/shaders/vme/inter_frame_haswell.g75b
src/shaders/vme/intra_frame_haswell.asm
src/shaders/vme/intra_frame_haswell.g75b
src/shaders/vme/vme75.inc
src/shaders/vme/vme7_mpeg2.inc
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Ironlake requires the vertex buffer to be ordered in a particular way.
More specifically, the correct order is bottom-right, bottom-left and
top-left vertices in "output" view, i.e. transformed.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
(cherry picked from commit dc4d4005d0f3de59b7218506cf5b20bcef61323f)
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The number is stolen from Mesa.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=57323
Signe-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Tested-by: zaverel <zaverel@free.fr>
(cherry picked from commit a140c632046e50a41bf75da097834fd9954b9561)
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The number is stolen from Mesa.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=57323
Signe-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Tested-by: zaverel <zaverel@free.fr>
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Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
(cherry picked from commit a7c42530c312bdb1c53cce49b6a86f47de2ccb65)
Conflicts:
src/i965_drv_video.c
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Signed-off-by: Li Xiaowei A <xiaowei.a.li@intel.com>
(cherry picked from commit 06998b16f470ba49c2af0372e2ef7fee74b1d5b6)
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Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
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Signed-off-by: Li Xiaowei A <xiaowei.a.li@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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Regenerate render kernels for Haswell because JMPI instruction semantics
changed there. In particular, the offset is now expressed in bytes instead
of 64-bit units.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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For normal behaviour, each Shader Channel Select should be set to the
value indicating that same channel. i.e. Shader Channel Select Red is
set to SCS_RED, Shader Channel Select Green is set to SCS_GREEN, etc.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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The sample mask value must match what is set for 3DSTATE_SAMPLE_MASK,
through gen7_emit_invarient_states().
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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The maximum number of threads is now a 9-bit value. Thus, one more bit
towards LSB was re-used. i.e. bit position is now 23 instead of 24 on
Ivy Bridge.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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Regenerate render kernels for Haswell because JMPI instruction semantics
changed there. In particular, the offset is now expressed in bytes instead
of 64-bit units.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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For normal behaviour, each Shader Channel Select should be set to the
value indicating that same channel. i.e. Shader Channel Select Red is
set to SCS_RED, Shader Channel Select Green is set to SCS_GREEN, etc.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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The sample mask value must match what is set for 3DSTATE_SAMPLE_MASK,
through gen7_emit_invarient_states().
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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The maximum number of threads is now a 9-bit value. Thus, one more bit
towards LSB was re-used. i.e. bit position is now 23 instead of 24 on
Ivy Bridge.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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Add new <va/va_backend_compat.h> glue file with various utility functions
and definitions to help building the driver against a previous version of
libva (1.0.x for VA-API 0.32.x in particular).
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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Ironlake requires the vertex buffer to be ordered in a particular way.
More specifically, the correct order is bottom-right, bottom-left and
top-left vertices in "output" view, i.e. transformed.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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Signed-off-by: Dmitry Ermilov <dmitry.ermilov@intel.com>
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
(cherry picked from commit 8098e75a2a7d1dab08819e851a0eeb884f8e7f69)
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Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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Signed-off-by: Dmitry Ermilov <dmitry.ermilov@intel.com>
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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Handle bob-deinterlacing flags passed to vaPutSurface().
i.e. VA_TOP_FIELD|VA_BOTTOM_FIELD.
Avoid advanced deinterlacing kernels as they allocate extra temporary
surfaces, which are useless for such simple tasks. i.e. display either
field of an interlaced surface.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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Handle bob-deinterlacing flags passed to vaPutSurface().
i.e. VA_TOP_FIELD|VA_BOTTOM_FIELD.
Avoid advanced deinterlacing kernels as they allocate extra temporary
surfaces, which are useless for such simple tasks. i.e. display either
field of an interlaced surface.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Conflicts:
.gitignore
src/i965_drv_video.c
src/shaders/post_processing/Makefile.am
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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