path: root/lib/Target/R600/R600MachineScheduler.cpp

//===-- R600MachineScheduler.cpp - R600 Scheduler Interface -*- C++ -*-----===//
//
//                     The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
/// \file
/// \brief R600 Machine Scheduler interface
// TODO: Scheduling is optimised for VLIW4 arch, modify it to support TRANS slot
//
//===----------------------------------------------------------------------===//

#define DEBUG_TYPE "misched"

#define TOP_DOWN 0

#include "R600MachineScheduler.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/Pass.h"
#include "llvm/PassManager.h"
#include "llvm/Support/raw_ostream.h"
#include <set>

using namespace llvm;

cl::opt<bool> TopDown("r600-topdown", cl::Hidden,
    cl::desc("Switch top-down scheduling"), cl::init(false));
static
unsigned getShortIndex(unsigned Reg, unsigned SubReg) {
  unsigned ShortReg = TargetRegisterInfo::virtReg2Index(Reg);
  return (ShortReg << 4) | SubReg;
}

static
const unsigned SubRegName[5] = {
  AMDGPU::NoRegister,
  AMDGPU::sub0,
  AMDGPU::sub1,
  AMDGPU::sub2,
  AMDGPU::sub3
};

class DependencyFix : public ScheduleDAGMutation {
private:

  struct SubVReg2SUnit {
    unsigned VirtReg;
    unsigned SubReg;
    SUnit *SU;

    SubVReg2SUnit(unsigned reg, unsigned sr, SUnit *su):
        VirtReg(reg), SubReg(sr), SU(su) {}

    unsigned getSparseSetIndex() const {
      return getShortIndex(VirtReg, SubReg);
    }
  };

  typedef SparseSet<SubVReg2SUnit> SubVReg2SUnitMap;

  SubVReg2SUnitMap VRegDefs;

  void addOutputDep(unsigned Reg, unsigned SubReg, unsigned ShortIndex,
      SUnit *SU) {
    SubVReg2SUnitMap::iterator DefI = VRegDefs.find(ShortIndex);
    if (DefI == VRegDefs.end())
      VRegDefs.insert(SubVReg2SUnit(Reg, SubReg, SU));
    else {
      SUnit *DefSU = DefI->SU;
      if (DefSU != SU) {
        SDep Dep(SU, SDep::Output, Reg);
        DefSU->addPred(Dep);
      }
      DefI->SU = SU;
    }
  }

  void addVRegDefDeps(MachineRegisterInfo &MRI, SUnit *SU, unsigned OperIdx) {
    const MachineInstr *MI = SU->getInstr();
    unsigned Reg = MI->getOperand(OperIdx).getReg();
    unsigned SubReg = MI->getOperand(OperIdx).getSubReg();

    // Singly defined vregs do not have output/anti dependencies.
    // The current operand is a def, so we have at least one.
    // Check here if there are any others...
    if (MRI.hasOneDef(Reg))
      return;

    addOutputDep(Reg, SubReg, getShortIndex(Reg, SubReg), SU);
    if (SubReg == AMDGPU::NoRegister) {
      for (unsigned i = 1; i < 5; i++) {
        addOutputDep(Reg, SubReg, getShortIndex(Reg, SubRegName[i]), SU);
      }
    }
  }

  void addAntiDep(unsigned Reg, unsigned SubReg, SUnit *SU) {
    SubVReg2SUnitMap::iterator DefI =
        VRegDefs.find(getShortIndex(Reg, SubReg));
    if (DefI != VRegDefs.end() && DefI->SU != SU)
      DefI->SU->addPred(SDep(SU, SDep::Anti, Reg));
  }
  
  void addVRegUseDeps(ScheduleDAGMI *dag, MachineInstr *RegionBegin, SUnit *SU,
      unsigned OperIdx) {
    MachineInstr *MI = SU->getInstr();
    unsigned Reg = MI->getOperand(OperIdx).getReg();
    unsigned SubReg = MI->getOperand(OperIdx).getSubReg();

    // Add antidependence to the following def of the vreg it uses.
    addAntiDep(Reg, SubReg, SU);
    if (SubReg == AMDGPU::NoRegister) {
      for (unsigned i = 0; i < 5; i++) {
        addAntiDep(Reg, SubRegName[i], SU);
      }
    }

    // Lookup this operand's reaching definition.
    // TODO: Use LiveInterval to avoid parsing whole MBB
    for (MachineBasicBlock::iterator MII = SU->getInstr(), E = RegionBegin;
        MII != E; --MII) {
      MachineInstr *MI = llvm::prior(MII);
      for (unsigned j = 0, n = MI->getNumOperands(); j != n; ++j) {
        const MachineOperand &MO = MI->getOperand(j);
        if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
          continue;
        if (SubReg == AMDGPU::NoRegister) {
          SUnit *DefSU = dag->getSUnit(MI);
          if (DefSU != SU) {
            SDep dep(DefSU, SDep::Data, Reg);
            SU->addPred(dep);
          }
          continue;
        } else if (MO.getSubReg() == AMDGPU::NoRegister ||
            SubReg == MO.getSubReg()) {
          SUnit *DefSU = dag->getSUnit(MI);
          if (DefSU != SU) {
            SDep dep(DefSU, SDep::Data, Reg);
            SU->addPred(dep);
          }
          return;
        }
      }
    }
  }

public:
  DependencyFix() { }

  /// \brief Recompute Output and Anti dependencies of incoming dag
  /// ScheduleDAGInstrs has a conservative policy about subreg dependencies.
  /// All subreg write of a same superreg will be chained by Output/Anti deps.
  /// These artificial deps delay releases of MI and thus reduce parallelism
  /// oportunities. This function recompute the ScheduleDag to produce proper
  /// subreg aware dependencies.
  void apply(ScheduleDAGMI *dag) {
    VRegDefs.clear();
    // Remove all Output/Anti deps
    for (unsigned i = 0; i < dag->SUnits.size(); ++i) {
      SUnit &SU = dag->SUnits[i];
      for (SUnit::pred_iterator SUIt = SU.Preds.begin(), SUE = SU.Preds.end();
          SUIt != SUE; ++SUIt) {
        SDep &SD = *SUIt;
        if (SD.getKind() != SDep::Order &&
            TargetRegisterInfo::isVirtualRegister(SD.getReg())) {
          SU.removePred(SD);
        }
      }
    }

    MachineBasicBlock *MBB = dag->SUnits.front().getInstr()->getParent();
    MachineBasicBlock::iterator RegionBegin = MBB->begin(),
        RegionEnd = MBB->end();

    while (!dag->getSUnit(RegionBegin))
      RegionBegin++;

    while (!dag->getSUnit(RegionEnd))
      RegionEnd--;

    VRegDefs.setUniverse((dag->MRI.getNumVirtRegs() << 4) | 15);
    // Now recompute output/anti dependencies
    for (MachineBasicBlock::iterator MII = RegionEnd, MIE = RegionBegin;
         MII != MIE; --MII) {
      MachineInstr *MI = MII;
      SUnit *SU = dag->getSUnit(MI);
      for (unsigned j = 0, n = MI->getNumOperands(); j != n; ++j) {
        const MachineOperand &MO = MI->getOperand(j);
        if (!MO.isReg()) continue;
        unsigned Reg = MO.getReg();
        if (Reg == 0) continue;

        if (TargetRegisterInfo::isVirtualRegister(Reg)) {
          if (MO.isDef()) {
            addVRegDefDeps(dag->MRI, SU, j);
          }
          else if (MO.readsReg()) {// ignore undef operands
            addVRegUseDeps(dag, RegionBegin, SU, j);
          }
        }
      }
    }
    DEBUG(
    for (unsigned i = 0, e = dag->SUnits.size(); i < e; ++i) {
      SUnit &SU = dag->SUnits[i];
      dbgs() << "\n Dependencies for SUnit ";
      SU.dump(dag);
      dbgs() << "Preds:\n";
      for (unsigned j = 0, e2 = SU.Preds.size(); j < e2; j++) {
        SUnit *Pred = SU.Preds[j].getSUnit();
        dbgs() << " - (" << SU.Preds[j].getKind() << ")";
        Pred->dump(dag);
      }
      dbgs() << "Succs:\n";
      for (unsigned j = 0, e2 = SU.Succs.size(); j < e2; j++) {
        SUnit *Succ = SU.Succs[j].getSUnit();
        if (Succ == &dag->ExitSU)
          continue;
        dbgs() << " - (" << SU.Succs[j].getKind() << ")";
        Succ->dump(dag);
      }
    }
    );
  }
};

ScheduleDAGInstrs *llvm::createR600MachineScheduler(MachineSchedContext *C) {
  ScheduleDAGMI *dag = new ScheduleDAGMI(C, new R600SchedStrategy());
  dag->addMutation(new DependencyFix);
  return dag;
}

void R600SchedStrategy::initialize(ScheduleDAGMI *dag) {

  DAG = dag;
  TII = static_cast<const R600InstrInfo*>(DAG->TII);
  TRI = static_cast<const R600RegisterInfo*>(DAG->TRI);
  MRI = &DAG->MRI;
  CurInstKind = IDOther;
  CurEmitted = 0;
  OccupedSlotsMask = 15;
  InstKindLimit[IDAlu] = TII->getMaxAlusPerClause();
  InstKindLimit[IDOther] = 32;

  const AMDGPUSubtarget &ST = DAG->TM.getSubtarget<AMDGPUSubtarget>();
  InstKindLimit[IDFetch] = ST.getTexVTXClauseSize();
}

void R600SchedStrategy::MoveUnits(std::vector<SUnit *> &QSrc, std::vector<SUnit *> &QDst)
{
  if (QSrc.empty())
    return;
  for (unsigned i = 0, e = QSrc.size(); i < e; ++i) {
    QDst.push_back(QSrc[i]);
  }
  QSrc.clear();
}

SUnit* R600SchedStrategy::pickNode(bool &IsTopNode) {
  SUnit *SU = 0;
  NextInstKind = IDOther;

  if (!FakeCopy.empty()) {
    IsTopNode = true;
    SU = *FakeCopy.begin();
    FakeCopy.erase(FakeCopy.begin());
    return SU;
  }

  IsTopNode = TOP_DOWN;

  // check if we might want to switch current clause type
  bool AllowSwitchToAlu = (CurEmitted > InstKindLimit[CurInstKind]) ||
      (Available[CurInstKind].empty());
  bool AllowSwitchFromAlu = (CurEmitted > InstKindLimit[CurInstKind]) &&
      (!Available[IDFetch].empty() || !Available[IDOther].empty());

  if ((AllowSwitchToAlu && CurInstKind != IDAlu) ||
      (!AllowSwitchFromAlu && CurInstKind == IDAlu)) {
    // try to pick ALU
    SU = pickAlu();
    if (SU) {
      if (CurEmitted >= InstKindLimit[IDAlu])
        CurEmitted = 0;
      NextInstKind = IDAlu;
    }
  }

  if (!SU) {
    // try to pick FETCH
    SU = pickOther(IDFetch);
    if (SU)
      NextInstKind = IDFetch;
  }

  // try to pick other
  if (!SU) {
    SU = pickOther(IDOther);
    if (SU)
      NextInstKind = IDOther;
  }

  DEBUG(
      if (SU) {
        dbgs() << " ** Pick node **\n";
        SU->dump(DAG);
      } else {
        dbgs() << "NO NODE \n";
        for (unsigned i = 0; i < DAG->SUnits.size(); i++) {
          const SUnit &S = DAG->SUnits[i];
          if (!S.isScheduled)
            S.dump(DAG);
        }
      }
  );

  return SU;
}

void R600SchedStrategy::schedNode(SUnit *SU, bool IsTopNode) {

  if (NextInstKind != CurInstKind) {
    DEBUG(dbgs() << "Instruction Type Switch\n");
    if (NextInstKind != IDAlu)
      OccupedSlotsMask = 15;
    CurEmitted = 0;
    CurInstKind = NextInstKind;
  }

  if (CurInstKind == IDAlu) {
    switch (getAluKind(SU)) {
    case AluT_XYZW:
      CurEmitted += 4;
      break;
    case AluDiscarded:
      break;
    default: {
      ++CurEmitted;
      for (MachineInstr::mop_iterator It = SU->getInstr()->operands_begin(),
          E = SU->getInstr()->operands_end(); It != E; ++It) {
        MachineOperand &MO = *It;
        if (MO.isReg() && MO.getReg() == AMDGPU::ALU_LITERAL_X)
          ++CurEmitted;
      }
    }
    }
  } else {
    ++CurEmitted;
  }


  DEBUG(dbgs() << CurEmitted << " Instructions Emitted in this clause\n");

  if (CurInstKind != IDFetch) {
    MoveUnits(Pending[IDFetch], Available[IDFetch]);
  }
  MoveUnits(Pending[IDOther], Available[IDOther]);
}

static bool
isFakeCopy(MachineInstr *MI) {
  if (MI->getOpcode() != AMDGPU::COPY)
    return false;
  if (!TargetRegisterInfo::isPhysicalRegister(MI->getOperand(1).getReg()))
    return false;
  if (MI->getOperand(1).getReg() == AMDGPU::ZERO)
    return false;
  return true;
}

void R600SchedStrategy::releaseTopNode(SUnit *SU) {
  DEBUG(dbgs() << "Top Releasing ";SU->dump(DAG););
  if (isFakeCopy(SU->getInstr())) {
    FakeCopy.push_back(SU);
    return;
  }

  if (TOP_DOWN) {
    int IK = getInstKind(SU);

    Pending[IK].push_back(SU);
  }
}

void R600SchedStrategy::releaseBottomNode(SUnit *SU) {
  DEBUG(dbgs() << "Bottom Releasing ";SU->dump(DAG););
  if (isFakeCopy(SU->getInstr())) {
    return;
  }
  if (!TOP_DOWN) {
    int IK = getInstKind(SU);

    if (IK == IDOther)
      Available[IDOther].push_back(SU);
    else
      Pending[IK].push_back(SU);
  }
}

bool R600SchedStrategy::regBelongsToClass(unsigned Reg,
                                          const TargetRegisterClass *RC) const {
  if (!TargetRegisterInfo::isVirtualRegister(Reg)) {
    return RC->contains(Reg);
  } else {
    return MRI->getRegClass(Reg) == RC;
  }
}

R600SchedStrategy::AluKind R600SchedStrategy::getAluKind(SUnit *SU) const {
  MachineInstr *MI = SU->getInstr();

    switch (MI->getOpcode()) {
    case AMDGPU::INTERP_PAIR_XY:
    case AMDGPU::PRED_X:
    case AMDGPU::INTERP_PAIR_ZW:
    case AMDGPU::INTERP_VEC_LOAD:
      return AluT_XYZW;
    case AMDGPU::COPY:
      if (MI->getOperand(1).isUndef()) {
        // MI will become a KILL, don't considers it in scheduling
        return AluDiscarded;
      }
    default:
      break;
    }

    // Does the instruction take a whole IG ?
    if(TII->isVector(*MI) || TII->isTransOnly(MI) ||
        TII->isCubeOp(MI->getOpcode()) ||
        TII->isReductionOp(MI->getOpcode()))
      return AluT_XYZW;

    // Is the result already assigned to a channel ?
    unsigned DestSubReg = MI->getOperand(0).getSubReg();
    switch (DestSubReg) {
    case AMDGPU::sub0:
      return AluT_X;
    case AMDGPU::sub1:
      return AluT_Y;
    case AMDGPU::sub2:
      return AluT_Z;
    case AMDGPU::sub3:
      return AluT_W;
    default:
      break;
    }

    // Is the result already member of a X/Y/Z/W class ?
    unsigned DestReg = MI->getOperand(0).getReg();
    if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_XRegClass) ||
        regBelongsToClass(DestReg, &AMDGPU::R600_AddrRegClass))
      return AluT_X;
    if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_YRegClass))
      return AluT_Y;
    if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_ZRegClass))
      return AluT_Z;
    if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_WRegClass))
      return AluT_W;
    if (regBelongsToClass(DestReg, &AMDGPU::R600_Reg128RegClass))
      return AluT_XYZW;

    return AluAny;

}

int R600SchedStrategy::getInstKind(SUnit* SU) {
  int Opcode = SU->getInstr()->getOpcode();

  if (TII->usesTextureCache(Opcode) || TII->usesVertexCache(Opcode))
    return IDFetch;

  if (TII->isALUInstr(Opcode)) {
    return IDAlu;
  }

  switch (Opcode) {
  case AMDGPU::COPY:
  case AMDGPU::CONST_COPY:
  case AMDGPU::INTERP_PAIR_XY:
  case AMDGPU::INTERP_PAIR_ZW:
  case AMDGPU::INTERP_VEC_LOAD:
  case AMDGPU::DOT4_eg_pseudo:
  case AMDGPU::DOT4_r600_pseudo:
    return IDAlu;
  default:
    return IDOther;
  }
}

SUnit *R600SchedStrategy::PopInst(std::vector<SUnit *> &Q) {
  if (Q.empty())
    return NULL;
  for (std::vector<SUnit *>::iterator It = Q.begin(), E = Q.end();
      It != E; ++It) {
    SUnit *SU = *It;
    InstructionsGroupCandidate.push_back(SU->getInstr());
    if (TII->canBundle(InstructionsGroupCandidate)) {
      InstructionsGroupCandidate.pop_back();
      Q.erase(It);
      return SU;
    } else {
      InstructionsGroupCandidate.pop_back();
    }
  }
  return NULL;
}

void R600SchedStrategy::LoadAlu() {
  std::vector<SUnit *> &QSrc = Pending[IDAlu];
  for (unsigned i = 0, e = QSrc.size(); i < e; ++i) {
    AluKind AK = getAluKind(QSrc[i]);
    AvailableAlus[AK].push_back(QSrc[i]);
  }
  QSrc.clear();
}

void R600SchedStrategy::PrepareNextSlot() {
  DEBUG(dbgs() << "New Slot\n");
  assert (OccupedSlotsMask && "Slot wasn't filled");
  OccupedSlotsMask = 0;
  InstructionsGroupCandidate.clear();
  LoadAlu();
}

void R600SchedStrategy::AssignSlot(MachineInstr* MI, unsigned Slot) {
  unsigned DestReg = MI->getOperand(0).getReg();
  // PressureRegister crashes if an operand is def and used in the same inst
  // and we try to constraint its regclass
  for (MachineInstr::mop_iterator It = MI->operands_begin(),
      E = MI->operands_end(); It != E; ++It) {
    MachineOperand &MO = *It;
    if (MO.isReg() && !MO.isDef() &&
        MO.getReg() == MI->getOperand(0).getReg())
      return;
  }
  // Constrains the regclass of DestReg to assign it to Slot
  switch (Slot) {
  case 0:
    MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_XRegClass);
    break;
  case 1:
    MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_YRegClass);
    break;
  case 2:
    MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_ZRegClass);
    break;
  case 3:
    MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_WRegClass);
    break;
  }
}

SUnit *R600SchedStrategy::AttemptFillSlot(unsigned Slot) {
  static const AluKind IndexToID[] = {AluT_X, AluT_Y, AluT_Z, AluT_W};
  SUnit *SlotedSU = PopInst(AvailableAlus[IndexToID[Slot]]);
  if (SlotedSU)
    return SlotedSU;
  SUnit *UnslotedSU = PopInst(AvailableAlus[AluAny]);
  if (UnslotedSU)
    AssignSlot(UnslotedSU->getInstr(), Slot);
  return UnslotedSU;
}

bool R600SchedStrategy::isAvailablesAluEmpty() const {
  return Pending[IDAlu].empty() && AvailableAlus[AluAny].empty() &&
      AvailableAlus[AluT_XYZW].empty() && AvailableAlus[AluT_X].empty() &&
      AvailableAlus[AluT_Y].empty() && AvailableAlus[AluT_Z].empty() &&
      AvailableAlus[AluT_W].empty() && AvailableAlus[AluDiscarded].empty();
}

SUnit* R600SchedStrategy::pickAlu() {
  while (!isAvailablesAluEmpty()) {
    if (!OccupedSlotsMask) {
      // Flush physical reg copies (RA will discard them)
      if (!AvailableAlus[AluDiscarded].empty()) {
        OccupedSlotsMask = 15;
        return PopInst(AvailableAlus[AluDiscarded]);
      }
      // If there is a T_XYZW alu available, use it
      if (!AvailableAlus[AluT_XYZW].empty()) {
        OccupedSlotsMask = 15;
        return PopInst(AvailableAlus[AluT_XYZW]);
      }
    }
    for (int Chan = 3; Chan > -1; --Chan) {
      bool isOccupied = OccupedSlotsMask & (1 << Chan);
      if (!isOccupied) {
        SUnit *SU = AttemptFillSlot(Chan);
        if (SU) {
          OccupedSlotsMask |= (1 << Chan);
          InstructionsGroupCandidate.push_back(SU->getInstr());
          return SU;
        }
      }
    }
    PrepareNextSlot();
  }
  return NULL;
}

SUnit* R600SchedStrategy::pickOther(int QID) {
  SUnit *SU = 0;
  std::vector<SUnit *> &AQ = Available[QID];

  if (AQ.empty()) {
    MoveUnits(Pending[QID], AQ);
  }
  if (!AQ.empty()) {
    SU = *AQ.begin();
    AQ.erase(AQ.begin());
  }
  return SU;
}