| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2012-10-11 | Merge master branch | tstellar | 1 | -10/+23 |
| 2012-09-24 | Machine Model (-schedmodel only). Added SchedAliases. | tstellar | 1 | -8/+23 |
| 2012-09-19 | SchedMachineModel: compress the CPU's WriteLatencyTable. | atrick | 1 | -0/+3 |
| 2012-09-18 | comment typo | atrick | 1 | -1/+1 |
| 2012-09-18 | TableGen subtarget emitter. Use getSchedClassIdx. | atrick | 1 | -9/+0 |
| 2012-09-17 | Revert r164061-r164067. Most of the new subtarget emitter. | atrick | 1 | -1/+10 |
| 2012-09-17 | comment typo | atrick | 1 | -1/+1 |
| 2012-09-17 | TableGen subtarget emitter. Use getSchedClassIdx. | atrick | 1 | -9/+0 |
| 2012-09-15 | TableGen subtarget parser. Handle new machine model. | atrick | 1 | -0/+29 |
| 2012-09-15 | TableGen subtarget parser. Handle new machine model. | atrick | 1 | -0/+17 |
| 2012-09-15 | TableGen subtarget parser. Handle new machine model. | atrick | 1 | -56/+228 |
| 2012-07-07 | I'm introducing a new machine model to simultaneously allow simple | Andrew Trick | 1 | -0/+172 |
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index : ~vlj/llvm | |
| AMDGPU backend development for LLVM | UNKNOWN |
| summaryrefslogtreecommitdiff |