R600: Relax some vector constraints on Dot4.codesize6

Dot4 now uses 8 scalar operands instead of 2 vectors one which allows register
coalescer to remove some unneeded COPY.
This patch also defines some structures/functions that can be used to handle
every vector instructions (CUBE, Cayman special instructions...) in a similar
fashion.

1 files changed, 2 insertions, 0 deletions

diff --git a/lib/Target/R600/R600MachineScheduler.cpp b/lib/Target/R600/R600MachineScheduler.cpp
index 5d4c4d7e73..343bb72a93 100644
--- a/lib/Target/R600/R600MachineScheduler.cpp
+++ b/lib/Target/R600/R600MachineScheduler.cpp
@@ -418,6 +418,7 @@ R600SchedStrategy::AluKind R600SchedStrategy::getAluKind(SUnit *SU) const {
     case AMDGPU::PRED_X:
     case AMDGPU::INTERP_PAIR_ZW:
     case AMDGPU::INTERP_VEC_LOAD:
+    case AMDGPU::DOT_4:
       return AluT_XYZW;
     case AMDGPU::COPY:
       if (MI->getOperand(1).isUndef()) {
@@ -485,6 +486,7 @@ int R600SchedStrategy::getInstKind(SUnit* SU) {
   case AMDGPU::INTERP_VEC_LOAD:
   case AMDGPU::DOT4_eg_pseudo:
   case AMDGPU::DOT4_r600_pseudo:
+  case AMDGPU::DOT_4:
     return IDAlu;
   default:
     return IDOther;