diff options
Diffstat (limited to 'lib/Target/AMDGPU/R600Instructions.td')
| -rw-r--r-- | lib/Target/AMDGPU/R600Instructions.td | 47 |
1 files changed, 38 insertions, 9 deletions
diff --git a/lib/Target/AMDGPU/R600Instructions.td b/lib/Target/AMDGPU/R600Instructions.td index e997721598..27c81e0258 100644 --- a/lib/Target/AMDGPU/R600Instructions.td +++ b/lib/Target/AMDGPU/R600Instructions.td @@ -13,9 +13,24 @@ include "R600Intrinsics.td" +class R600GPUInst <dag outs, dag ins, string asm, list<dag> pattern> + : AMDGPUInst <outs, ins, asm, pattern> { + bit isALU = 0; + bit isFETCH = 0; + + let TSFlags{12} = isALU; + let TSFlags{13} = isFETCH; +} + +class R600GPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern> + : R600GPUInst<outs, ins, asm, pattern> { + + field bits<32> Inst = 0xffffffff; +} + class InstR600 <bits<11> inst, dag outs, dag ins, string asm, list<dag> pattern, InstrItinClass itin> - : AMDGPUInst <outs, ins, asm, pattern> { + : R600GPUInst <outs, ins, asm, pattern> { field bits<64> Inst; bit Trig = 0; @@ -48,7 +63,7 @@ class InstR600 <bits<11> inst, dag outs, dag ins, string asm, list<dag> pattern, } class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> : - AMDGPUInst <outs, ins, asm, pattern> { + R600GPUInst <outs, ins, asm, pattern> { field bits<64> Inst; let Namespace = "AMDGPU"; @@ -239,6 +254,7 @@ class R600_1OP <bits<11> inst, string opName, list<dag> pattern, let HasNativeOperands = 1; let Op1 = 1; let DisableEncoding = "$literal"; + let isALU = 1; let Inst{31-0} = Word0; let Inst{63-32} = Word1; @@ -275,6 +291,7 @@ class R600_2OP <bits<11> inst, string opName, list<dag> pattern, let HasNativeOperands = 1; let Op2 = 1; let DisableEncoding = "$literal"; + let isALU = 1; let Inst{31-0} = Word0; let Inst{63-32} = Word1; @@ -313,6 +330,7 @@ class R600_3OP <bits<5> inst, string opName, list<dag> pattern, let HasNativeOperands = 1; let DisableEncoding = "$literal"; let Op3 = 1; + let isALU = 1; let Inst{31-0} = Word0; let Inst{63-32} = Word1; @@ -325,7 +343,9 @@ class R600_REDUCTION <bits<11> inst, dag ins, string asm, list<dag> pattern, ins, asm, pattern, - itin>; + itin>{ + let isALU = 1; +} class R600_TEX <bits<11> inst, string opName, list<dag> pattern, InstrItinClass itin = AnyALU> : @@ -336,6 +356,7 @@ class R600_TEX <bits<11> inst, string opName, list<dag> pattern, pattern, itin>{ let Inst {10-0} = inst; + let isFETCH = 1; } } // End mayLoad = 1, mayStore = 0, hasSideEffects = 0 @@ -422,23 +443,26 @@ def isR600toCayman : Predicate< // Interpolation Instructions //===----------------------------------------------------------------------===// -def INTERP_PAIR_XY : AMDGPUShaderInst < + +let isALU = 1 in { +def INTERP_PAIR_XY : R600GPUShaderInst < (outs R600_TReg32_X:$dst0, R600_TReg32_Y:$dst1), (ins i32imm:$src0, R600_Reg32:$src1, R600_Reg32:$src2), "INTERP_PAIR_XY $src0 $src1 $src2 : $dst0 dst1", []>; -def INTERP_PAIR_ZW : AMDGPUShaderInst < +def INTERP_PAIR_ZW : R600GPUShaderInst < (outs R600_TReg32_Z:$dst0, R600_TReg32_W:$dst1), (ins i32imm:$src0, R600_Reg32:$src1, R600_Reg32:$src2), "INTERP_PAIR_ZW $src0 $src1 $src2 : $dst0 dst1", []>; -def INTERP_VEC_LOAD : AMDGPUShaderInst < +def INTERP_VEC_LOAD : R600GPUShaderInst < (outs R600_Reg128:$dst), (ins i32imm:$src0), "INTERP_LOAD $src0 : $dst", []>; +} // isALU = 1 def INTERP_XY : R600_2OP <0xD6, "INTERP_XY", []> { let bank_swizzle = 5; @@ -633,7 +657,7 @@ def MOV : R600_1OP <0x19, "MOV", []>; let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1 in { -class MOV_IMM <ValueType vt, Operand immType> : AMDGPUInst < +class MOV_IMM <ValueType vt, Operand immType> : R600GPUInst < (outs R600_Reg32:$dst), (ins immType:$imm), "", @@ -880,6 +904,7 @@ multiclass CUBE_Common <bits<11> inst> { VecALU > { let isPseudo = 1; + let isALU = 1; } def _real : R600_2OP <inst, "CUBE", []>; @@ -1475,6 +1500,8 @@ def PRED_X : InstR600 < (ins R600_Reg32:$src0, i32imm:$src1, i32imm:$flags), "", [], NullALU> { let FlagOperandIdx = 3; + let isALU = 1; + let isTerminator = 1; } let isTerminator = 1, isBranch = 1, isBarrier = 1 in { @@ -1505,19 +1532,21 @@ def MASK_WRITE : AMDGPUShaderInst < } // End isPseudo = 1 } // End usesCustomInserter = 1 -def TXD: AMDGPUShaderInst < +let isFETCH = 1 in { +def TXD: R600GPUShaderInst < (outs R600_Reg128:$dst), (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget), "TXD $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget", [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$resourceId, imm:$samplerId, imm:$textureTarget))] >; -def TXD_SHADOW: AMDGPUShaderInst < +def TXD_SHADOW: R600GPUShaderInst < (outs R600_Reg128:$dst), (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget), "TXD_SHADOW $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget", [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$resourceId, imm:$samplerId, TEX_SHADOW:$textureTarget))] >; +} // isFETCH = 1 def CLAMP_R600 : CLAMP <R600_Reg32>; def FABS_R600 : FABS<R600_Reg32>; |