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2013-06-04Revert series of sched model patches until I figure out what is going on.Arnold Schwaighofer1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183273 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04SubtargetEmitter fixArnold Schwaighofer1-1/+1
Don't output data if we are supposed to ignore the record. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183255 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-31Make SubRegIndex size mandatory, following r183020.Ahmed Bougacha3-7/+18
This also makes TableGen able to compute sizes/offsets of synthesized indices representing tuples. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183061 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-31Add a way to define the bit range covered by a SubRegIndex.Ahmed Bougacha3-5/+36
NOTE: If this broke your out-of-tree backend, in *RegisterInfo.td, change the instances of SubRegIndex that have a comps template arg to use the ComposedSubRegIndex class instead. In TableGen land, this adds Size and Offset attributes to SubRegIndex, and the ComposedSubRegIndex class, for which the Size and Offset are computed by TableGen. This also adds an accessor in MCRegisterInfo, and Size/Offsets for the X86 and ARM subreg indices. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183020 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-30Fixed bug when tests in executable partially used absolute paths.Galina Kistanova1-3/+5
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182910 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-28Remove the MCRegAliasIterator tables and compute the aliases dynamically.Chad Rosier3-66/+3
The size reduction in the RegDiffLists are rather dramatic. Here are a few size differences for MCTargetDesc.o files (before and after) in bytes: R600 - 36160B - 11184B - 69% reduction ARM - 28480B - 8368B - 71% reduction Mips - 816B - 576B - 29% reduction One side effect of dynamically computing the aliases is that the iterator does not guarantee that the entries are ordered or that duplicates have been removed. The documentation implies this is a safe assumption and I found no clients that requires these attributes (i.e., strict ordering and uniqueness). My local LNT tester results showed no execution-time failures or significant compile-time regressions (i.e., beyond what I would consider noise) for -O0g, -O2 and -O3 runs on x86_64 and i386 configurations. rdar://12906217 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182783 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-28Revert r182715 and r182758Alexey Samsonov1-7/+5
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182761 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-28Fixup for r182715: provide correct arg to --gtest-filterAlexey Samsonov1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182758 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-26Fixed bug when tests in executable partially used absolute paths.Galina Kistanova1-5/+7
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182715 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22Recognize ValueType operands in source patterns for fast-isel.Bill Schmidt1-3/+7
Currently the fast-isel table generator recognizes registers, register classes, and immediates for source pattern operands. ValueType operands are not recognized. This is not a problem for existing targets with fast-isel support, but will not work for targets like PowerPC and SPARC that use types in source patterns. The proposed patch allows ValueType operands and treats them in the same manner as register classes. There is no convenient way to map from a ValueType to a register class, but there's no need to do so. The table generator already requires that all types in the source pattern be identical, and we know the register class of the output operand already. So we just assign that register class to any ValueType operands we encounter. No functional effect on existing targets. Testing deferred until the PowerPC target implements fast-isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182512 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16Add TargetRegisterInfo::getCoveringLanes().Jakob Stoklund Olesen3-6/+35
This lane mask provides information about which register lanes completely cover super-registers. See the block comment before getCoveringLanes(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182034 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-15Use proper syntax.Bill Wendling1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181930 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-15Add lldb and polly to the projects to tag.Bill Wendling1-2/+3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181925 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14Add 'CHECK-DAG' supportMichael Liao1-23/+147
Refer to 'FileCheck.rst'f for details of 'CHECK-DAG'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181827 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14Refactor string checking. No functionality change.Michael Liao1-62/+94
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181824 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14Get the unittests compiling when building with cmake and the settingDuncan Sands1-0/+4
-DLLVM_ENABLE_THREADS=false. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181788 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-08Add libcxx and clang-tools-extra to the testing thing.Bill Wendling1-3/+10
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181418 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-08Add clang-tools-extra to the list of things to tag for the release.Bill Wendling1-2/+2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181402 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07Add the libc++ project to those we tag.Bill Wendling1-2/+2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181371 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30Try to fix ProgramTest on FreeBSDReid Kleckner1-0/+5
This seemed like the cleanest way to find the test executable. Also fix the file mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180770 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-27Handle tied sub-operands in AsmMatcherEmitterUlrich Weigand1-30/+19
The problem this patch addresses is the handling of register tie constraints in AsmMatcherEmitter, where one operand is tied to a sub-operand of another operand. The typical scenario for this to happen is the tie between the "write-back" register of a pre-inc instruction, and the base register sub-operand of the memory address operand of that instruction. The current AsmMatcherEmitter code attempts to handle tied operands by emitting the operand as usual first, and emitting a CVT_Tied node when handling the second (tied) operand. However, this really only works correctly if the tied operand does not have sub-operands (and isn't a sub-operand itself). Under those circumstances, a wrong MC operand list is generated. In discussions with Jim Grosbach, it turned out that the MC operand list really ought not to contain tied operands in the first place; instead, it ought to consist of exactly those operands that are named in the AsmString. However, getting there requires significant rework of (some) targets. This patch fixes the immediate problem, and at the same time makes one (small) step in the direction of the long-term solution, by implementing two changes: 1. Restricts the AsmMatcherEmitter handling of tied operands to apply solely to simple operands (not complex operands or sub-operand of such). This means that at least we don't get silently corrupt MC operand lists as output. However, if we do have tied sub-operands, they would now no longer be handled at all, except for: 2. If we have an operand that does not occur in the AsmString, and also isn't handled as tied operand, simply emit a dummy MC operand (constant 0). This works as long as target code never attempts to access MC operands that do no not occur in the AsmString (and are not tied simple operands), which happens to be the case for all targets where this situation can occur (ARM and PowerPC). [ Note that this change means that many of the ARM custom converters are now superfluous, since the implement the same "hack" now performed already by common code. ] Longer term, we ought to fix targets to never access *any* MC operand that does not occur in the AsmString (including tied simple operands), and then finally completely remove all such operands from the MC operand list. Patch approved by Jim Grosbach. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180677 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26Use 'git svn find-rev' in git-svnrevert instead of shell script fu.Michael Gottesman1-4/+3
Thanks Chandler! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180592 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26Added the scripts git-svnup/git-svnrevert to utils/git-svn.Michael Gottesman2-0/+68
It makes more sense to have git-svnup here than catting said file in the documentation (where we should rather point users to this directory). I included git-svnrevert as an additional gift to the community. I will update the documentation in a second commit later today. git-svnrevert takes in a git hash for a commit, looks up the svn revision for said commit and then creates the normal git revert commit message with the one liner message, except instead of saying Revert "<<<INSERT ONELINER HERE>>>" This reverts commit <<<INSERT GITHASH HERE>>> It says: Revert "<<<INSERT ONELINER HERE>>>" This reverts commit r<<<INSERT SVN REVISION HERE>>> so git hashes will not escape into our svn logs (which just look unseemly). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180587 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25Remove SMLoc paired with CHECK-NOT patterns. Not functionality change.Michael Liao1-8/+9
Pattern has source location by itself. After adding a trivial method to retrieve it, it's unnecessary to pair a source location for CHECK-NOT patterns. One thing revised after this is the diagnostic info is more accurate by pointing to the start of the CHECK-NOT pattern instead of the end of the CHECK-NOT pattern. E.g. diagnostic message previously looks like <stdin>:1:1: error: CHECK-NOT: string occurred! test ^ test.txt:1:16: note: CHECK-NOT: pattern specified here CHECK-NOT: test ^ is changed to <stdin>:1:1: error: CHECK-NOT: string occurred! test ^ test.txt:1:12: note: CHECK-NOT: pattern specified here CHECK-NOT: test ^ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180578 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25Remove tailing whitespacesMichael Liao1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180564 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-23Machine model: Generate table entries for super-resources.Andrew Trick1-14/+23
Super-resources and resource groups are two ways of expressing overlapping sets of processor resources. Now we generate table entries the same way for both so the scheduler never needs to explicitly check for super-resources. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180162 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-23Machine model: verify well-formed processor resource groups.Andrew Trick2-0/+54
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180161 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-23Machine model: rewrite a tablegen loop to avoid comparing record pointers.Andrew Trick1-8/+4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180160 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18[asm parser] Add support for predicating MnemonicAlias based on the assemblerChad Rosier1-20/+45
variant/dialect. Addresses a FIXME in the emitMnemonicAliases function. Use and test case to come shortly. rdar://13688439 and part of PR13340. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179804 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12lit: Fix infinite recursion when an out-of-tree test root is located inside ↵Daniel Dunbar5-9/+47
the source test root. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179402 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12lit: Add a test for discovery w/ test_exec_root (out-of-tree test root).Daniel Dunbar3-9/+60
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179401 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11Add CLAC/STAC instruction encoding/decoding supportMichael Liao1-17/+19
As these two instructions in AVX extension are privileged instructions for special purpose, it's only expected to be used in inlined assembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179266 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11lit: Don't descend into .git directories during test discovery.Daniel Dunbar1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179249 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11lit: Shorten a metavar to make --help look nicer.Daniel Dunbar1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179248 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11lit: Add a test for discovery when exact test names are given.Daniel Dunbar1-0/+15
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179247 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11lit: Add a trivial test of the basic progress bar.Daniel Dunbar6-0/+22
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179243 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05Move yaml2obj to tools too.Rafael Espindola4-733/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178904 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05Use ScalarBitSetTraits.Rafael Espindola1-83/+84
What was missing was were the type strong operator|. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178879 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05Move obj2yaml to tools to sort out make's dependencies.Rafael Espindola6-509/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178835 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05Build obj2yaml with configure+make.Rafael Espindola1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178833 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04Add back parsing of header charactestics.Rafael Espindola1-1/+37
It had been dropped during the switch to yaml::IO. Also add a test going from yaml2obj to llvm-readobj. It can be extended as we add more fields/formats to yaml2obj. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178786 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03Remove anonymous namespace.Rafael Espindola1-4/+0
Looks like the gcc in http://lab.llvm.org:8011/builders/clang-x86_64-darwin11-self-mingw32/ doesn't like "not external linkage": /Volumes/Macintosh_HD2/buildbots/clang-x86_64-darwin11-self-mingw32/llvm.src/include/llvm/Support/YAMLTraits.h: In instantiation of 'const bool llvm::yaml::has_SequenceMethodTraits<std::vector<<unnamed>::COFFYAML::Relocation, std::allocator<<unnamed>::COFFYAML::Relocation> > >::value': /Volumes/Macintosh_HD2/buildbots/clang-x86_64-darwin11-self-mingw32/llvm.src/include/llvm/Support/YAMLTraits.h:281: instantiated from 'llvm::yaml::has_SequenceTraits<std::vector<<unnamed>::COFFYAML::Relocation, std::allocator<<unnamed>::COFFYAML::Relocation> > >' /Volumes/Macintosh_HD2/buildbots/clang-x86_64-darwin11-self-mingw32/llvm.src/utils/yaml2obj/yaml2obj.cpp:627: instantiated from here /Volumes/Macintosh_HD2/buildbots/clang-x86_64-darwin11-self-mingw32/llvm.src/include/llvm/Support/YAMLTraits.h:243: error: 'llvm::yaml::SequenceTraits<std::vector<<unnamed>::COFFYAML::Relocation, std::allocator<<unnamed>::COFFYAML::Relocation> > >::size' is not a valid template argument for type 'size_t (*)(llvm::yaml::IO&, std::vector<<unnamed>::COFFYAML::Relocation, std::allocator<<unnamed>::COFFYAML::Relocation> >&)' because function 'static size_t llvm::yaml::SequenceTraits<std::vector<<unnamed>::COFFYAML::Relocation, std::allocator<<unnamed>::COFFYAML::Relocation> > >::size(llvm::yaml::IO&, std::vector<<unnamed>::COFFYAML::Relocation, std::allocator<<unnamed>::COFFYAML::Relocation> >&)' has not external linkage git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178600 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02Use yaml::IO in yaml2obj.cpp.Rafael Espindola1-551/+346
The generic structs and specializations will be refactored when obj2yaml is changed to use yaml::IO. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178593 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29Fix TableGen subtarget-emitter to handle A9/Swift.Andrew Trick1-5/+11
A9 uses itinerary classes, Swift uses RW lists. This tripped some verification when we're expanding variants. I had to refine the verification a bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178357 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29Revert r178166. According to Howard, this code is actually ok.Dan Gohman1-3/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178319 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-27Avoid undefined behavior from passing a std::vector's own contentsDan Gohman1-1/+3
in as an argument to push_back. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178166 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26TableGen SubtargetEmitter fix to allow A9 and Swift to coexist.Andrew Trick2-2/+24
Allow variants to be defined only for some processors on a target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178074 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25x86 -- add the XTEST instructionDave Zarzycki1-8/+9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177888 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-24Allow types to be omitted in output patterns.Jakob Stoklund Olesen2-0/+16
This syntax is now preferred: def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>; There is no reason to repeat the types in the output pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177844 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-24Allow direct value types to be used in instruction 'set' patterns.Jakob Stoklund Olesen1-2/+24
This makes it possible to define instruction patterns like this: def LDri : F3_2<3, 0b000000, (outs IntRegs:$dst), (ins MEMri:$addr), "ld [$addr], $dst", [(set i32:$dst, (load ADDRri:$addr))]>; ~~~ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177834 91177308-0d34-0410-b5e6-96231b3b80d8
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