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2015-01-06XXX: R600/SI VOP1 Assemblerassembler-Jan-06-2015Tom Stellard1-1/+3
2015-01-06R600/SI:: XX MUBUF store assembler.Tom Stellard2-3/+127
2015-01-06R600/SI: Encode offset as 0 for mubuf _BOTHEN instructionsTom Stellard1-1/+1
2015-01-06R600/SI: Add soffset operand to mubuf addr64 instructionTom Stellard5-28/+32
2015-01-06Revert "XXX: Select all immediates to SALU"Tom Stellard1-2/+2
2015-01-06XXX: V_CNDMASKTom Stellard1-0/+5
2014-12-30R600/SI: Add assembler support for VOP2 instructionsTom Stellard5-24/+201
2014-12-30R600/SI: Fix mad*k definitionsTom Stellard3-5/+38
2014-12-30R600/SI: Add 32-bit encoding of v_cndmask_b32Tom Stellard3-7/+8
2014-12-30R600/SI: Add assembler support for sop2 instructionsTom Stellard3-15/+16
2014-12-30R600/SI: Refactor SOP2 definitionsTom Stellard1-25/+17
2014-12-30XXX: Select all immediates to SALUTom Stellard1-2/+2
2014-12-30XXX: Implent inline asm hooksTom Stellard6-3/+48
2014-12-30R600/SI: Assembler support for SOP1 instructionsTom Stellard5-21/+103
2014-12-16R600/SI: Add assembler support for s_load_dword* instructionsTom Stellard2-15/+150
2014-12-16R600/SI: Refactor SOP1 classesTom Stellard1-26/+19
2014-12-16R600/SI: Lowercase register namesTom Stellard1-4/+4
2014-12-16R600/SI: Use RegisterOperands to specify which operands can accept immediatesTom Stellard10-70/+85
2014-12-11R600/SI: Remove some unused TableGen classesTom Stellard1-19/+0
2014-12-11R600/SI: Remove SIISelLowering::legalizeOperands()remove-fold-operandsTom Stellard2-176/+1
2014-12-11R600/SI: Teach SIFoldOperands to split 64-bit constants when foldingTom Stellard1-17/+43
2014-12-11R600/SI: isLegalOperand() shouldn't check constant bus for SALU instructionsTom Stellard1-1/+1
2014-12-11R600/SI: Use immediates in the first operand in fabs/fneg patternsTom Stellard1-9/+9
2014-12-11R600/SI: Use unordered equal instructionsMatt Arsenault2-6/+2
2014-12-11R600/SI: Make more unordered comparisons legalMatt Arsenault3-18/+9
2014-12-11R600/SI: Use unordered not equal instructionsMatt Arsenault4-10/+19
2014-12-11[CodeGen] Add print and verify pass after each MachineFunctionPass by defaultMatthias Braun1-26/+21
2014-12-11This reverts commit r224043 and r224042.Rafael Espindola1-21/+26
2014-12-11[CodeGen] Add print and verify pass after each MachineFunctionPass by defaultMatthias Braun1-26/+21
2014-12-10R600/SI: Use getTargetConstant in AdjustRegClassMarek Olsak1-2/+2
2014-12-09R600/SI: Set MayStore = 0 on MUBUF loadsTom Stellard1-1/+1
2014-12-09R600/SI: Move setting of the lds bit to the base MUBUF classTom Stellard1-6/+9
2014-12-08R600/SI: Move continue after checking s_mov_b32.Matt Arsenault1-3/+3
2014-12-07R600/SI: Disable VMEM and SMEM clauses by breaking them with S_NOPMarek Olsak1-8/+46
2014-12-07R600/SI: Set 20-bit immediate byte offset for SMRD on VIMarek Olsak6-20/+85
2014-12-07R600/SI: Update instruction conversions for VIMarek Olsak3-1/+48
2014-12-07R600/SI: Add VI instructionsMarek Olsak12-651/+1439
2014-12-07R600/SI: Add SCC Defs/Uses to SOP1 and SOP2 opcodesMarek Olsak1-28/+49
2014-12-06R600/SI: Restore PrivateGlobalPrefix to the default ELF value of ".L"Tom Stellard1-1/+0
2014-12-04Allow target to specify prefix for labelsMatt Arsenault1-0/+2
2014-12-03R600/SI: Move SIInsertWaits into AMDGPUPassConfig::addPreSched2()Tom Stellard1-1/+3
2014-12-03R600/SI: Don't run SI passes on R600 subtargetsTom Stellard1-1/+1
2014-12-03Silencing a 32-bit implicit conversion warning in MSVC; NFC.Aaron Ballman1-1/+1
2014-12-03R600/SI: Fix SIFixSGPRCopies for copies to physical registersMatt Arsenault1-1/+6
2014-12-03R600/SI: Remove incorrect assertionMatt Arsenault1-5/+5
2014-12-03R600/SI: Remove i1 pseudo VALU opsMatt Arsenault3-63/+70
2014-12-03R600/SI: Fix suspicious indexingMatt Arsenault1-5/+7
2014-12-03R600/SI: Fix running SILowerI1Copies a second timeMatt Arsenault1-2/+1
2014-12-03R600/SI: Fix live range error hidden by SIFoldOperandsMatt Arsenault1-0/+9
2014-12-03R600/SI: Enable inline assemblyTom Stellard1-2/+1