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~tstellar/llvm
9.1-abi-fix
Nov13-test
Oct18-backup
assembler
assembler-Jan-06-2015
assembler-push
backup-Oct15
backup-Oct18
bfgminer
bfgminer-perf
cayman-only-bfgminer
clover-elf
clover-elf-v2
hazard-rec
hsa
image-support
indirect-addressing
indirect-wip
indirect-wip-2
indirect-wip-3
indirect-wip-4
indirect-wip-5
kernel-args-WIP
lds
lds-v2
long-alu
madk
master
master-testing
master-testing-patches
master-testing-patches-v2
master-testing-si
master-testing-v2
mi-sched-experimental
native
opencv-Sep18-patches
perf-Dec31-2014
perf-Jan-08-2015
push-jan16
r600
r600-May09
r600-alu-encoding
r600-final-push
r600-gen-fixes
r600-imm-flags
r600-initial-review
r600-initial-review-May11
r600-master
r600-private-mem-fixes
r600-private-memory
r600-review-v10
r600-review-v3
r600-review-v7
r600-review-v8
r600-review-v9
r600-rewrite-pats
r600-structurizer
r600-structurizer-v2
r600-tablegen-hwreg
r600-tablegen-reg-encoding
r600-vliw
remove-fold-operands
sched-fixes
sched-perf-Mar-27-2015
si-compute
si-compute-v3
si-fold
si-lowercase
si-scheduler
si-scheduler-v2
si-scheduler-v3
si-sgpr-copies
si-spill-fixes
si-spill-fixes-v2
si-spill-fixes-v3
si-spill-fixes-v4
smrd-cluster
struct-divergence
struct-divergence-v1
vgpr-spilling-Jan07-2014
vinterp-fix
vliw5-rebase
vlj-bottom-up
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R600
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Author
Files
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2015-01-06
XXX: R600/SI VOP1 Assembler
assembler-Jan-06-2015
Tom Stellard
1
-1
/
+3
2015-01-06
R600/SI:: XX MUBUF store assembler.
Tom Stellard
2
-3
/
+127
2015-01-06
R600/SI: Encode offset as 0 for mubuf _BOTHEN instructions
Tom Stellard
1
-1
/
+1
2015-01-06
R600/SI: Add soffset operand to mubuf addr64 instruction
Tom Stellard
5
-28
/
+32
2015-01-06
Revert "XXX: Select all immediates to SALU"
Tom Stellard
1
-2
/
+2
2015-01-06
XXX: V_CNDMASK
Tom Stellard
1
-0
/
+5
2014-12-30
R600/SI: Add assembler support for VOP2 instructions
Tom Stellard
5
-24
/
+201
2014-12-30
R600/SI: Fix mad*k definitions
Tom Stellard
3
-5
/
+38
2014-12-30
R600/SI: Add 32-bit encoding of v_cndmask_b32
Tom Stellard
3
-7
/
+8
2014-12-30
R600/SI: Add assembler support for sop2 instructions
Tom Stellard
3
-15
/
+16
2014-12-30
R600/SI: Refactor SOP2 definitions
Tom Stellard
1
-25
/
+17
2014-12-30
XXX: Select all immediates to SALU
Tom Stellard
1
-2
/
+2
2014-12-30
XXX: Implent inline asm hooks
Tom Stellard
6
-3
/
+48
2014-12-30
R600/SI: Assembler support for SOP1 instructions
Tom Stellard
5
-21
/
+103
2014-12-16
R600/SI: Add assembler support for s_load_dword* instructions
Tom Stellard
2
-15
/
+150
2014-12-16
R600/SI: Refactor SOP1 classes
Tom Stellard
1
-26
/
+19
2014-12-16
R600/SI: Lowercase register names
Tom Stellard
1
-4
/
+4
2014-12-16
R600/SI: Use RegisterOperands to specify which operands can accept immediates
Tom Stellard
10
-70
/
+85
2014-12-11
R600/SI: Remove some unused TableGen classes
Tom Stellard
1
-19
/
+0
2014-12-11
R600/SI: Remove SIISelLowering::legalizeOperands()
remove-fold-operands
Tom Stellard
2
-176
/
+1
2014-12-11
R600/SI: Teach SIFoldOperands to split 64-bit constants when folding
Tom Stellard
1
-17
/
+43
2014-12-11
R600/SI: isLegalOperand() shouldn't check constant bus for SALU instructions
Tom Stellard
1
-1
/
+1
2014-12-11
R600/SI: Use immediates in the first operand in fabs/fneg patterns
Tom Stellard
1
-9
/
+9
2014-12-11
R600/SI: Use unordered equal instructions
Matt Arsenault
2
-6
/
+2
2014-12-11
R600/SI: Make more unordered comparisons legal
Matt Arsenault
3
-18
/
+9
2014-12-11
R600/SI: Use unordered not equal instructions
Matt Arsenault
4
-10
/
+19
2014-12-11
[CodeGen] Add print and verify pass after each MachineFunctionPass by default
Matthias Braun
1
-26
/
+21
2014-12-11
This reverts commit r224043 and r224042.
Rafael Espindola
1
-21
/
+26
2014-12-11
[CodeGen] Add print and verify pass after each MachineFunctionPass by default
Matthias Braun
1
-26
/
+21
2014-12-10
R600/SI: Use getTargetConstant in AdjustRegClass
Marek Olsak
1
-2
/
+2
2014-12-09
R600/SI: Set MayStore = 0 on MUBUF loads
Tom Stellard
1
-1
/
+1
2014-12-09
R600/SI: Move setting of the lds bit to the base MUBUF class
Tom Stellard
1
-6
/
+9
2014-12-08
R600/SI: Move continue after checking s_mov_b32.
Matt Arsenault
1
-3
/
+3
2014-12-07
R600/SI: Disable VMEM and SMEM clauses by breaking them with S_NOP
Marek Olsak
1
-8
/
+46
2014-12-07
R600/SI: Set 20-bit immediate byte offset for SMRD on VI
Marek Olsak
6
-20
/
+85
2014-12-07
R600/SI: Update instruction conversions for VI
Marek Olsak
3
-1
/
+48
2014-12-07
R600/SI: Add VI instructions
Marek Olsak
12
-651
/
+1439
2014-12-07
R600/SI: Add SCC Defs/Uses to SOP1 and SOP2 opcodes
Marek Olsak
1
-28
/
+49
2014-12-06
R600/SI: Restore PrivateGlobalPrefix to the default ELF value of ".L"
Tom Stellard
1
-1
/
+0
2014-12-04
Allow target to specify prefix for labels
Matt Arsenault
1
-0
/
+2
2014-12-03
R600/SI: Move SIInsertWaits into AMDGPUPassConfig::addPreSched2()
Tom Stellard
1
-1
/
+3
2014-12-03
R600/SI: Don't run SI passes on R600 subtargets
Tom Stellard
1
-1
/
+1
2014-12-03
Silencing a 32-bit implicit conversion warning in MSVC; NFC.
Aaron Ballman
1
-1
/
+1
2014-12-03
R600/SI: Fix SIFixSGPRCopies for copies to physical registers
Matt Arsenault
1
-1
/
+6
2014-12-03
R600/SI: Remove incorrect assertion
Matt Arsenault
1
-5
/
+5
2014-12-03
R600/SI: Remove i1 pseudo VALU ops
Matt Arsenault
3
-63
/
+70
2014-12-03
R600/SI: Fix suspicious indexing
Matt Arsenault
1
-5
/
+7
2014-12-03
R600/SI: Fix running SILowerI1Copies a second time
Matt Arsenault
1
-2
/
+1
2014-12-03
R600/SI: Fix live range error hidden by SIFoldOperands
Matt Arsenault
1
-0
/
+9
2014-12-03
R600/SI: Enable inline assembly
Tom Stellard
1
-2
/
+1
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