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path: root/lib/Target/R600/SIISelLowering.cpp
AgeCommit message (Expand)AuthorFilesLines
2014-08-09R600/SI: Custom lower CONCAT_VECTORSTom Stellard1-1/+3
2014-08-06Remove the target machine from CCState. Previously it was only usedEric Christopher1-2/+2
2014-08-04Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher1-27/+26
2014-08-02R600/SI: Fix formatting.Matt Arsenault1-22/+28
2014-08-01[SDAG] MorphNodeTo recursively deletes dead operands of the oldChandler Carruth1-1/+3
2014-08-01R600/SI: Do abs/neg folding with ComplexPatternsTom Stellard1-25/+7
2014-07-28R600/SI: Implement getOptimalMemOpTypeMatt Arsenault1-0/+20
2014-07-28R600/SI: Make argument loads invariantMatt Arsenault1-9/+17
2014-07-27Add alignment value to allowsUnalignedMemoryAccessMatt Arsenault1-8/+10
2014-07-26R600: Move intrinsic lowering to separate functionsMatt Arsenault1-109/+123
2014-07-24R600: Add new functions for splitting vector loads and stores.Matt Arsenault1-3/+3
2014-07-21R600/SI: Clean up some of the unused REGISTER_{LOAD,STORE} codeTom Stellard1-148/+24
2014-07-21R600/SI: Use scratch memory for large private arraysTom Stellard1-8/+86
2014-07-21R600/SI: Store constant initializer data in constant memoryTom Stellard1-0/+28
2014-07-20SIISelLowering.cpp: Define _USE_MATH_DEFINES to let M_PI provided on MS <cmath>.NAKAMURA Takumi1-0/+6
2014-07-20R600/SI: Remove dead code and add missing tests.Matt Arsenault1-14/+0
2014-07-19R600/SI: implement range reduction for sin/cosMatt Arsenault1-0/+23
2014-07-15R600/SI: Allow using f32 rcp / rsq when denormals not handled.Matt Arsenault1-8/+29
2014-07-15R600/SI: Fix select on i1Matt Arsenault1-0/+3
2014-07-15R600/SI: Implement less wrong f32 fdivMatt Arsenault1-0/+76
2014-07-13R600: Make ShaderType privateMatt Arsenault1-6/+7
2014-07-10R600: Implement float to long/ulongJan Vesely1-0/+3
2014-07-07R600: Fix mishandling of load / store chains.Matt Arsenault1-24/+33
2014-07-03[codegen,aarch64] Add a target hook to the code generator to controlChandler Carruth1-2/+6
2014-07-02R600: Promote i64 loads to v2i32Tom Stellard1-1/+8
2014-06-24R600: Promote i64 stores to v2i32Tom Stellard1-1/+6
2014-06-23R600: Move more out of AMDILISelLoweringMatt Arsenault1-1/+3
2014-06-23R600/SI: Handle i64 sub.Matt Arsenault1-0/+2
2014-06-23R600: Rename AMDIL fileMatt Arsenault1-1/+1
2014-06-18R600/SI: Prettier operand printing for 64-bit ops.Matt Arsenault1-11/+12
2014-06-18R600/SI: Temporary fix for f64 fnegMatt Arsenault1-0/+4
2014-06-11R600/SI: Use v_cvt_f32_ubyte* instructionsMatt Arsenault1-0/+118
2014-06-10R600: Use BCNT_INT for evergreenMatt Arsenault1-3/+0
2014-06-10R600/SI: Implement i64 ctpopMatt Arsenault1-0/+1
2014-06-10R600/SI: Use bcnt instruction for ctpopMatt Arsenault1-0/+2
2014-06-10R600/SI: Handle sign_extend and zero_extend to i64 with patterns.Matt Arsenault1-40/+0
2014-06-10SelectionDAG: Expand SELECT_CC to SELECT + SETCCTom Stellard1-18/+4
2014-06-05Use nullptrMatt Arsenault1-3/+2
2014-06-03Fix typosMatt Arsenault1-6/+6
2014-05-22R600: Add dag combine for BFEMatt Arsenault1-1/+2
2014-05-16R600/SI: Promote f32 SELECT to i32Tom Stellard1-0/+2
2014-05-15Use range forMatt Arsenault1-3/+2
2014-05-15R600/SI: Stop using VSrc_* as the default register class for types.Tom Stellard1-42/+7
2014-05-10R600/SI: Fold fabs/fneg into src input modifierVincent Lejeune1-2/+31
2014-05-10R600/SI: Prettier display of input modifiersVincent Lejeune1-5/+11
2014-05-10R600/SI: Use pseudo instruction for fabs/clamp/fnegVincent Lejeune1-0/+44
2014-05-09R600: Move MIN/MAX matching from LowerOperation() to PerformDAGCombine()Tom Stellard1-6/+0
2014-04-30R600/SI: Use VALU instructions for copying i1 valuesTom Stellard1-1/+1
2014-04-29R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errorsTom Stellard1-9/+40
2014-04-29R600: Change UDIV/UREM to UDIVREM when legalizing typesTom Stellard1-0/+4
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