| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2015-03-11 | Remove the need to cache the subtarget in the R600 TargetRegisterInfo | Eric Christopher | 1 | -4/+1 |
| 2014-12-03 | R600/SI: Enable inline assembly | Tom Stellard | 1 | -2/+1 |
| 2014-06-13 | R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtarget | Tom Stellard | 1 | -2/+2 |
| 2014-05-15 | Use range for | Matt Arsenault | 1 | -1/+1 |
| 2014-04-04 | Make consistent use of MCPhysReg instead of uint16_t throughout the tree. | Craig Topper | 1 | -3/+3 |
| 2013-12-10 | Use llvm_unreachable instead of assert(0) | Matt Arsenault | 1 | -1/+1 |
| 2013-08-14 | R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2 | Tom Stellard | 1 | -19/+13 |
| 2013-06-07 | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 1 | -4/+2 |
| 2013-02-07 | R600: Consolidate sub register indices. | Tom Stellard | 1 | -16/+16 |
| 2013-02-06 | R600: Support for indirect addressing v4 | Tom Stellard | 1 | -0/+23 |
| 2013-01-31 | Update AMDGPURegisterInfo::eliminateFrameIndex() corresponding to r174083. | NAKAMURA Takumi | 1 | -0/+1 |
| 2012-12-11 | Add R600 backend | Tom Stellard | 1 | -0/+51 |
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index : ~tstellar/llvm | |
| Unnamed repository; edit this file 'description' to name the repository. | tstellar |
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