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path: root/lib/Target/ARM/ARMBaseInstrInfo.cpp
AgeCommit message (Expand)AuthorFilesLines
2013-04-05ARM scheduler model: Swift has varying latencies, uops for simple ALU opsArnold Schwaighofer1-0/+12
2013-03-27Enabling the generation of dependency breakers for partial updates on Cortex-...Silviu Baranga1-7/+5
2013-03-15Adding an A15 specific optimization pass for interactions between S/D/Q regis...Silviu Baranga1-1/+1
2013-02-21Radar numbers don't belong in source code.Evan Cheng1-2/+0
2013-01-02Move all of the header files which are involved in modelling the LLVM IRChandler Carruth1-3/+3
2012-12-30Remove the Function::getFnAttributes method in favor of using the AttributeSetBill Wendling1-2/+3
2012-12-20MachineInstrBuilderize ARM.Jakob Stoklund Olesen1-3/+4
2012-12-19Remove the explicit MachineInstrBuilder(MI) constructor.Jakob Stoklund Olesen1-3/+4
2012-12-19Rename the 'Attributes' class to 'Attribute'. It's going to represent a singl...Bill Wendling1-1/+1
2012-12-03Use the new script to sort the includes of every file under lib.Chandler Carruth1-4/+4
2012-11-28Remove all references to TargetInstrInfoImpl.Jakob Stoklund Olesen1-5/+5
2012-11-12misched: Target-independent support for load/store clustering.Andrew Trick1-0/+6
2012-10-26Add GPRPair Register class to ARM.Jakob Stoklund Olesen1-0/+19
2012-10-10misched: Use the TargetSchedModel interface wherever possible.Andrew Trick1-12/+0
2012-10-10whitespaceAndrew Trick1-3/+3
2012-10-09Create enums for the different attributes.Bill Wendling1-1/+2
2012-09-29Add LLVM support for Swift.Bob Wilson1-9/+458
2012-09-26Remove the `hasFnAttr' method from Function.Bill Wendling1-1/+1
2012-09-18More domain conversion; convert VFP VMOVS to NEON instructions in more cases ...James Molloy1-13/+56
2012-09-14Implement getNumLDMAddresses and expose through ARMBaseInstrInfo.Andrew Trick1-0/+31
2012-09-13This patch introduces A15 as a target in LLVM.Silviu Baranga1-13/+13
2012-09-10Don't attempt to use flags from predicated instructions.Jakob Stoklund Olesen1-2/+8
2012-09-05Use predication instead of pseudo-opcodes when folding into MOVCC.Jakob Stoklund Olesen1-56/+31
2012-09-05Strip old MachineInstrs *after* we know we can put them back.Tim Northover1-6/+6
2012-09-01Limit domain conversion to cases where it won't break dep chains.Tim Northover1-12/+48
2012-08-30Add support for moving pure S-register to NEON pipeline if desiredTim Northover1-2/+71
2012-08-29Refactor setExecutionDomain to be clearer about what it's doing and more robust.Tim Northover1-45/+53
2012-08-29Cleanup sloppy code. Jakob's review.Andrew Trick1-4/+3
2012-08-29Fix ARM vector copies of overlapping register tuples.Andrew Trick1-0/+13
2012-08-29cleanupAndrew Trick1-21/+19
2012-08-28Revert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ...Jakob Stoklund Olesen1-10/+10
2012-08-27Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM.Jakob Stoklund Olesen1-10/+10
2012-08-27Make sure we add the predicate after all of the registers are added.Bill Wendling1-2/+3
2012-08-21Add a missing def flag.Jakob Stoklund Olesen1-4/+2
2012-08-17Avoid folding ADD instructions with FI operands.Jakob Stoklund Olesen1-0/+3
2012-08-17Implement NEON domain switching for scalar <-> S-register vmovs on ARMTim Northover1-15/+97
2012-08-16Add ADD and SUB to the predicable ARM instructions.Jakob Stoklund Olesen1-0/+20
2012-08-16Handle ARM MOVCC optimization in PeepholeOptimizer.Jakob Stoklund Olesen1-3/+64
2012-08-15Fold predicable instructions into MOVCC / t2MOVCC.Jakob Stoklund Olesen1-0/+49
2012-08-04Recognize vst1.64 / vld1.64 with 3 and 4 regs as load from / store to stack s...Anton Korobeynikov1-0/+4
2012-08-04Add stack spill / reload instructions for DTriple and DQuad register classes,...Anton Korobeynikov1-3/+43
2012-07-23Fix a typo (the the => the)Sylvestre Ledru1-1/+1
2012-07-11ARM: fix typo in commentsManman Ren1-1/+1
2012-07-11ARM: Fix optimizeCompare to correctly check safe condition.Manman Ren1-9/+14
2012-07-02Revert accidental checkin.Andrew Trick1-3/+2
2012-07-02Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary."Andrew Trick1-10/+11
2012-06-29ARM: Clean up optimizeCompare in peephole, no functional change.Manman Ren1-80/+73
2012-06-29Add SrcReg2 to analyzeCompare and optimizeCompareInstr to handle CompareManman Ren1-14/+21
2012-06-29Revert "Make NumMicroOps a variable in the subtarget's instruction itinerary."Andrew Trick1-9/+9
2012-06-29Make NumMicroOps a variable in the subtarget's instruction itinerary.Andrew Trick1-9/+9