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~tstellar/llvm
9.1-abi-fix
Nov13-test
Oct18-backup
assembler
assembler-Jan-06-2015
assembler-push
backup-Oct15
backup-Oct18
bfgminer
bfgminer-perf
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clover-elf
clover-elf-v2
hazard-rec
hsa
image-support
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indirect-wip-3
indirect-wip-4
indirect-wip-5
kernel-args-WIP
lds
lds-v2
long-alu
madk
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master-testing
master-testing-patches
master-testing-patches-v2
master-testing-si
master-testing-v2
mi-sched-experimental
native
opencv-Sep18-patches
perf-Dec31-2014
perf-Jan-08-2015
push-jan16
r600
r600-May09
r600-alu-encoding
r600-final-push
r600-gen-fixes
r600-imm-flags
r600-initial-review
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r600-master
r600-private-mem-fixes
r600-private-memory
r600-review-v10
r600-review-v3
r600-review-v7
r600-review-v8
r600-review-v9
r600-rewrite-pats
r600-structurizer
r600-structurizer-v2
r600-tablegen-hwreg
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r600-vliw
remove-fold-operands
sched-fixes
sched-perf-Mar-27-2015
si-compute
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si-scheduler-v3
si-sgpr-copies
si-spill-fixes
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si-spill-fixes-v3
si-spill-fixes-v4
smrd-cluster
struct-divergence
struct-divergence-v1
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vinterp-fix
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path:
root
/
lib
/
Target
/
ARM
/
ARMBaseInstrInfo.cpp
Age
Commit message (
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)
Author
Files
Lines
2013-04-05
ARM scheduler model: Swift has varying latencies, uops for simple ALU ops
Arnold Schwaighofer
1
-0
/
+12
2013-03-27
Enabling the generation of dependency breakers for partial updates on Cortex-...
Silviu Baranga
1
-7
/
+5
2013-03-15
Adding an A15 specific optimization pass for interactions between S/D/Q regis...
Silviu Baranga
1
-1
/
+1
2013-02-21
Radar numbers don't belong in source code.
Evan Cheng
1
-2
/
+0
2013-01-02
Move all of the header files which are involved in modelling the LLVM IR
Chandler Carruth
1
-3
/
+3
2012-12-30
Remove the Function::getFnAttributes method in favor of using the AttributeSet
Bill Wendling
1
-2
/
+3
2012-12-20
MachineInstrBuilderize ARM.
Jakob Stoklund Olesen
1
-3
/
+4
2012-12-19
Remove the explicit MachineInstrBuilder(MI) constructor.
Jakob Stoklund Olesen
1
-3
/
+4
2012-12-19
Rename the 'Attributes' class to 'Attribute'. It's going to represent a singl...
Bill Wendling
1
-1
/
+1
2012-12-03
Use the new script to sort the includes of every file under lib.
Chandler Carruth
1
-4
/
+4
2012-11-28
Remove all references to TargetInstrInfoImpl.
Jakob Stoklund Olesen
1
-5
/
+5
2012-11-12
misched: Target-independent support for load/store clustering.
Andrew Trick
1
-0
/
+6
2012-10-26
Add GPRPair Register class to ARM.
Jakob Stoklund Olesen
1
-0
/
+19
2012-10-10
misched: Use the TargetSchedModel interface wherever possible.
Andrew Trick
1
-12
/
+0
2012-10-10
whitespace
Andrew Trick
1
-3
/
+3
2012-10-09
Create enums for the different attributes.
Bill Wendling
1
-1
/
+2
2012-09-29
Add LLVM support for Swift.
Bob Wilson
1
-9
/
+458
2012-09-26
Remove the `hasFnAttr' method from Function.
Bill Wendling
1
-1
/
+1
2012-09-18
More domain conversion; convert VFP VMOVS to NEON instructions in more cases ...
James Molloy
1
-13
/
+56
2012-09-14
Implement getNumLDMAddresses and expose through ARMBaseInstrInfo.
Andrew Trick
1
-0
/
+31
2012-09-13
This patch introduces A15 as a target in LLVM.
Silviu Baranga
1
-13
/
+13
2012-09-10
Don't attempt to use flags from predicated instructions.
Jakob Stoklund Olesen
1
-2
/
+8
2012-09-05
Use predication instead of pseudo-opcodes when folding into MOVCC.
Jakob Stoklund Olesen
1
-56
/
+31
2012-09-05
Strip old MachineInstrs *after* we know we can put them back.
Tim Northover
1
-6
/
+6
2012-09-01
Limit domain conversion to cases where it won't break dep chains.
Tim Northover
1
-12
/
+48
2012-08-30
Add support for moving pure S-register to NEON pipeline if desired
Tim Northover
1
-2
/
+71
2012-08-29
Refactor setExecutionDomain to be clearer about what it's doing and more robust.
Tim Northover
1
-45
/
+53
2012-08-29
Cleanup sloppy code. Jakob's review.
Andrew Trick
1
-4
/
+3
2012-08-29
Fix ARM vector copies of overlapping register tuples.
Andrew Trick
1
-0
/
+13
2012-08-29
cleanup
Andrew Trick
1
-21
/
+19
2012-08-28
Revert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ...
Jakob Stoklund Olesen
1
-10
/
+10
2012-08-27
Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM.
Jakob Stoklund Olesen
1
-10
/
+10
2012-08-27
Make sure we add the predicate after all of the registers are added.
Bill Wendling
1
-2
/
+3
2012-08-21
Add a missing def flag.
Jakob Stoklund Olesen
1
-4
/
+2
2012-08-17
Avoid folding ADD instructions with FI operands.
Jakob Stoklund Olesen
1
-0
/
+3
2012-08-17
Implement NEON domain switching for scalar <-> S-register vmovs on ARM
Tim Northover
1
-15
/
+97
2012-08-16
Add ADD and SUB to the predicable ARM instructions.
Jakob Stoklund Olesen
1
-0
/
+20
2012-08-16
Handle ARM MOVCC optimization in PeepholeOptimizer.
Jakob Stoklund Olesen
1
-3
/
+64
2012-08-15
Fold predicable instructions into MOVCC / t2MOVCC.
Jakob Stoklund Olesen
1
-0
/
+49
2012-08-04
Recognize vst1.64 / vld1.64 with 3 and 4 regs as load from / store to stack s...
Anton Korobeynikov
1
-0
/
+4
2012-08-04
Add stack spill / reload instructions for DTriple and DQuad register classes,...
Anton Korobeynikov
1
-3
/
+43
2012-07-23
Fix a typo (the the => the)
Sylvestre Ledru
1
-1
/
+1
2012-07-11
ARM: fix typo in comments
Manman Ren
1
-1
/
+1
2012-07-11
ARM: Fix optimizeCompare to correctly check safe condition.
Manman Ren
1
-9
/
+14
2012-07-02
Revert accidental checkin.
Andrew Trick
1
-3
/
+2
2012-07-02
Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary."
Andrew Trick
1
-10
/
+11
2012-06-29
ARM: Clean up optimizeCompare in peephole, no functional change.
Manman Ren
1
-80
/
+73
2012-06-29
Add SrcReg2 to analyzeCompare and optimizeCompareInstr to handle Compare
Manman Ren
1
-14
/
+21
2012-06-29
Revert "Make NumMicroOps a variable in the subtarget's instruction itinerary."
Andrew Trick
1
-9
/
+9
2012-06-29
Make NumMicroOps a variable in the subtarget's instruction itinerary.
Andrew Trick
1
-9
/
+9
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