~tstellar/llvm - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2012-11-16	XXX: First try at LDS.indirect-wip-3	Tom Stellard	5	-6/+135
2012-11-16	radeon/llvm: support for v2f32 store/load	Vincent Lejeune	1	-6/+57
2012-11-16	XXX: WIP multiple frame object support	Tom Stellard	6	-6/+38
2012-11-16	Indirect Adressing: Fix IndirectIndexEnd calculation	Tom Stellard	1	-3/+9
2012-11-16	R600: Support for indirect addressing	Tom Stellard	17	-8/+464
2012-11-16	AMDGPU: Fix name of SI control flow lowering source file.	Michel Dänzer	1	-1/+1
2012-11-16	AMDGPU: Don't allow using SI SGPRs 102 and 103 directly.	Michel Dänzer	1	-2/+2
2012-11-16	AMDGPU: Fix string concatenation in AMDGPUInstPrinter::printRel().	Michel Dänzer	1	-1/+1
2012-11-16	R600: replaces fragment input with negative index with undef values	Vincent Lejeune	1	-3/+9
2012-11-16	R600: Fix operand index table for OP3 instructions	Tom Stellard	1	-1/+1
2012-11-16	AMDGPU: Print integer and floating point values for literals	Tom Stellard	3	-1/+13
2012-11-16	R600: Add helper function for setting instruction modifiers	Tom Stellard	3	-9/+16
2012-11-13	AMDGPU: Fix builds with -DNDEBUG	tstellar	1	-0/+2
2012-11-13	R600: Fix sampler->resource_id mapping	tstellar	1	-2/+2
2012-11-13	SI: s/flow control/control flow/g .	tstellar	4	-15/+15
2012-11-13	SI: fix SGPR liveness v4	tstellar	4	-0/+191
2012-11-13	SI: Add intrinsic for sampling with explicit LOD.	tstellar	2	-1/+9
2012-11-13	SI: Add intrinsic for sampling with bias.	tstellar	2	-1/+9
2012-11-13	SI: Update flow control comments to match current code.	tstellar	1	-4/+5
2012-11-13	Merge master branch	tstellar	599	-7650/+20056
2012-11-13	SI: Only allow SGPR for the first operand of VOP3 instructions.	tstellar	2	-4/+4
2012-10-31	SI: Enable control flow pass again	tstellar	1	-2/+1
2012-10-31	SI: Handle kilp intrinsic	tstellar	1	-0/+5
2012-10-31	SI: Use SReg_1 class for SI_IF_(N)Z condition code operand	tstellar	1	-3/+3
2012-10-31	SI: Prevent instructions modifying the EXEC register from being moved	tstellar	2	-0/+6
2012-10-31	SI: Handle more cases in copyPhysReg callback	tstellar	1	-3/+15
2012-10-31	SI: Alternative handling of EXEC register for control flow	tstellar	2	-26/+36
2012-10-31	SI: Use SReg_64RegClass for i64 register class	tstellar	1	-1/+1
2012-10-31	R600: use specialised R600.store.pixel.* for fragment shader	tstellar	8	-2/+185
2012-10-26	R600: Add a v4f32 to v4i32 BitConvert pattern	tstellar	1	-0/+1
2012-10-26	R600: Set isBarrier bit for JUMP instruction	tstellar	1	-2/+2
2012-10-25	SI: Add intrinsic for reading the FRONT_FACE VGPR.	tstellar	2	-0/+6
2012-10-25	SI: Use 64-bit encoding for V_CMP instructions	tstellar	6	-51/+155
2012-10-22	R600: Cayman uses vector instruction for SIN/COS/RECIP_CLAMPED_RECIPSQRT_IEEE	tstellar	1	-10/+20
2012-10-22	R600: turn select into select_cc	tstellar	2	-0/+17
2012-10-22	R600: add support for vector setCC	tstellar	1	-4/+2
2012-10-22	R600: Remove input.face and input.position intrinsics	tstellar	3	-40/+0
2012-10-22	R600: Add super reg to reserved reg list	tstellar	1	-0/+3
2012-10-22	R600: interp instructions emits native outputs	tstellar	3	-38/+27
2012-10-22	R600: Fix llvm.pow.ll test	tstellar	1	-1/+1
2012-10-22	AMDGPU: Fix build after merge	tstellar	1	-1/+1
2012-10-22	Merge master branch	tstellar	164	-783/+5586
2012-10-19	R600: Remove deprecated code from R600MCCodeEmitter	tstellar	1	-129/+9
2012-10-19	R600: Use native operands for KILLGT instruction	tstellar	4	-38/+29
2012-10-19	R600: Use native operands for CUBE, DOT4 instructions	tstellar	3	-68/+46
2012-10-19	R600: Organize pseudo instruction in R600Instructions.td	tstellar	1	-27/+10
2012-10-19	R600: Add support for the AMDGPU::BREAK instruction	tstellar	1	-1/+17
2012-10-19	R600: Lower PRED_X to a native instruction prior to codegen	tstellar	9	-50/+111
2012-10-19	R600: Use native operands for R600_OP3 instructions	tstellar	1	-34/+64
2012-10-19	R600: Use native operands for R600_2OP instructions	tstellar	4	-123/+79