diff options
Diffstat (limited to 'test/CodeGen/R600/llvm.AMDGPU.bfe.u32.ll')
-rw-r--r-- | test/CodeGen/R600/llvm.AMDGPU.bfe.u32.ll | 332 |
1 files changed, 166 insertions, 166 deletions
diff --git a/test/CodeGen/R600/llvm.AMDGPU.bfe.u32.ll b/test/CodeGen/R600/llvm.AMDGPU.bfe.u32.ll index 1d239af7aa4..0794ac4480d 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.bfe.u32.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.bfe.u32.ll @@ -4,7 +4,7 @@ declare i32 @llvm.AMDGPU.bfe.u32(i32, i32, i32) nounwind readnone ; FUNC-LABEL: {{^}}bfe_u32_arg_arg_arg: -; SI: V_BFE_U32 +; SI: v_bfe_u32 ; EG: BFE_UINT define void @bfe_u32_arg_arg_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 %src0, i32 %src1, i32 %src1) nounwind readnone @@ -13,7 +13,7 @@ define void @bfe_u32_arg_arg_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i } ; FUNC-LABEL: {{^}}bfe_u32_arg_arg_imm: -; SI: V_BFE_U32 +; SI: v_bfe_u32 ; EG: BFE_UINT define void @bfe_u32_arg_arg_imm(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 %src0, i32 %src1, i32 123) nounwind readnone @@ -22,7 +22,7 @@ define void @bfe_u32_arg_arg_imm(i32 addrspace(1)* %out, i32 %src0, i32 %src1) n } ; FUNC-LABEL: {{^}}bfe_u32_arg_imm_arg: -; SI: V_BFE_U32 +; SI: v_bfe_u32 ; EG: BFE_UINT define void @bfe_u32_arg_imm_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src2) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 %src0, i32 123, i32 %src2) nounwind readnone @@ -31,7 +31,7 @@ define void @bfe_u32_arg_imm_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src2) n } ; FUNC-LABEL: {{^}}bfe_u32_imm_arg_arg: -; SI: V_BFE_U32 +; SI: v_bfe_u32 ; EG: BFE_UINT define void @bfe_u32_imm_arg_arg(i32 addrspace(1)* %out, i32 %src1, i32 %src2) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 123, i32 %src1, i32 %src2) nounwind readnone @@ -40,8 +40,8 @@ define void @bfe_u32_imm_arg_arg(i32 addrspace(1)* %out, i32 %src1, i32 %src2) n } ; FUNC-LABEL: {{^}}bfe_u32_arg_0_width_reg_offset: -; SI-NOT: BFE -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_arg_0_width_reg_offset(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 %src0, i32 %src1, i32 0) nounwind readnone @@ -50,8 +50,8 @@ define void @bfe_u32_arg_0_width_reg_offset(i32 addrspace(1)* %out, i32 %src0, i } ; FUNC-LABEL: {{^}}bfe_u32_arg_0_width_imm_offset: -; SI-NOT: BFE -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_arg_0_width_imm_offset(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 %src0, i32 8, i32 0) nounwind readnone @@ -60,9 +60,9 @@ define void @bfe_u32_arg_0_width_imm_offset(i32 addrspace(1)* %out, i32 %src0, i } ; FUNC-LABEL: {{^}}bfe_u32_zextload_i8: -; SI: BUFFER_LOAD_UBYTE -; SI-NOT: BFE -; SI: S_ENDPGM +; SI: buffer_load_ubyte +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_u32_zextload_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) nounwind { %load = load i8 addrspace(1)* %in %ext = zext i8 %load to i32 @@ -72,11 +72,11 @@ define void @bfe_u32_zextload_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) n } ; FUNC-LABEL: {{^}}bfe_u32_zext_in_reg_i8: -; SI: BUFFER_LOAD_DWORD -; SI: V_ADD_I32 -; SI-NEXT: V_AND_B32_e32 -; SI-NOT: BFE -; SI: S_ENDPGM +; SI: buffer_load_dword +; SI: v_add_i32 +; SI-NEXT: v_and_b32_e32 +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_u32_zext_in_reg_i8(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %load = load i32 addrspace(1)* %in, align 4 %add = add i32 %load, 1 @@ -87,11 +87,11 @@ define void @bfe_u32_zext_in_reg_i8(i32 addrspace(1)* %out, i32 addrspace(1)* %i } ; FUNC-LABEL: {{^}}bfe_u32_zext_in_reg_i16: -; SI: BUFFER_LOAD_DWORD -; SI: V_ADD_I32 -; SI-NEXT: V_AND_B32_e32 -; SI-NOT: BFE -; SI: S_ENDPGM +; SI: buffer_load_dword +; SI: v_add_i32 +; SI-NEXT: v_and_b32_e32 +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_u32_zext_in_reg_i16(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %load = load i32 addrspace(1)* %in, align 4 %add = add i32 %load, 1 @@ -102,10 +102,10 @@ define void @bfe_u32_zext_in_reg_i16(i32 addrspace(1)* %out, i32 addrspace(1)* % } ; FUNC-LABEL: {{^}}bfe_u32_zext_in_reg_i8_offset_1: -; SI: BUFFER_LOAD_DWORD -; SI: V_ADD_I32 -; SI: BFE -; SI: S_ENDPGM +; SI: buffer_load_dword +; SI: v_add_i32 +; SI: bfe +; SI: s_endpgm define void @bfe_u32_zext_in_reg_i8_offset_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %load = load i32 addrspace(1)* %in, align 4 %add = add i32 %load, 1 @@ -116,11 +116,11 @@ define void @bfe_u32_zext_in_reg_i8_offset_1(i32 addrspace(1)* %out, i32 addrspa } ; FUNC-LABEL: {{^}}bfe_u32_zext_in_reg_i8_offset_3: -; SI: BUFFER_LOAD_DWORD -; SI: V_ADD_I32 -; SI-NEXT: V_AND_B32_e32 {{v[0-9]+}}, 0xf8 -; SI-NEXT: BFE -; SI: S_ENDPGM +; SI: buffer_load_dword +; SI: v_add_i32 +; SI-NEXT: v_and_b32_e32 {{v[0-9]+}}, 0xf8 +; SI-NEXT: bfe +; SI: s_endpgm define void @bfe_u32_zext_in_reg_i8_offset_3(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %load = load i32 addrspace(1)* %in, align 4 %add = add i32 %load, 1 @@ -131,11 +131,11 @@ define void @bfe_u32_zext_in_reg_i8_offset_3(i32 addrspace(1)* %out, i32 addrspa } ; FUNC-LABEL: {{^}}bfe_u32_zext_in_reg_i8_offset_7: -; SI: BUFFER_LOAD_DWORD -; SI: V_ADD_I32 -; SI-NEXT: V_AND_B32_e32 {{v[0-9]+}}, 0x80 -; SI-NEXT: BFE -; SI: S_ENDPGM +; SI: buffer_load_dword +; SI: v_add_i32 +; SI-NEXT: v_and_b32_e32 {{v[0-9]+}}, 0x80 +; SI-NEXT: bfe +; SI: s_endpgm define void @bfe_u32_zext_in_reg_i8_offset_7(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %load = load i32 addrspace(1)* %in, align 4 %add = add i32 %load, 1 @@ -146,10 +146,10 @@ define void @bfe_u32_zext_in_reg_i8_offset_7(i32 addrspace(1)* %out, i32 addrspa } ; FUNC-LABEL: {{^}}bfe_u32_zext_in_reg_i16_offset_8: -; SI: BUFFER_LOAD_DWORD -; SI: V_ADD_I32 -; SI-NEXT: BFE -; SI: S_ENDPGM +; SI: buffer_load_dword +; SI: v_add_i32 +; SI-NEXT: bfe +; SI: s_endpgm define void @bfe_u32_zext_in_reg_i16_offset_8(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %load = load i32 addrspace(1)* %in, align 4 %add = add i32 %load, 1 @@ -160,9 +160,9 @@ define void @bfe_u32_zext_in_reg_i16_offset_8(i32 addrspace(1)* %out, i32 addrsp } ; FUNC-LABEL: {{^}}bfe_u32_test_1: -; SI: BUFFER_LOAD_DWORD -; SI: V_AND_B32_e32 {{v[0-9]+}}, 1, {{v[0-9]+}} -; SI: S_ENDPGM +; SI: buffer_load_dword +; SI: v_and_b32_e32 {{v[0-9]+}}, 1, {{v[0-9]+}} +; SI: s_endpgm ; EG: AND_INT T{{[0-9]\.[XYZW]}}, T{{[0-9]\.[XYZW]}}, 1, define void @bfe_u32_test_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 @@ -188,12 +188,12 @@ define void @bfe_u32_test_3(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounw } ; FUNC-LABEL: {{^}}bfe_u32_test_4: -; SI-NOT: LSHL -; SI-NOT: SHR -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: lshl +; SI-NOT: shr +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm define void @bfe_u32_test_4(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %shl = shl i32 %x, 31 @@ -204,11 +204,11 @@ define void @bfe_u32_test_4(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounw } ; FUNC-LABEL: {{^}}bfe_u32_test_5: -; SI: BUFFER_LOAD_DWORD -; SI-NOT: LSHL -; SI-NOT: SHR -; SI: V_BFE_I32 {{v[0-9]+}}, {{v[0-9]+}}, 0, 1 -; SI: S_ENDPGM +; SI: buffer_load_dword +; SI-NOT: lshl +; SI-NOT: shr +; SI: v_bfe_i32 {{v[0-9]+}}, {{v[0-9]+}}, 0, 1 +; SI: s_endpgm define void @bfe_u32_test_5(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %shl = shl i32 %x, 31 @@ -219,9 +219,9 @@ define void @bfe_u32_test_5(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounw } ; FUNC-LABEL: {{^}}bfe_u32_test_6: -; SI: V_LSHLREV_B32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}} -; SI: V_LSHRREV_B32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}} -; SI: S_ENDPGM +; SI: v_lshlrev_b32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}} +; SI: v_lshrrev_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}} +; SI: s_endpgm define void @bfe_u32_test_6(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %shl = shl i32 %x, 31 @@ -231,9 +231,9 @@ define void @bfe_u32_test_6(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounw } ; FUNC-LABEL: {{^}}bfe_u32_test_7: -; SI: V_LSHLREV_B32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}} -; SI-NOT: BFE -; SI: S_ENDPGM +; SI: v_lshlrev_b32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}} +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_u32_test_7(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %shl = shl i32 %x, 31 @@ -243,10 +243,10 @@ define void @bfe_u32_test_7(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounw } ; FUNC-LABEL: {{^}}bfe_u32_test_8: -; SI-NOT: BFE -; SI: V_AND_B32_e32 {{v[0-9]+}}, 1, {{v[0-9]+}} -; SI-NOT: BFE -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_and_b32_e32 {{v[0-9]+}}, 1, {{v[0-9]+}} +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_u32_test_8(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %shl = shl i32 %x, 31 @@ -256,10 +256,10 @@ define void @bfe_u32_test_8(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounw } ; FUNC-LABEL: {{^}}bfe_u32_test_9: -; SI-NOT: BFE -; SI: V_LSHRREV_B32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}} -; SI-NOT: BFE -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_lshrrev_b32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}} +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_u32_test_9(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %x, i32 31, i32 1) @@ -268,10 +268,10 @@ define void @bfe_u32_test_9(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounw } ; FUNC-LABEL: {{^}}bfe_u32_test_10: -; SI-NOT: BFE -; SI: V_LSHRREV_B32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}} -; SI-NOT: BFE -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_lshrrev_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}} +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_u32_test_10(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %x, i32 1, i32 31) @@ -280,10 +280,10 @@ define void @bfe_u32_test_10(i32 addrspace(1)* %out, i32 addrspace(1)* %in) noun } ; FUNC-LABEL: {{^}}bfe_u32_test_11: -; SI-NOT: BFE -; SI: V_LSHRREV_B32_e32 v{{[0-9]+}}, 8, v{{[0-9]+}} -; SI-NOT: BFE -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_lshrrev_b32_e32 v{{[0-9]+}}, 8, v{{[0-9]+}} +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_u32_test_11(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %x, i32 8, i32 24) @@ -292,10 +292,10 @@ define void @bfe_u32_test_11(i32 addrspace(1)* %out, i32 addrspace(1)* %in) noun } ; FUNC-LABEL: {{^}}bfe_u32_test_12: -; SI-NOT: BFE -; SI: V_LSHRREV_B32_e32 v{{[0-9]+}}, 24, v{{[0-9]+}} -; SI-NOT: BFE -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_lshrrev_b32_e32 v{{[0-9]+}}, 24, v{{[0-9]+}} +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_u32_test_12(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %x, i32 24, i32 8) @@ -305,8 +305,8 @@ define void @bfe_u32_test_12(i32 addrspace(1)* %out, i32 addrspace(1)* %in) noun ; FUNC-LABEL: {{^}}bfe_u32_test_13: ; V_ASHRREV_U32_e32 {{v[0-9]+}}, 31, {{v[0-9]+}} -; SI-NOT: BFE -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_u32_test_13(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %shl = ashr i32 %x, 31 @@ -315,9 +315,9 @@ define void @bfe_u32_test_13(i32 addrspace(1)* %out, i32 addrspace(1)* %in) noun } ; FUNC-LABEL: {{^}}bfe_u32_test_14: -; SI-NOT: LSHR -; SI-NOT: BFE -; SI: S_ENDPGM +; SI-NOT: lshr +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_u32_test_14(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %shl = lshr i32 %x, 31 @@ -326,10 +326,10 @@ define void @bfe_u32_test_14(i32 addrspace(1)* %out, i32 addrspace(1)* %in) noun } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_0: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_constant_fold_test_0(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 0, i32 0, i32 0) nounwind readnone @@ -338,10 +338,10 @@ define void @bfe_u32_constant_fold_test_0(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_1: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_constant_fold_test_1(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 12334, i32 0, i32 0) nounwind readnone @@ -350,10 +350,10 @@ define void @bfe_u32_constant_fold_test_1(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_2: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_constant_fold_test_2(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 0, i32 0, i32 1) nounwind readnone @@ -362,10 +362,10 @@ define void @bfe_u32_constant_fold_test_2(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_3: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 1 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_constant_fold_test_3(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 1, i32 0, i32 1) nounwind readnone @@ -374,10 +374,10 @@ define void @bfe_u32_constant_fold_test_3(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_4: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], -1 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], -1 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_constant_fold_test_4(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 4294967295, i32 0, i32 1) nounwind readnone @@ -386,10 +386,10 @@ define void @bfe_u32_constant_fold_test_4(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_5: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 1 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_constant_fold_test_5(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 128, i32 7, i32 1) nounwind readnone @@ -398,10 +398,10 @@ define void @bfe_u32_constant_fold_test_5(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_6: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0x80 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0x80 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_constant_fold_test_6(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 128, i32 0, i32 8) nounwind readnone @@ -410,10 +410,10 @@ define void @bfe_u32_constant_fold_test_6(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_7: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0x7f -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0x7f +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_constant_fold_test_7(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 127, i32 0, i32 8) nounwind readnone @@ -422,10 +422,10 @@ define void @bfe_u32_constant_fold_test_7(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_8: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 1 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_constant_fold_test_8(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 127, i32 6, i32 8) nounwind readnone @@ -434,10 +434,10 @@ define void @bfe_u32_constant_fold_test_8(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_9: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 1 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFEfppppppppppppp define void @bfe_u32_constant_fold_test_9(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 65536, i32 16, i32 8) nounwind readnone @@ -446,10 +446,10 @@ define void @bfe_u32_constant_fold_test_9(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_10: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_constant_fold_test_10(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 65535, i32 16, i32 16) nounwind readnone @@ -458,10 +458,10 @@ define void @bfe_u32_constant_fold_test_10(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_11: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 10 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 10 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_constant_fold_test_11(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 160, i32 4, i32 4) nounwind readnone @@ -470,10 +470,10 @@ define void @bfe_u32_constant_fold_test_11(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_12: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_constant_fold_test_12(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 160, i32 31, i32 1) nounwind readnone @@ -482,10 +482,10 @@ define void @bfe_u32_constant_fold_test_12(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_13: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 1 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_constant_fold_test_13(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 131070, i32 16, i32 16) nounwind readnone @@ -494,10 +494,10 @@ define void @bfe_u32_constant_fold_test_13(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_14: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 40 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 40 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_constant_fold_test_14(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 160, i32 2, i32 30) nounwind readnone @@ -506,10 +506,10 @@ define void @bfe_u32_constant_fold_test_14(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_15: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 10 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 10 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_constant_fold_test_15(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 160, i32 4, i32 28) nounwind readnone @@ -518,10 +518,10 @@ define void @bfe_u32_constant_fold_test_15(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_16: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0x7f -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0x7f +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_constant_fold_test_16(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 4294967295, i32 1, i32 7) nounwind readnone @@ -530,10 +530,10 @@ define void @bfe_u32_constant_fold_test_16(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_17: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0x7f -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0x7f +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_constant_fold_test_17(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 255, i32 1, i32 31) nounwind readnone @@ -542,10 +542,10 @@ define void @bfe_u32_constant_fold_test_17(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_18: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_constant_fold_test_18(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 255, i32 31, i32 1) nounwind readnone @@ -558,12 +558,12 @@ define void @bfe_u32_constant_fold_test_18(i32 addrspace(1)* %out) nounwind { ; XXX: The operand to v_bfe_u32 could also just directly be the load register. ; FUNC-LABEL: {{^}}simplify_bfe_u32_multi_use_arg: -; SI: BUFFER_LOAD_DWORD [[ARG:v[0-9]+]] -; SI: V_AND_B32_e32 [[AND:v[0-9]+]], 63, [[ARG]] -; SI: V_BFE_U32 [[BFE:v[0-9]+]], [[AND]], 2, 2 -; SI-DAG: BUFFER_STORE_DWORD [[AND]] -; SI-DAG: BUFFER_STORE_DWORD [[BFE]] -; SI: S_ENDPGM +; SI: buffer_load_dword [[ARG:v[0-9]+]] +; SI: v_and_b32_e32 [[AND:v[0-9]+]], 63, [[ARG]] +; SI: v_bfe_u32 [[BFE:v[0-9]+]], [[AND]], 2, 2 +; SI-DAG: buffer_store_dword [[AND]] +; SI-DAG: buffer_store_dword [[BFE]] +; SI: s_endpgm define void @simplify_bfe_u32_multi_use_arg(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 addrspace(1)* %in) nounwind { |