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BranchCommit messageAuthorAge
assembler-pushR600/SI: Initial support for assembler and inline assemblyTom Stellard9 years
hazard-recAMDGPU: Implement SIRegisterInfo::getRegPressureSetScore()Tom Stellard8 years
madkR600/SI: Use v_madmk_f32Matt Arsenault9 years
perf-Jan-08-2015R600: Enable subreg livenessTom Stellard9 years
sched-perf-Mar-27-2015R600/SI: Disable register pressure tracking in the schedulerTom Stellard9 years
smrd-clusterR600/SI: Enable post-ra machine schedulerTom Stellard9 years
struct-divergenceXXX: remove debug prints.Tom Stellard9 years
struct-divergence-v1XXX: Struct fixesTom Stellard8 years
vgpr-spilling-Jan07-2014XXX: Clear some kill flags.Tom Stellard9 years
vinterp-fixR600/SI: Remove some unnecessary patterns from VINTRP multiclassTom Stellard9 years
[...]
 
TagDownloadAuthorAge
mesa-9.1.1commit ce7bbb8b46...Michel Danzer11 years
mesa-9.1commit 16ca877f58...Michel Danzer11 years
 
AgeCommit messageAuthorFilesLines
2014-11-04R600/SI: Change all instruction assembly names to lowercase.si-lowercaseTom Stellard238-5748/+5748
2014-11-04R600/SI: Add an extra check line to make test more strictTom Stellard1-0/+1
2014-11-04[X86] Add 'FeatureSlowSHLD' to cpu 'bdver3'. Also explicit set FeatureAVX and...Andrea Di Biagio1-8/+11
2014-11-04ErrorOr: Be more explicit in the implicit conversion to bool docsJustin Bogner1-3/+3
2014-11-04[PBQP] Callee saved regs should have a higher cost than scratch regsArnaud A. de Grandmaison2-0/+107
2014-11-04[PBQP] Tweak spill costs and coalescing benefitsArnaud A. de Grandmaison4-12/+29
2014-11-04R600/SI: Rename div_scale dest operands to match documentationMatt Arsenault1-2/+2
2014-11-04AArch64: Pattern match integer vector abs like we do on ARM.Benjamin Kramer2-0/+92
2014-11-04[asan] [mips] changed ShadowOffset32 for systems having 16kb PageSize; patch ...Kostya Serebryany1-1/+1
2014-11-04Remove unused DisableRedZone option.Rafael Espindola1-5/+0
[...]
 
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