diff options
Diffstat (limited to 'lib/Target')
-rw-r--r-- | lib/Target/Mips/Mips32r6InstrFormats.td | 41 | ||||
-rw-r--r-- | lib/Target/Mips/Mips32r6InstrInfo.td | 13 | ||||
-rw-r--r-- | lib/Target/Mips/Mips64r6InstrInfo.td | 4 | ||||
-rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 8 | ||||
-rw-r--r-- | lib/Target/Mips/MipsMSAInstrInfo.td | 8 |
5 files changed, 64 insertions, 10 deletions
diff --git a/lib/Target/Mips/Mips32r6InstrFormats.td b/lib/Target/Mips/Mips32r6InstrFormats.td index e3aa920a98a..b1ab7670f3e 100644 --- a/lib/Target/Mips/Mips32r6InstrFormats.td +++ b/lib/Target/Mips/Mips32r6InstrFormats.td @@ -29,6 +29,7 @@ def OPGROUP_DAUI { bits<6> Value = 0b011101; } def OPGROUP_PCREL { bits<6> Value = 0b111011; } def OPGROUP_REGIMM { bits<6> Value = 0b000001; } def OPGROUP_SPECIAL { bits<6> Value = 0b000000; } +def OPGROUP_SPECIAL3 { bits<6> Value = 0b011111; } class OPCODE2<bits<2> Val> { bits<2> Value = Val; @@ -43,6 +44,12 @@ def OPCODE5_AUIPC : OPCODE5<0b11110>; def OPCODE5_DAHI : OPCODE5<0b00110>; def OPCODE5_DATI : OPCODE5<0b11110>; +class OPCODE6<bits<6> Val> { + bits<6> Value = Val; +} +def OPCODE6_ALIGN : OPCODE6<0b100000>; +def OPCODE6_DALIGN : OPCODE6<0b100100>; + class FIELD_FMT<bits<5> Val> { bits<5> Value = Val; } @@ -126,6 +133,40 @@ class SPECIAL_3R_FM<bits<5> mulop, bits<6> funct> : MipsR6Inst { let Inst{5-0} = funct; } +class SPECIAL3_ALIGN_FM<OPCODE6 Operation> : MipsR6Inst { + bits<5> rd; + bits<5> rs; + bits<5> rt; + bits<2> bp; + + bits<32> Inst; + + let Inst{31-26} = OPGROUP_SPECIAL3.Value; + let Inst{25-21} = rs; + let Inst{20-16} = rt; + let Inst{15-11} = rd; + let Inst{10-8} = 0b010; + let Inst{7-6} = bp; + let Inst{5-0} = Operation.Value; +} + +class SPECIAL3_DALIGN_FM<OPCODE6 Operation> : MipsR6Inst { + bits<5> rd; + bits<5> rs; + bits<5> rt; + bits<3> bp; + + bits<32> Inst; + + let Inst{31-26} = OPGROUP_SPECIAL3.Value; + let Inst{25-21} = rs; + let Inst{20-16} = rt; + let Inst{15-11} = rd; + let Inst{10-9} = 0b01; + let Inst{8-6} = bp; + let Inst{5-0} = Operation.Value; +} + class REGIMM_FM<OPCODE5 Operation> : MipsR6Inst { bits<5> rs; bits<16> imm; diff --git a/lib/Target/Mips/Mips32r6InstrInfo.td b/lib/Target/Mips/Mips32r6InstrInfo.td index e4006c0849b..ec1712585f6 100644 --- a/lib/Target/Mips/Mips32r6InstrInfo.td +++ b/lib/Target/Mips/Mips32r6InstrInfo.td @@ -59,6 +59,7 @@ include "Mips32r6InstrFormats.td" //===----------------------------------------------------------------------===// class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>; +class ALIGN_ENC : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>; class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>; class AUI_ENC : AUI_FM; class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>; @@ -88,6 +89,16 @@ class ADDIUPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> { class ADDIUPC_DESC : ADDIUPC_DESC_BASE<"addiupc", GPR32Opnd>; +class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, + Operand ImmOpnd> { + dag OutOperandList = (outs GPROpnd:$rd); + dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp); + string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp"); + list<dag> Pattern = []; +} + +class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2>; + class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> { dag OutOperandList = (outs GPROpnd:$rs); dag InOperandList = (ins simm16:$imm); @@ -149,7 +160,7 @@ class SEL_S_DESC : SEL_DESC_BASE<"sel.s", FGR32Opnd>; //===----------------------------------------------------------------------===// def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6; -def ALIGN; // Known as as BALIGN in DSP ASE +def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6; def ALUIPC : ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6; def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6; def AUIPC : AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6; diff --git a/lib/Target/Mips/Mips64r6InstrInfo.td b/lib/Target/Mips/Mips64r6InstrInfo.td index 6fcc7e2d19e..bc970436f0c 100644 --- a/lib/Target/Mips/Mips64r6InstrInfo.td +++ b/lib/Target/Mips/Mips64r6InstrInfo.td @@ -25,6 +25,7 @@ // //===----------------------------------------------------------------------===// +class DALIGN_ENC : SPECIAL3_DALIGN_FM<OPCODE6_DALIGN>; class DAUI_ENC : DAUI_FM; class DAHI_ENC : REGIMM_FM<OPCODE5_DAHI>; class DATI_ENC : REGIMM_FM<OPCODE5_DATI>; @@ -43,6 +44,7 @@ class DMULU_ENC : SPECIAL_3R_FM<0b00010, 0b111001>; // //===----------------------------------------------------------------------===// +class DALIGN_DESC : ALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3>; class DAHI_DESC : AUI_DESC_BASE<"dahi", GPR64Opnd>; class DATI_DESC : AUI_DESC_BASE<"dati", GPR64Opnd>; class DAUI_DESC : AUI_DESC_BASE<"daui", GPR64Opnd>; @@ -62,7 +64,7 @@ class DMULU_DESC : MUL_R6_DESC_BASE<"dmulu", GPR64Opnd>; //===----------------------------------------------------------------------===// def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6; -def DALIGN; +def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6; def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6; def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6; def DBITSWAP; diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index b63c5cf2250..ee7594f61dc 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -340,6 +340,14 @@ def uimmz : Operand<i32> { } // Unsigned Operand +def uimm2 : Operand<i32> { + let PrintMethod = "printUnsignedImm"; +} + +def uimm3 : Operand<i32> { + let PrintMethod = "printUnsignedImm"; +} + def uimm5 : Operand<i32> { let PrintMethod = "printUnsignedImm"; } diff --git a/lib/Target/Mips/MipsMSAInstrInfo.td b/lib/Target/Mips/MipsMSAInstrInfo.td index a35a16e1d34..285bb146cdb 100644 --- a/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/lib/Target/Mips/MipsMSAInstrInfo.td @@ -65,10 +65,6 @@ def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT", // Operands -def uimm2 : Operand<i32> { - let PrintMethod = "printUnsignedImm"; -} - // The immediate of an LSA instruction needs special handling // as the encoded value should be subtracted by one. def uimm2LSAAsmOperand : AsmOperandClass { @@ -84,10 +80,6 @@ def LSAImm : Operand<i32> { let ParserMatchClass = uimm2LSAAsmOperand; } -def uimm3 : Operand<i32> { - let PrintMethod = "printUnsignedImm8"; -} - def uimm4 : Operand<i32> { let PrintMethod = "printUnsignedImm8"; } |