path: root/lib/Target
AgeCommit message (Expand)AuthorFilesLines
2014-05-16R600/SI: Implement VGPR register spilling v2si-spill-fixes-v4Tom Stellard6-13/+245
2014-05-15[ARM64] Improve diagnostics for Cn operands in SYS instructionsBradley Smith1-69/+24
2014-05-15[X86] Teach the backend how to fold SSE4.1/AVX/AVX2 blend intrinsics.Andrea Di Biagio1-2/+54
2014-05-15[mips][mips64r6] Add CLASS.fmt instructionsZoran Jovanovic1-5/+9
2014-05-15[mips][mips64r6] Add RINT.fmt instructionsZoran Jovanovic2-2/+29
2014-05-15[mips][mips64r6] Add SELEQZ/SELNEZ.fmt instructionsZoran Jovanovic1-4/+21
2014-05-15[mips][mips64r6] Add MAX/MIN/MAXA/MINA.fmt instructionsZoran Jovanovic1-7/+35
2014-05-15R600/SI: Stop using VSrc_* as the default register class for types.Tom Stellard2-63/+11
2014-05-15R600/SI: Fix a bug with handling of INSERT_SUBREG in SIFixSGPRCopiesTom Stellard2-7/+28
2014-05-15R600/SI: Only use SALU instructions for 64-bit add in a block of CF depth 0Tom Stellard1-5/+6
2014-05-15R600/SI: Use VALU instructions for i1 opsTom Stellard2-11/+29
2014-05-15TableGen: use correct MIOperand when printing aliasesTim Northover3-36/+20
2014-05-15[mips][mips64r6] Add bitswap, and dbitswapDaniel Sanders3-4/+32
2014-05-15Instead of littering asserts throughout the code after every call toJay Foad1-2/+0
2014-05-15ARM64: print correct aliases for NEON mov & mvn instructionsTim Northover2-15/+7
2014-05-15[mips][mips64r6] Add align and dalignDaniel Sanders5-10/+64
2014-05-15TableGen/ARM64: print aliases even if they have syntax variants.Tim Northover5-40/+47
2014-05-15ARM64: add correct vector registers during asm parsingTim Northover2-5/+23
2014-05-15[ARM64] Improve load/store diagnostics and forbid 32-bit register addressesBradley Smith1-2/+11
2014-05-15[ARM64] Parse fixed vector lanes properly so that diagnostics can be emittedBradley Smith3-81/+92
2014-05-15[ARM64] Add/Fixup diagnostics for floating point immediatesBradley Smith2-3/+18
2014-05-15[ARM64] Add condition code operand type such that proper diagnostics can be e...Bradley Smith4-32/+62
2014-05-15[ARM64] Add more simple diagnostics for immediate/shift rangesBradley Smith2-10/+25
2014-05-15[mips][mips64r6] Add addiupc, aluipc, and auipcDaniel Sanders7-4/+93
2014-05-15[mips][mips64r6] Add aui, daui, dahi, and datiDaniel Sanders3-5/+59
2014-05-15[mips][mips64r6] Test that branch likelies are not accepted on MIPS64r6.Daniel Sanders1-2/+0
2014-05-15Fix some dyslexia in an assert messageJonathan Roelofs1-2/+2
2014-05-15Fix typosAlp Toker2-3/+3
2014-05-15[ARM64] Support aggressive fastcc/tailcallopt breaking ABI by popping out arg...Jiangning Liu5-101/+377
2014-05-15Move the TargetMachine MC options to MCTargetOptions. No functionalEric Christopher1-4/+0
2014-05-14Rename ComputeMaskedBits to computeKnownBits. "Masked" has beenJay Foad20-106/+106
2014-05-14ARM-BE: test files for vector argument passingChristian Pirker1-1/+2
2014-05-14[ARM64-BE] Fix byte order of CIE and FDE frames for exception handlingChristian Pirker1-0/+17
2014-05-14X86: If we have an instruction that sets a flag and a zero test on the input ...Benjamin Kramer1-3/+63
2014-05-14[mips][mips64r6] Add sel.s and sel.dDaniel Sanders2-4/+52
2014-05-14ARM64: remove unneeded InstPrinter hacksTim Northover1-32/+0
2014-05-14ARM: implement support for the UDF mnemonicSaleem Abdulrasool4-2/+37
2014-05-14Fix typo in function name.Eric Christopher1-5/+5
2014-05-13R600/SI: Try to fix BFE operands when moving to VALUMatt Arsenault1-1/+1
2014-05-13Save the optimization level the subtarget was created with in aEric Christopher2-15/+14
2014-05-13ARMEB: Fix byte order of EH frame unwinding instructions, with modified test ...Christian Pirker1-4/+14
2014-05-13Revert "ARMEB: Fix byte order of EH frame unwinding instructions"Rafael Espindola1-14/+4
2014-05-13[mips] Marked up instructions added in MIPS32r2 and tested that IAS for -mcpu...Daniel Sanders7-21/+35
2014-05-13ARMEB: Fix byte order of EH frame unwinding instructionsChristian Pirker1-4/+14
2014-05-13[mips] Free up two values in SubtargetFeatureFlag by folding the redundant Is...Daniel Sanders2-6/+5
2014-05-13[un]wrap extracted from lib/Target/Target[MachineC].cpp, lib/ExecutionEngine/...Artyom Skrobov2-25/+0
2014-05-13[ARM64] Fix the misleading diagnostic on bad extend amount of reg+reg address...Kevin Qin2-11/+8
2014-05-13Folding into CSEL when there is ZEXT between SETCC and ADDWeiming Zhao1-3/+11
2014-05-12Try to fix an SDAG dependence issue with sretReid Kleckner2-18/+23
2014-05-12Use cast<> for unchecked useMatt Arsenault1-1/+1