diff options
Diffstat (limited to 'lib/Target/R600/R600InstrInfo.h')
| -rw-r--r-- | lib/Target/R600/R600InstrInfo.h | 32 |
1 files changed, 22 insertions, 10 deletions
diff --git a/lib/Target/R600/R600InstrInfo.h b/lib/Target/R600/R600InstrInfo.h index a6add8382cf..1ba4160747b 100644 --- a/lib/Target/R600/R600InstrInfo.h +++ b/lib/Target/R600/R600InstrInfo.h @@ -84,26 +84,38 @@ namespace llvm { SmallVector<std::pair<MachineOperand *, int64_t>, 3> getSrcs(MachineInstr *MI) const; - bool isLegal( - const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs, - const std::vector<R600InstrInfo::BankSwizzle> &Swz, - unsigned CheckedSize) const; - bool recursiveFitsFPLimitation( - const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs, - std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, - unsigned Depth = 0) const; + unsigned isLegalUpTo( + const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs, + const std::vector<R600InstrInfo::BankSwizzle> &Swz, + const std::vector<std::pair<int, unsigned> > &TransSrcs, + R600InstrInfo::BankSwizzle TransSwz) const; + + bool FindSwizzleForVectorSlot( + const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs, + std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, + const std::vector<std::pair<int, unsigned> > &TransSrcs, + R600InstrInfo::BankSwizzle TransSwz) const; /// Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 /// returns true and the first (in lexical order) BankSwizzle affectation /// starting from the one already provided in the Instruction Group MIs that /// fits Read Port limitations in BS if available. Otherwise returns false /// and undefined content in BS. + /// isLastAluTrans should be set if the last Alu of MIs will be executed on + /// Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to + /// apply to the last instruction. /// PV holds GPR to PV registers in the Instruction Group MIs. bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs, const DenseMap<unsigned, unsigned> &PV, - std::vector<BankSwizzle> &BS) const; + std::vector<BankSwizzle> &BS, + bool isLastAluTrans) const; + + /// An instruction group can only access 2 channel pair (either [XY] or [ZW]) + /// from KCache bank on R700+. This function check if MI set in input meet + /// this limitations + bool fitsConstReadLimitations(const std::vector<MachineInstr *> &) const; + /// Same but using const index set instead of MI set. bool fitsConstReadLimitations(const std::vector<unsigned>&) const; - bool canBundle(const std::vector<MachineInstr *> &) const; /// \breif Vector instructions are instructions that must fill all /// instruction slots within an instruction group. |