diff options
author | Kevin Qin <Kevin.Qin@arm.com> | 2014-05-13 07:35:12 +0000 |
---|---|---|
committer | Kevin Qin <Kevin.Qin@arm.com> | 2014-05-13 07:35:12 +0000 |
commit | 2a74dfe388f8c1bedb32b3664c7b288fcc335833 (patch) | |
tree | 2203b89d815cf82383a8c4ec35a1803036135d35 /lib/Target | |
parent | 51a167d6c4612d82a43227c293e287a9f5108591 (diff) |
[ARM64] Fix the misleading diagnostic on bad extend amount of reg+reg addressing mode.
A vague diagnostic replaced the misleading one.
This can fix bug 19502.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208669 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r-- | lib/Target/ARM64/ARM64InstrFormats.td | 1 | ||||
-rw-r--r-- | lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp | 18 |
2 files changed, 8 insertions, 11 deletions
diff --git a/lib/Target/ARM64/ARM64InstrFormats.td b/lib/Target/ARM64/ARM64InstrFormats.td index 431cd082e2e..3f88b8253fa 100644 --- a/lib/Target/ARM64/ARM64InstrFormats.td +++ b/lib/Target/ARM64/ARM64InstrFormats.td @@ -2251,6 +2251,7 @@ class PrefetchLiteral<bits<2> opc, bit V, string asm, list<dag> pat> class MemROAsmOperand<int sz> : AsmOperandClass { let Name = "MemoryRegisterOffset"#sz; + let DiagnosticType = "InvalidMemoryIndexed"; } def MemROAsmOperand8 : MemROAsmOperand<8>; diff --git a/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp b/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp index c54a49b6e25..99c6a13876f 100644 --- a/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp +++ b/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp @@ -3699,6 +3699,8 @@ bool ARM64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode) { return Error(Loc, "index must be a multiple of 8 in range [-512, 504]."); case Match_InvalidMemoryIndexed128SImm7: return Error(Loc, "index must be a multiple of 16 in range [-1024, 1008]."); + case Match_InvalidMemoryIndexed: + return Error(Loc, "invalid offset in memory address."); case Match_InvalidMemoryIndexed8: return Error(Loc, "index must be an integer in range [0, 4095]."); case Match_InvalidMemoryIndexed16: @@ -4114,17 +4116,11 @@ bool ARM64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, if (Operands.size() == ErrorInfo + 1 && !((ARM64Operand *)Operands[ErrorInfo])->isImm() && !Tok.startswith("stur") && !Tok.startswith("ldur")) { - // whether we want an Indexed64 or Indexed32 diagnostic depends on - // the register class of the previous operand. Default to 64 in case - // we see something unexpected. - MatchResult = Match_InvalidMemoryIndexed64; - if (ErrorInfo) { - ARM64Operand *PrevOp = (ARM64Operand *)Operands[ErrorInfo - 1]; - if (PrevOp->isReg() && - ARM64MCRegisterClasses[ARM64::GPR32RegClassID].contains( - PrevOp->getReg())) - MatchResult = Match_InvalidMemoryIndexed32; - } + // FIXME: Here we use a vague diagnostic for memory operand in many + // instructions of various formats. This diagnostic can be more accurate + // if splitting memory operand into many smaller operands to help + // diagnose. + MatchResult = Match_InvalidMemoryIndexed; } SMLoc ErrorLoc = ((ARM64Operand *)Operands[ErrorInfo])->getStartLoc(); if (ErrorLoc == SMLoc()) |