diff options
| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-12-11 22:15:35 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-12-11 22:15:35 +0000 |
| commit | 8651adfe4f98502eb5187acd0a19be03450d1437 (patch) | |
| tree | 90176c67610df5220980b72b93ddbbf804cdf4f2 /lib/Target/R600/SIISelLowering.cpp | |
| parent | 05e5839d4f31851387989cc9a182f9d19f02df25 (diff) | |
R600/SI: Use unordered not equal instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224065 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/SIISelLowering.cpp')
| -rw-r--r-- | lib/Target/R600/SIISelLowering.cpp | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp index 132aa284a3b..03068462290 100644 --- a/lib/Target/R600/SIISelLowering.cpp +++ b/lib/Target/R600/SIISelLowering.cpp @@ -62,14 +62,12 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) : computeRegisterProperties(); // Condition Codes - setCondCodeAction(ISD::SETONE, MVT::f32, Expand); setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand); setCondCodeAction(ISD::SETUGE, MVT::f32, Expand); setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); setCondCodeAction(ISD::SETULE, MVT::f32, Expand); setCondCodeAction(ISD::SETULT, MVT::f32, Expand); - setCondCodeAction(ISD::SETONE, MVT::f64, Expand); setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand); setCondCodeAction(ISD::SETUGE, MVT::f64, Expand); setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); |