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authorVincent Lejeune <vljn@ovi.com>2013-02-14 16:55:11 +0000
committerVincent Lejeune <vljn@ovi.com>2013-02-14 16:55:11 +0000
commitf846add9adf0752e552cb98fd0ba5dae791e4c3b (patch)
tree97ea8e8955c366b0d900b48c82084b5e4d341c04 /lib/Target/R600/R600Instructions.td
parentabfd5f6154b10cc5801bc9e1b8e8221df0113c68 (diff)
R600: Export instructions are no longer terminator
This allows MachineInstScheduler to reorder them, and thus make scheduling more efficient. Reviewed-by: Tom Stellard <thomas.stellard at amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175182 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/R600Instructions.td')
-rw-r--r--lib/Target/R600/R600Instructions.td4
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/R600/R600Instructions.td b/lib/Target/R600/R600Instructions.td
index 286ec9be90b..e495beac3e9 100644
--- a/lib/Target/R600/R600Instructions.td
+++ b/lib/Target/R600/R600Instructions.td
@@ -644,7 +644,7 @@ multiclass SteamOutputExportPattern<Instruction ExportInst,
4095, imm:$mask, buf3inst, 0)>;
}
-let isTerminator = 1, usesCustomInserter = 1 in {
+let usesCustomInserter = 1 in {
class ExportSwzInst : InstR600ISA<(
outs),
@@ -658,7 +658,7 @@ class ExportSwzInst : InstR600ISA<(
let Inst{63-32} = Word1;
}
-} // End isTerminator = 1, usesCustomInserter = 1
+} // End usesCustomInserter = 1
class ExportBufInst : InstR600ISA<(
outs),