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path: root/lib/Target/R600/R600Instructions.td
AgeCommit message (Expand)AuthorFilesLines
2013-06-07XXX: Use correct encoding for Vertex Fetch instructions on Cayman.cayman-only-bfgminerTom Stellard1-137/+255
2013-06-07R600: Use EXPORT_RAT_INST_STORE_DWORD for stores on CaymanTom Stellard1-37/+56
2013-06-07R600: Factor the instruction encoding out the RAT_WRITE_CACHELESS_eg classTom Stellard1-50/+23
2013-06-07R600: Move instruction encoding definitions into a separate .td fileTom Stellard1-362/+1
2013-06-03R600: Constraints input regs of interp_xy,_zwVincent Lejeune1-2/+2
2013-05-20R600: Swap the legality of rotl and rotrTom Stellard1-4/+2
2013-05-17R600: Relax some vector constraints on Dot4.Vincent Lejeune1-10/+49
2013-05-17R600: Improve texture handlingVincent Lejeune1-110/+86
2013-05-17R600: Rename 128 bit registers.Vincent Lejeune1-9/+8
2013-05-17R600: prettier dump of clampVincent Lejeune1-3/+3
2013-05-10R600: Remove AMDILPeeopholeOptimizer and replace optimizations with tablegen ...Tom Stellard1-0/+1
2013-05-03R600: BFI_INT is a vector-only instructionTom Stellard1-1/+1
2013-05-03R600: Add pattern for SHA-256 Ma functionTom Stellard1-0/+3
2013-05-02R600: Improve asmPrint of ALU clauseVincent Lejeune1-4/+7
2013-05-02R600: Prettier asmPrint of AluVincent Lejeune1-7/+8
2013-05-02R600: Use new tablegen syntax for patternsTom Stellard1-172/+129
2013-04-30R600: use native for aluVincent Lejeune1-0/+17
2013-04-30R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chipsVincent Lejeune1-15/+66
2013-04-30R600: Add a Bank Swizzle operandVincent Lejeune1-4/+10
2013-04-30R600: Turn TEX/VTX into native instructionsVincent Lejeune1-0/+8
2013-04-30R600: Add FetchInst bit to instruction defs to denote vertex/tex instructionsVincent Lejeune1-3/+15
2013-04-30R600: Clean up instruction class definitionsVincent Lejeune1-23/+14
2013-04-29R600: Fix encoding of CF_END_{EG, R600} instructionsTom Stellard1-0/+1
2013-04-23R600: Use .AMDGPU.config section to emit stacksizeVincent Lejeune1-7/+0
2013-04-23R600: Add CF_ENDVincent Lejeune1-1/+23
2013-04-19R600: Add pattern for the BFI_INT instructionTom Stellard1-0/+3
2013-04-17R600: Make Export Instruction not duplicableVincent Lejeune1-1/+3
2013-04-17R600: Export is emitted as a CF_NATIVE instVincent Lejeune1-4/+4
2013-04-10R600/SI: Add pattern for AMDGPUurecipMichel Danzer1-1/+2
2013-04-08R600: Control Flow support for pre EG genVincent Lejeune1-50/+148
2013-04-01R600: Add support for native control flowVincent Lejeune1-0/+100
2013-04-01R600: Emit CF_ALU and use true kcache register.Vincent Lejeune1-9/+70
2013-03-31R600: Emit native instructions for texVincent Lejeune1-17/+125
2013-03-22R600: Use legacy (0 * anything = 0) MUL instructions for pow intrinsicsMichel Danzer1-1/+4
2013-03-18R600/SI: add float vector typesChristian Konig1-2/+2
2013-03-11R600: Fix JUMP handling so that MachineInstr verification can occurVincent Lejeune1-7/+16
2013-03-08R600: Improve custom lowering of select_ccTom Stellard1-0/+12
2013-03-05R600: Remove LowerConstCopyPass and lower CONST_COPY right after ISel.Vincent Lejeune1-3/+4
2013-03-05R600: CONST_ADDRESS node is not marked as mayLoad anymoreVincent Lejeune1-1/+1
2013-03-05R600: Use MUL_IEEE for trig/fdiv intrinsicVincent Lejeune1-4/+4
2013-03-05R600: Add support for indirect addressing of non default const bufferVincent Lejeune1-5/+4
2013-02-21R600: Fix for Unigine when MachineSched is enabledTom Stellard1-0/+1
2013-02-18R600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for mad patternVincent Lejeune1-1/+8
2013-02-18R600: Support for TBOVincent Lejeune1-0/+54
2013-02-14R600: Export instructions are no longer terminatorVincent Lejeune1-2/+2
2013-02-14R600: Fold zero/one in export instructionsVincent Lejeune1-15/+5
2013-02-13R600: Add support for 128-bit parametersTom Stellard1-0/+4
2013-02-12R600: Fix regression with shadow array sampler on pre-SI GPUs.Michel Danzer1-1/+1
2013-02-10Test Commit - Remove some trailing whitespace in R600Instructions.tdVincent Lejeune1-6/+6
2013-02-07R600/SI: Use proper instructions for array/shadow samplers.Tom Stellard1-1/+15
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