diff options
| author | Alexandre Courbot <acourbot@nvidia.com> | 2014-02-28 16:41:58 +0900 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2014-06-03 15:03:57 +0200 |
| commit | fadeeaaba0f0007e29eb247d3ea429f77a99fd6a (patch) | |
| tree | 4f945fa6e5ae017d10ad2ce95f1740a60f2e0b87 /drivers | |
| parent | d9b0455af633e69dee6dac10c60eb6172b452b1b (diff) | |
[HACK] drm/nouveau/graph: do not write reg 0x260
What is it for anyway?
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c | 4 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c | 10 |
2 files changed, 7 insertions, 7 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c index c5b24923858..f722089945d 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c @@ -957,7 +957,7 @@ nve4_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; int i; - nv_mask(priv, 0x000260, 0x00000001, 0x00000000); + //nv_mask(priv, 0x000260, 0x00000001, 0x00000000); nvc0_graph_mmio(priv, oclass->hub); nvc0_graph_mmio(priv, oclass->gpc); @@ -991,7 +991,7 @@ nve4_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) nvc0_graph_icmd(priv, oclass->icmd); nv_wr32(priv, 0x404154, 0x00000400); nvc0_graph_mthd(priv, oclass->mthd); - nv_mask(priv, 0x000260, 0x00000001, 0x00000001); + //nv_mask(priv, 0x000260, 0x00000001, 0x00000001); nv_mask(priv, 0x418800, 0x00200000, 0x00200000); nv_mask(priv, 0x41be10, 0x00800000, 0x00800000); diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c index bf7bdb1f291..7a6cd1e2f29 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c @@ -946,17 +946,17 @@ nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv) { struct nvc0_graph_oclass *oclass = (void *)nv_object(priv)->oclass; struct nvc0_grctx_oclass *cclass = (void *)nv_engine(priv)->cclass; - u32 r000260; + //u32 r000260; int i; if (priv->firmware) { /* load fuc microcode */ - r000260 = nv_mask(priv, 0x000260, 0x00000001, 0x00000000); + //r000260 = nv_mask(priv, 0x000260, 0x00000001, 0x00000000); nvc0_graph_init_fw(priv, 0x409000, &priv->fuc409c, &priv->fuc409d); nvc0_graph_init_fw(priv, 0x41a000, &priv->fuc41ac, &priv->fuc41ad); - nv_wr32(priv, 0x000260, r000260); + //nv_wr32(priv, 0x000260, r000260); /* start both of them running */ nv_wr32(priv, 0x409840, 0xffffffff); @@ -1043,7 +1043,7 @@ nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv) } /* load HUB microcode */ - r000260 = nv_mask(priv, 0x000260, 0x00000001, 0x00000000); + //r000260 = nv_mask(priv, 0x000260, 0x00000001, 0x00000000); nv_wr32(priv, 0x4091c0, 0x01000000); for (i = 0; i < oclass->fecs.ucode->data.size / 4; i++) nv_wr32(priv, 0x4091c4, oclass->fecs.ucode->data.data[i]); @@ -1066,7 +1066,7 @@ nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x41a188, i >> 6); nv_wr32(priv, 0x41a184, oclass->gpccs.ucode->code.data[i]); } - nv_wr32(priv, 0x000260, r000260); + //nv_wr32(priv, 0x000260, r000260); /* load register lists */ nvc0_graph_init_csdata(priv, cclass->hub, 0x409000, 0x000, 0x000000); |