diff options
| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-05-30 17:26:57 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-05-31 12:59:03 +0200 |
| commit | 01cbc720105b30a7a4b3e125521c2798cf3984b3 (patch) | |
| tree | 262931aabd00abadb5eed7b4151abb9b799ef56c | |
| parent | 3c5e346c7e1954f3a7e7ceb41f8672083aaef119 (diff) | |
drm/i915: only set the sdvo/hdmi pixel multiplier when the pll is upcea-double-clocked
Bspec isn't too clear about this, but it sounds like we should only
set this once the pll is fully up and stable, and we should start the
pll with a pixel multiplier of 1.
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 16 |
1 files changed, 7 insertions, 9 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 914789420906..2d3e32046cf9 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4520,13 +4520,10 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, dpll |= DPLLB_MODE_LVDS; else dpll |= DPLLB_MODE_DAC_SERIAL; - if (is_sdvo) { - int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); - if (pixel_multiplier > 1) { - dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; - } + + if (is_sdvo) dpll |= DPLL_DVO_HIGH_SPEED; - } + if (is_dp && !is_cpu_edp) dpll |= DPLL_DVO_HIGH_SPEED; @@ -4651,10 +4648,11 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, /* The pixel multiplier can only be updated once the * DPLL is enabled and the clocks are stable. - * - * So write it again. */ - I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll); + if (pixel_multiplier > 1) { + dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; + I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll); + } } intel_crtc->lowfreq_avail = false; |