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path: root/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
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2015-12-21Teach ARMLoadStoreOptimizer to ignore DBG_VALUE instructions when mergingAdrian Prantl1-1/+5
instructions. As noted in PR24563. rdar://problem/23963293 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256183 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-21ARMLoadStoreOptimizer: Cleanup isMemoryOp(); NFCMatthias Braun1-33/+33
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253757 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-19ARM: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith1-3/+2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250759 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-01[ARM] More care with Thumb1 writeback in ARMLoadStoreOptimizerScott Douglass1-3/+7
Differential Revision: http://reviews.llvm.org/D13240 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249002 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-16[ARM] Register ARMPreAllocLoadStoreOpt pass with LLVM pass manager.Chad Rosier1-2/+14
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247791 91177308-0d34-0410-b5e6-96231b3b80d8
2015-08-07[ARM] Remove an unused reference to MachineRegisterInfo. NFC.Chad Rosier1-2/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244334 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-23[ARM] Register (existing) ARMLoadStoreOpt pass with LLVM pass manager.David Gross1-2/+12
Summary: Among other things, this allows -print-after-all/-print-before-all to dump IR around this pass. Subscribers: aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D11373 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243052 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-23Test commit.David Gross1-0/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243046 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-21ARMLoadStoreOpt: Merge subs/adds into LDRD/STRD; Factor out common codeMatthias Braun1-166/+186
Re-apply of r241928 which had to be reverted because of the r241926 revert. This commit factors out common code from MergeBaseUpdateLoadStore() and MergeBaseUpdateLSMultiple() and introduces a new function MergeBaseUpdateLSDouble() which merges adds/subs preceding/following a strd/ldrd instruction into an strd/ldrd instruction with writeback where possible. Differential Revision: http://reviews.llvm.org/D10676 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242743 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-21ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2Matthias Braun1-31/+102
Re-apply r241926 with an additional check that r13 and r15 are not used for LDRD/STRD. See http://llvm.org/PR24190. This also already includes the fix from r241951. Differential Revision: http://reviews.llvm.org/D10623 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242742 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-20Revert "ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2"Matthias Braun1-96/+29
This reverts commit r241926. This caused http://llvm.org/PR24190 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242735 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-20Revert "ARMLoadStoreOpt: Merge subs/adds into LDRD/STRD; Factor out common code"Matthias Braun1-186/+166
This reverts commit r241928. This caused http://llvm.org/PR24190 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242734 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-20Revert "ARM: Use SpecificBumpPtrAllocator to fix leak introduced in r241920"Matthias Braun1-3/+3
This reverts commit r241951. It caused http://llvm.org/PR24190 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242733 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-16Move most user of TargetMachine::getDataLayout to the Module oneMehdi Amini1-1/+1
Summary: This change is part of a series of commits dedicated to have a single DataLayout during compilation by using always the one owned by the module. This patch is quite boring overall, except for some uglyness in ASMPrinter which has a getDataLayout function but has some clients that use it without a Module (llmv-dsymutil, llvm-dwarfdump), so some methods are taking a DataLayout as parameter. Reviewers: echristo Subscribers: yaron.keren, rafael, llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D11090 From: Mehdi Amini <mehdi.amini@apple.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242386 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-16Clear kill flags in ARMLoadStoreOptimizer.Pete Cooper1-1/+3
The pass here was clearing kill flags on instructions which had their sources killed in the instruction being combined. But given that the new instruction is inserted after the existing ones, any existing instructions with kill flags will lead to the verifier complaining that we are reading an undefined physreg. For example, what we had prior to this optimization is t2STRi12 %R1, %SP, 12 t2STRi12 %R1<kill>, %SP, 16 t2STRi12 %R0<kill>, %SP, 8 and prior to this fix that would generate t2STRi12 %R1<kill>, %SP, 16 t2STRDi8 %R0<kill>, %R1, %SP, 8 This is clearly incorrect as it didn't clear the kill flag on R1 used with offset 16 because there was no kill flag on the instruction with offset 12. After this change we clear the kill flag on the offset 16 instruction because we know it will be used afterwards in the new instruction. I haven't provided a test case. I have a small test, but even it is very sensitive to register allocation order which isn't ideal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242359 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-13Removing several -Wunused-but-set-variable warnings; NFC intended.Aaron Ballman1-26/+0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242028 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10ARM: Use SpecificBumpPtrAllocator to fix leak introduced in r241920Matthias Braun1-3/+3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241951 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10ARMLoadStoreOpt: Merge subs/adds into LDRD/STRD; Factor out common codeMatthias Braun1-166/+186
This commit factors out common code from MergeBaseUpdateLoadStore() and MergeBaseUpdateLSMultiple() and introduces a new function MergeBaseUpdateLSDouble() which merges adds/subs preceding/following a strd/ldrd instruction into an strd/ldrd instruction with writeback where possible. Differential Revision: http://reviews.llvm.org/D10676 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241928 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2Matthias Braun1-29/+96
Differential Revision: http://reviews.llvm.org/D10623 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241926 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10ARMLoadStoreOptimizer: Rewrite LDM/STM matching logic.Matthias Braun1-551/+481
This improves the logic in several ways and is a preparation for followup patches: - First perform an analysis and create a list of merge candidates, then transform. This simplifies the code in that you have don't have to care to much anymore that you may be holding iterators to MachineInstrs that get removed. - Analyze/Transform basic blocks in reverse order. This allows to use LivePhysRegs to find free registers instead of the RegisterScavenger. The RegisterScavenger will become less precise in the future as it relies on the deprecated kill-flags. - Return the newly created node in MergeOps so there's no need to look around in the schedule to find it. - Rename some MBBI iterators to InsertBefore to make their role clear. - General code cleanup. Differential Revision: http://reviews.llvm.org/D10140 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241920 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29ARM: add correct kill flags when combining stm instructionsTim Northover1-0/+6
When the store sequence being combined actually stores the base register, we should not mark it as killed until the end. rdar://21504262 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241003 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-24ARMLoadStoreOptimizer: Fix errata 602117 handling and make testcase actually ↵Matthias Braun1-107/+112
test for it This fixes PR23912 Differential Revision: http://reviews.llvm.org/D10620 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240582 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-23[ARM] ARMLoadStoreOpt::UpdateBaseRegUses should stop on defJohn Brawn1-1/+1
When UpdateBaseRegUses sees an instruction that defines the base register it must stop, as the base register value it is updating is no longer live. Ideally we would already have seen the register be killed (which is already checked for), but the kill flags may be inaccurate and we have to account for this. Differential Revision: http://reviews.llvm.org/D10566 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240424 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-23Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC)Alexander Kornienko1-2/+2
Apparently, the style needs to be agreed upon first. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240390 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-19Fixed/added namespace ending comments using clang-tidy. NFCAlexander Kornienko1-2/+2
The patch is generated using this command: tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py -fix \ -checks=-*,llvm-namespace-comment -header-filter='llvm/.*|clang/.*' \ llvm/lib/ Thanks to Eugene Kosov for the original patch! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240137 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-05[ARM] Make helper function static.Benjamin Kramer1-8/+2
This one had a declaration but it differed from the definition so the declaration was actually dead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239157 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-03ARM: Thumb2 LDRD/STRD supports independent input/output regsMatthias Braun1-20/+22
The existing code would unnecessarily break LDRD/STRD apart with non-adjacent registers, on thumb2 this is not necessary. Ideally on thumb2 we shouldn't match for ldrd/strd pre-regalloc anymore as there is not reason to set register hints anymore, changing that is something for a future patch however. Differential Revision: http://reviews.llvm.org/D9694 Recommiting after the revert in r238821, the buildbot still failed with the patch removed so there seems to be another reason for the breakage. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238935 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02Revert "ARM: Thumb2 LDRD/STRD supports independent input/output regs"Renato Golin1-22/+20
This reverts commit r238795, as it broke the Thumb2 self-hosting buildbot. Since self-hosting issues with Clang are hard to investigate, I'm taking the liberty to revert now, so we can investigate it offline. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238821 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-01ARM: Thumb2 LDRD/STRD supports independent input/output regsMatthias Braun1-20/+22
The existing code would unnecessarily break LDRD/STRD apart with non-adjacent registers, on thumb2 this is not necessary. Ideally on thumb2 we shouldn't match for ldrd/strd pre-regalloc anymore as there is not reason to set register hints anymore, changing that is something for a future patch however. Differential Revision: http://reviews.llvm.org/D9694 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238795 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-01ARMLoadStoreOptimizer: Fix doxygen comments; NFCMatthias Braun1-34/+28
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238784 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-29CodeGen: Use mop_iterator instead of MIOperands/ConstMIOperandsMatthias Braun1-3/+3
MIOperands/ConstMIOperands are classes iterating over the MachineOperand of a MachineInstr, however MachineInstr::mop_iterator does the same thing. I assume these two iterators exist to have a uniform interface to iterate over the operands of a machine instruction bundle and a single machine instruction. However in practice I find it more confusing to have 2 different iterator classes, so this patch transforms (nearly all) the code to use mop_iterators. The only exception being MIOperands::anlayzePhysReg() and MIOperands::analyzeVirtReg() still needing an equivalent, I leave that as an exercise for the next patch. Differential Revision: http://reviews.llvm.org/D9932 This version is slightly modified from the proposed revision in that it introduces MachineInstr::getOperandNo to avoid the extra counting variable in the few loops that previously used MIOperands::getOperandNo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238539 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-27ARMLoadStoreOptimizer: Code cleanup; NFCMatthias Braun1-15/+12
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238289 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-18MachineInstr: Change return value of getOpcode() to unsigned.Matthias Braun1-15/+15
This was previously returning int. However there are no negative opcode numbers and more importantly this was needlessly different from MCInstrDesc::getOpcode() (which even is the value returned here) and SDValue::getOpcode()/SDNode::getOpcode(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237611 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-23Re-sort includes with sort-includes.py and insert raw_ostream.h where it's used.Benjamin Kramer1-0/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232998 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-12In preparation for moving ARM's TargetRegisterInfo to the TargetMachineEric Christopher1-1/+1
merge Thumb1RegisterInfo and Thumb2RegisterInfo. This will enable us to match the TargetMachine for our TargetRegisterInfo classes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232117 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-25Improve handling of stack accesses in Thumb-1Renato Golin1-9/+27
Thumb-1 only allows SP-based LDR and STR to be word-sized, and SP-base LDR, STR, and ADD only allow offsets that are a multiple of 4. Make some changes to better make use of these instructions: * Use word loads for anyext byte and halfword loads from the stack. * Enforce 4-byte alignment on objects accessed in this way, to ensure that the offset is valid. * Do the same for objects whose frame index is used, in order to avoid having to use more than one ADD to generate the frame index. * Correct how many bits of offset we think AddrModeT1_s has. Patch by John Brawn. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230496 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-29Migrate ARM except for TTI, AsmPrinter, and frame loweringEric Christopher1-11/+8
away from getSubtargetImpl. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227399 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-26Move DataLayout back to the TargetMachine from TargetSubtargetInfoEric Christopher1-1/+1
derived classes. Since global data alignment, layout, and mangling is often based on the DataLayout, move it to the TargetMachine. This ensures that global data is going to be layed out and mangled consistently if the subtarget changes on a per function basis. Prior to this all targets(*) have had subtarget dependent code moved out and onto the TargetMachine. *One target hasn't been migrated as part of this change: R600. The R600 port has, as a subtarget feature, the size of pointers and this affects global data layout. I've currently hacked in a FIXME to enable progress, but the port needs to be updated to either pass the 64-bitness to the TargetMachine, or fix the DataLayout to avoid subtarget dependent features. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227113 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-21Fix load-store optimizer on thumbv4tJonathan Roelofs1-3/+14
Thumbv4t does not have lo->lo copies other than MOVS, and that can't be predicated. So emit MOVS when needed and bail if there's a predicate. http://reviews.llvm.org/D6592 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226711 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-14Grab the subtarget info off of the MachineFunction rather thanEric Christopher1-1/+1
indirecting through the TargetMachine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219674 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-24[Thumb] Make load/store optimizer less conservative.Moritz Roth1-60/+195
If it's safe to clobber the condition flags, we can do a few extra things: it's then possible to reset the base register writeback using a SUBS, so we can try to merge even if the base register isn't dead after the merged instruction. This is effectively a (heavily bug-fixed) rewrite of r208992. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218386 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-16ARM load/store optimizer: Don't materialize a new base register withMoritz Roth1-4/+15
ADDS/SUBS unless it's safe to clobber the condition flags. If the merged instructions are in a range where the CPSR is live, e.g. between a CMP -> Bcc, we can't safely materialize a new base register. This problem is quite rare, I couldn't come up with a test case and I've never actually seen this happen in the tests I'm running - there is a potential trigger for this in LNT/oggenc (spills being inserted between a CMP/Bcc), but at the moment this isn't being merged. I'll try to reduce that into a small test case once I've committed my upcoming patch to make merging less conservative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217881 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21Thumb1 load/store optimizer: Improve code to materialize new base register.Moritz Roth1-5/+13
There are two add-immediate instructions in Thumb1: tADDi8 and tADDi3. Only the latter supports using different source and destination registers, so whenever we materialize a new base register (at a certain offset) we'd do so by moving the base register value to the new register and then adding in place. This patch changes the code to use a single tADDi3 if the offset is small enough to fit in 3 bits. Differential Revision: http://reviews.llvm.org/D5006 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216193 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21Repace SmallPtrSet with SmallPtrSetImpl in function arguments to avoid ↵Craig Topper1-1/+1
needing to mention the size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216158 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-18Revert "Repace SmallPtrSet with SmallPtrSetImpl in function arguments to ↵Craig Topper1-1/+1
avoid needing to mention the size." Getting a weird buildbot failure that I need to investigate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215870 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-17Repace SmallPtrSet with SmallPtrSetImpl in function arguments to avoid ↵Craig Topper1-1/+1
needing to mention the size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215868 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-15ARM: Fix and re-enable load/store optimizer for Thumb1.Moritz Roth1-111/+8
In a previous iteration of the pass, we would try to compensate for writeback by updating later instructions and/or inserting a SUBS to reset the base register if necessary. Since such a SUBS sets the condition flags it's not generally safe to do this. For now, only merge LDR/STRs if there is no writeback to the base register (LDM that loads into the base register) or the base register is killed by one of the merged instructions. These cases are clear wins both in terms of instruction count and performance. Also add three new test cases, and update the existing ones accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215729 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-15ARM load/store optimizer: Compute BaseKill correctly.Moritz Roth1-5/+11
This adds some code back that was deleted in r92053. The location of the last merged memory operation needs to be kept up-to-date since MemOps may be in a different order to the original instruction stream to allow merging (since registers need to be in ascending order). Also simplify the logic to determine BaseKill using findRegisterUseOperandIdx to use an equivalent function call instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215728 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-05Have MachineFunction cache a pointer to the subtarget to make lookupsEric Christopher1-3/+3
shorter/easier and have the DAG use that to do the same lookup. This can be used in the future for TargetMachine based caching lookups from the MachineFunction easily. Update the MIPS subtarget switching machinery to update this pointer at the same time it runs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214838 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-04Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher1-6/+6
information and update all callers. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214781 91177308-0d34-0410-b5e6-96231b3b80d8
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