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path: root/lib/CodeGen/PostRASchedulerList.cpp
AgeCommit message (Expand)AuthorFilesLines
2015-11-06MachineScheduler: Add regpressure information to debug dumpMatthias Braun1-2/+6
2015-11-03ScheduleDAGInstrs: Remove IsPostRA flag; NFCMatthias Braun1-1/+1
2015-10-09CodeGen: Use range-based for in PostRAScheduler, NFCDuncan P. N. Exon Smith1-12/+11
2015-09-09[PM/AA] Rebuild LLVM's alias analysis infrastructure in a way compatibleChandler Carruth1-2/+2
2015-06-23Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC)Alexander Kornienko1-1/+1
2015-06-19Fixed/added namespace ending comments using clang-tidy. NFCAlexander Kornienko1-1/+1
2015-06-13Rename TargetSubtargetInfo::enablePostMachineScheduler() to enablePostRASched...Matthias Braun1-1/+1
2015-04-11Use 'override/final' instead of 'virtual' for overridden methodsAlexander Kornienko1-1/+1
2015-01-27The subtarget is cached on the MachineFunction. Access it directly.Eric Christopher1-3/+1
2014-10-29Whitespace.NAKAMURA Takumi1-5/+5
2014-10-14Grab the subtarget and subtarget dependent variables off ofEric Christopher1-4/+2
2014-08-20Cleanup: Delete seemingly unused reference to MachineDominatorTree from Sched...Alexey Samsonov1-11/+10
2014-08-20Fix null reference creation in ScheduleDAGInstrs constructor call.Alexey Samsonov1-1/+1
2014-08-05Have MachineFunction cache a pointer to the subtarget to make lookupsEric Christopher1-1/+1
2014-08-04Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher1-3/+5
2014-07-15Move Post RA Scheduling flag bit into SchedMachineModelSanjay Patel1-3/+20
2014-04-22[Modules] Remove potential ODR violations by sinking the DEBUG_TYPEChandler Carruth1-1/+2
2014-04-14[C++11] More 'nullptr' conversion. In some cases just using a boolean check i...Craig Topper1-10/+10
2014-03-31Disable each MachineFunctionPass for 'optnone' functions, unless thatPaul Robinson1-0/+3
2014-03-23remove a bunch of unused private methodsNuno Lopes1-1/+0
2014-03-07[C++11] Add 'override' keyword to virtual methods that override their base cl...Craig Topper1-10/+10
2014-03-02[C++11] Replace llvm::next and llvm::prior with std::next and std::prev.Benjamin Kramer1-3/+3
2013-12-28Move the PostRA scheduler's fixupKills function for reuse.Andrew Trick1-160/+3
2013-12-11Add two additional hazard recognizer functionsHal Finkel1-7/+43
2013-10-16After PostRA scheduling, don't set kill flags on undef operands.Andrew Trick1-2/+2
2013-08-23mi-sched: Don't call MBB.size() in initSUnits. The driver already has instr c...Andrew Trick1-7/+18
2013-05-22Simplify logic now that r182490 is in place. No functional change intended.Chad Rosier1-10/+8
2013-02-05Remove special-casing of return blocks for liveness.Jakob Stoklund Olesen1-19/+5
2012-12-20Use MachineInstrBuilder in a few CodeGen passes.Jakob Stoklund Olesen1-5/+3
2012-12-03Use the new script to sort the includes of every file under lib.Chandler Carruth1-11/+11
2012-11-13misched: Don't consider artificial edges weak edges.Andrew Trick1-1/+1
2012-11-12misched: Infrastructure for weak DAG edges.Andrew Trick1-7/+7
2012-10-15Switch most getReservedRegs() clients to the MRI equivalent.Jakob Stoklund Olesen1-3/+2
2012-09-11Release build: guard dump functions withManman Ren1-1/+1
2012-09-06Release build: guard dump functions with "ifndef NDEBUG"Manman Ren1-0/+2
2012-08-22Add a getName function to MachineFunction. Use it in places that previously d...Craig Topper1-1/+1
2012-06-06Move RegisterClassInfo.h.Andrew Trick1-1/+1
2012-06-06Remove unused private fields found by clang's new -Wunused-private-field.Benjamin Kramer1-1/+0
2012-06-01Switch all register list clients to the new MC*Iterator interface.Jakob Stoklund Olesen1-19/+13
2012-04-23This patch fixes a problem which arose when using the Post-RA schedulerPreston Gurd1-0/+4
2012-03-09misched interface: rename Begin/End to RegionBegin/RegionEnd since they are n...Andrew Trick1-7/+7
2012-03-07misched prep: Expose the ScheduleDAGInstrs interface so targets mayAndrew Trick1-1/+1
2012-03-07misched prep: rename InsertPos to End.Andrew Trick1-8/+8
2012-03-07misched preparation: rename core scheduler methods for consistency.Andrew Trick1-17/+17
2012-03-07misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.Andrew Trick1-12/+38
2012-03-07misched preparation: modularize schedule emission.Andrew Trick1-0/+36
2012-03-07misched preparation: modularize schedule printing.Andrew Trick1-0/+18
2012-03-07misched preparation: modularize schedule verification.Andrew Trick1-2/+8
2012-03-05Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce stati...Craig Topper1-6/+6
2012-02-23BitVectorize loop.Benjamin Kramer1-3/+1
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