diff options
| author | Eric Christopher <echristo@gmail.com> | 2015-05-07 23:10:21 +0000 |
|---|---|---|
| committer | Eric Christopher <echristo@gmail.com> | 2015-05-07 23:10:21 +0000 |
| commit | 330497fc957bd27a2e6af940b3f5e749b7c4e515 (patch) | |
| tree | d9a7ab7cd2dd159218fce377dc95d4c7f4c3705c | |
| parent | a534f7be2b7394ebbe0a60f92d2d8be47aa515ed (diff) | |
Rename the MIPS routine abiUsesSoftFloat -> useSoftFloat to match
some incoming changes and the general scheme used by features (use/has).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236794 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h | 4 | ||||
| -rw-r--r-- | lib/Target/Mips/Mips16ISelLowering.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsCallingConv.td | 8 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsISelLowering.cpp | 4 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsInstrFPU.td | 2 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsSEISelLowering.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsSubtarget.h | 4 |
8 files changed, 13 insertions, 15 deletions
diff --git a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 1aa895d9ca8..cefe4c03811 100644 --- a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -434,7 +434,7 @@ public: return STI.getFeatureBits() & Mips::FeatureMips16; } - bool abiUsesSoftFloat() const { + bool useSoftFloat() const { return (STI.getFeatureBits() & Mips::FeatureSoftFloat); } diff --git a/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h b/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h index c14391151ef..7b3c9caba10 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h +++ b/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h @@ -131,7 +131,7 @@ public: template <class PredicateLibrary> void setCPR1SizeFromPredicates(const PredicateLibrary &P) { - if (P.abiUsesSoftFloat()) + if (P.useSoftFloat()) CPR1Size = Mips::AFL_REG_NONE; else if (P.hasMSA()) CPR1Size = Mips::AFL_REG_128; @@ -159,7 +159,7 @@ public: Is32BitABI = P.isABI_O32(); FpABI = FpABIKind::ANY; - if (P.abiUsesSoftFloat()) + if (P.useSoftFloat()) FpABI = FpABIKind::SOFT; else if (P.isABI_N32() || P.isABI_N64()) FpABI = FpABIKind::S64; diff --git a/lib/Target/Mips/Mips16ISelLowering.cpp b/lib/Target/Mips/Mips16ISelLowering.cpp index 3e72c13ee02..846e3c964f4 100644 --- a/lib/Target/Mips/Mips16ISelLowering.cpp +++ b/lib/Target/Mips/Mips16ISelLowering.cpp @@ -127,7 +127,7 @@ Mips16TargetLowering::Mips16TargetLowering(const MipsTargetMachine &TM, // Set up the register classes addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass); - if (!Subtarget.abiUsesSoftFloat()) + if (!Subtarget.useSoftFloat()) setMips16HardFloatLibCalls(); setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand); diff --git a/lib/Target/Mips/MipsCallingConv.td b/lib/Target/Mips/MipsCallingConv.td index c2e23ffea06..93e1908083c 100644 --- a/lib/Target/Mips/MipsCallingConv.td +++ b/lib/Target/Mips/MipsCallingConv.td @@ -64,9 +64,9 @@ def RetCC_F128HardFloat : CallingConv<[ // Handle F128 specially since we can't identify the original type during the // tablegen-erated code. def RetCC_F128 : CallingConv<[ - CCIfSubtarget<"abiUsesSoftFloat()", + CCIfSubtarget<"useSoftFloat()", CCIfType<[i64], CCDelegateTo<RetCC_F128SoftFloat>>>, - CCIfSubtargetNot<"abiUsesSoftFloat()", + CCIfSubtargetNot<"useSoftFloat()", CCIfType<[i64], CCDelegateTo<RetCC_F128HardFloat>>> ]>; @@ -134,7 +134,7 @@ def CC_MipsN : CallingConv<[ CCIfType<[i8, i16, i32], CCIfOrigArgWasNotFloat<CCPromoteToType<i64>>>, // The only i32's we have left are soft-float arguments. - CCIfSubtarget<"abiUsesSoftFloat()", CCIfType<[i32], CCDelegateTo<CC_MipsN_SoftFloat>>>, + CCIfSubtarget<"useSoftFloat()", CCIfType<[i32], CCDelegateTo<CC_MipsN_SoftFloat>>>, // Integer arguments are passed in integer registers. CCIfType<[i64], CCAssignToRegWithShadow<[A0_64, A1_64, A2_64, A3_64, @@ -372,7 +372,7 @@ def CC_Mips_FixedArg : CallingConv<[ // f128 should only occur for the N64 ABI where long double is 128-bit. On // N32, long double is equivalent to double. CCIfType<[i64], - CCIfSubtargetNot<"abiUsesSoftFloat()", + CCIfSubtargetNot<"useSoftFloat()", CCIfOrigArgWasF128<CCBitConvertToType<f64>>>>, CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_Mips_FastCC>>, diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index ddf846b7483..ad278c28057 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -3017,7 +3017,7 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain, // when allocating floating point values to integer registers. // This shouldn't influence how we load the value into registers unless // we are targetting softfloat. - if (VA.getValVT().isFloatingPoint() && !Subtarget.abiUsesSoftFloat()) + if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat()) LocVT = VA.getValVT(); } @@ -3087,7 +3087,7 @@ MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const { - if (Subtarget.hasMips3() && Subtarget.abiUsesSoftFloat()) { + if (Subtarget.hasMips3() && Subtarget.useSoftFloat()) { if (Type == MVT::i32) return true; } diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td index 848cebcb997..41280471afb 100644 --- a/lib/Target/Mips/MipsInstrFPU.td +++ b/lib/Target/Mips/MipsInstrFPU.td @@ -65,7 +65,7 @@ def IsSingleFloat : Predicate<"Subtarget->isSingleFloat()">, AssemblerPredicate<"FeatureSingleFloat">; def IsNotSingleFloat : Predicate<"!Subtarget->isSingleFloat()">, AssemblerPredicate<"!FeatureSingleFloat">; -def IsNotSoftFloat : Predicate<"!Subtarget->abiUsesSoftFloat()">, +def IsNotSoftFloat : Predicate<"!Subtarget->useSoftFloat()">, AssemblerPredicate<"!FeatureSoftFloat">; //===----------------------------------------------------------------------===// diff --git a/lib/Target/Mips/MipsSEISelLowering.cpp b/lib/Target/Mips/MipsSEISelLowering.cpp index d4adf00be6e..0fec6879bd3 100644 --- a/lib/Target/Mips/MipsSEISelLowering.cpp +++ b/lib/Target/Mips/MipsSEISelLowering.cpp @@ -99,7 +99,7 @@ MipsSETargetLowering::MipsSETargetLowering(const MipsTargetMachine &TM, setTargetDAGCombine(ISD::XOR); } - if (!Subtarget.abiUsesSoftFloat()) { + if (!Subtarget.useSoftFloat()) { addRegisterClass(MVT::f32, &Mips::FGR32RegClass); // When dealing with single precision only, use libcalls diff --git a/lib/Target/Mips/MipsSubtarget.h b/lib/Target/Mips/MipsSubtarget.h index 932b5d5b069..7e9b5a68081 100644 --- a/lib/Target/Mips/MipsSubtarget.h +++ b/lib/Target/Mips/MipsSubtarget.h @@ -236,9 +236,7 @@ public: bool hasStandardEncoding() const { return !inMips16Mode(); } - bool abiUsesSoftFloat() const { - return IsSoftFloat && !InMips16HardFloat; - } + bool useSoftFloat() const { return IsSoftFloat && !InMips16HardFloat; } bool enableLongBranchPass() const { return hasStandardEncoding() || allowMixed16_32(); |