Import i810 dri driver from mesa 7.0.3.7.0.47.0.3

4 files changed, 2287 insertions, 0 deletions

diff --git a/src/server/i810_common.h b/src/server/i810_common.h
new file mode 100644
index 0000000..02e548b
--- /dev/null
+++ b/src/server/i810_common.h
@@ -0,0 +1,192 @@
+/* i810_common.h -- common header definitions for I810 2D/3D/DRM suite
+ *
+ * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Converted to common header format:
+ *   Jens Owen <jens@tungstengraphics.com>
+ *
+ * $XFree86: xc/programs/Xserver/hw/xfree86/drivers/i810/i810_common.h,v 1.1 2002/09/11 00:29:31 dawes Exp $
+ *
+ */
+
+/* WARNING: If you change any of these defines, make sure to change
+ * the kernel include file as well (i810_drm.h)
+ */
+
+#ifndef _I810_COMMON_H_
+#define _I810_COMMON_H_
+
+#ifndef _I810_DEFINES_
+#define _I810_DEFINES_
+#define I810_USE_BATCH 1
+
+#define I810_DMA_BUF_ORDER     12
+#define I810_DMA_BUF_SZ        (1<<I810_DMA_BUF_ORDER)
+#define I810_DMA_BUF_NR        256
+
+#define I810_NR_SAREA_CLIPRECTS 8
+
+/* Each region is a minimum of 64k, and there are at most 64 of them.
+ */
+#define I810_NR_TEX_REGIONS 64
+#define I810_LOG_MIN_TEX_REGION_SIZE 16
+
+/* Destbuffer state
+ *    - backbuffer linear offset and pitch -- invarient in the current dri
+ *    - zbuffer linear offset and pitch -- also invarient
+ *    - drawing origin in back and depth buffers.
+ *
+ * Keep the depth/back buffer state here to acommodate private buffers
+ * in the future.
+ */
+#define I810_DESTREG_DI0  0		/* CMD_OP_DESTBUFFER_INFO (2 dwords) */
+#define I810_DESTREG_DI1  1
+#define I810_DESTREG_DV0  2		/* GFX_OP_DESTBUFFER_VARS (2 dwords) */
+#define I810_DESTREG_DV1  3
+#define I810_DESTREG_DR0  4		/* GFX_OP_DRAWRECT_INFO (4 dwords) */
+#define I810_DESTREG_DR1  5
+#define I810_DESTREG_DR2  6
+#define I810_DESTREG_DR3  7
+#define I810_DESTREG_DR4  8
+#define I810_DEST_SETUP_SIZE 10
+
+/* Context state
+ */
+#define I810_CTXREG_CF0   0		/* GFX_OP_COLOR_FACTOR */
+#define I810_CTXREG_CF1   1
+#define I810_CTXREG_ST0   2		/* GFX_OP_STIPPLE */
+#define I810_CTXREG_ST1   3
+#define I810_CTXREG_VF    4		/* GFX_OP_VERTEX_FMT */
+#define I810_CTXREG_MT    5		/* GFX_OP_MAP_TEXELS */
+#define I810_CTXREG_MC0   6		/* GFX_OP_MAP_COLOR_STAGES - stage 0 */
+#define I810_CTXREG_MC1   7		/* GFX_OP_MAP_COLOR_STAGES - stage 1 */
+#define I810_CTXREG_MC2   8		/* GFX_OP_MAP_COLOR_STAGES - stage 2 */
+#define I810_CTXREG_MA0   9		/* GFX_OP_MAP_ALPHA_STAGES - stage 0 */
+#define I810_CTXREG_MA1   10		/* GFX_OP_MAP_ALPHA_STAGES - stage 1 */
+#define I810_CTXREG_MA2   11		/* GFX_OP_MAP_ALPHA_STAGES - stage 2 */
+#define I810_CTXREG_SDM   12		/* GFX_OP_SRC_DEST_MONO */
+#define I810_CTXREG_FOG   13		/* GFX_OP_FOG_COLOR */
+#define I810_CTXREG_B1    14		/* GFX_OP_BOOL_1 */
+#define I810_CTXREG_B2    15		/* GFX_OP_BOOL_2 */
+#define I810_CTXREG_LCS   16		/* GFX_OP_LINEWIDTH_CULL_SHADE_MODE */
+#define I810_CTXREG_PV    17		/* GFX_OP_PV_RULE -- Invarient! */
+#define I810_CTXREG_ZA    18		/* GFX_OP_ZBIAS_ALPHAFUNC */
+#define I810_CTXREG_AA    19		/* GFX_OP_ANTIALIAS */
+#define I810_CTX_SETUP_SIZE 20
+
+/* Texture state (per tex unit)
+ */
+#define I810_TEXREG_MI0  0		/* GFX_OP_MAP_INFO (4 dwords) */
+#define I810_TEXREG_MI1  1
+#define I810_TEXREG_MI2  2
+#define I810_TEXREG_MI3  3
+#define I810_TEXREG_MF   4		/* GFX_OP_MAP_FILTER */
+#define I810_TEXREG_MLC  5		/* GFX_OP_MAP_LOD_CTL */
+#define I810_TEXREG_MLL  6		/* GFX_OP_MAP_LOD_LIMITS */
+#define I810_TEXREG_MCS  7		/* GFX_OP_MAP_COORD_SETS ??? */
+#define I810_TEX_SETUP_SIZE 8
+
+/* Driver specific DRM command indices
+ * NOTE: these are not OS specific, but they are driver specific
+ */
+#define DRM_I810_INIT                     0x00
+#define DRM_I810_VERTEX                   0x01
+#define DRM_I810_CLEAR                    0x02
+#define DRM_I810_FLUSH                    0x03
+#define DRM_I810_GETAGE                   0x04
+#define DRM_I810_GETBUF                   0x05
+#define DRM_I810_SWAP                     0x06
+#define DRM_I810_COPY                     0x07
+#define DRM_I810_DOCOPY                   0x08
+#define DRM_I810_OV0INFO                  0x09
+#define DRM_I810_FSTATUS                  0x0a
+#define DRM_I810_OV0FLIP                  0x0b
+#define DRM_I810_MC                       0x0c
+#define DRM_I810_RSTATUS                  0x0d
+#define DRM_I810_FLIP                     0x0e
+
+#endif
+
+typedef enum _drmI810Initfunc {
+	I810_INIT_DMA = 0x01,
+	I810_CLEANUP_DMA = 0x02,
+	I810_INIT_DMA_1_4 = 0x03
+} drmI810Initfunc;
+
+typedef struct {
+   drmI810Initfunc func;
+   unsigned int mmio_offset;
+   unsigned int buffers_offset;
+   int sarea_priv_offset;
+   unsigned int ring_start;
+   unsigned int ring_end;
+   unsigned int ring_size;
+   unsigned int front_offset;
+   unsigned int back_offset;
+   unsigned int depth_offset;
+   unsigned int overlay_offset;
+   unsigned int overlay_physical;
+   unsigned int w;
+   unsigned int h;
+   unsigned int pitch;
+   unsigned int pitch_bits;
+} drmI810Init;
+
+typedef struct {
+   void *virtual;
+   int request_idx;
+   int request_size;
+   int granted;
+} drmI810DMA;
+
+/* Flags for clear ioctl
+ */
+#define I810_FRONT   0x1
+#define I810_BACK    0x2
+#define I810_DEPTH   0x4
+
+typedef struct {
+   int clear_color;
+   int clear_depth;
+   int flags;
+} drmI810Clear;
+
+typedef struct {
+   int idx;				/* buffer index */
+   int used;				/* nr bytes in use */
+   int discard;				/* client is finished with the buffer? */
+} drmI810Vertex;
+
+/* Flags for vertex ioctl
+ */
+#define PR_TRIANGLES         (0x0<<18)
+#define PR_TRISTRIP_0        (0x1<<18)
+#define PR_TRISTRIP_1        (0x2<<18)
+#define PR_TRIFAN            (0x3<<18)
+#define PR_POLYGON           (0x4<<18)
+#define PR_LINES             (0x5<<18)
+#define PR_LINESTRIP         (0x6<<18)
+#define PR_RECTS             (0x7<<18)
+#define PR_MASK              (0x7<<18)
+
+#endif
diff --git a/src/server/i810_dri.c b/src/server/i810_dri.c
new file mode 100644
index 0000000..f52797c
--- /dev/null
+++ b/src/server/i810_dri.c
@@ -0,0 +1,975 @@
+/**
+ * \file server/i810_dri.c
+ * \brief File to perform the device-specific initialization tasks typically
+ * done in the X server.
+ *
+ * Here they are converted to run in the client (or perhaps a standalone
+ * process), and to work with the frame buffer device rather than the X
+ * server infrastructure.
+ * 
+ * Copyright (C) 2004 Dave Airlie (airlied@linux.ie)
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <errno.h>
+#include <unistd.h>
+
+#include "driver.h"
+#include "drm.h"
+
+#include "i810.h"
+#include "i810_dri.h"
+#include "i810_reg.h"
+
+
+static int i810_pitches[] = {
+   512,
+   1024,
+   2048,
+   4096,
+   0
+};
+
+static int i810_pitch_flags[] = {
+   0x0,
+   0x1,
+   0x2,
+   0x3,
+   0
+};
+
+static unsigned int i810_drm_version = 0;
+
+static int
+I810AllocLow(I810MemRange * result, I810MemRange * pool, int size)
+{
+   if (size > pool->Size)
+      return 0;
+
+   pool->Size -= size;
+   result->Size = size;
+   result->Start = pool->Start;
+   result->End = pool->Start += size;
+
+   return 1;
+}
+
+static int
+I810AllocHigh(I810MemRange * result, I810MemRange * pool, int size)
+{
+   if (size > pool->Size)
+      return 0;
+
+   pool->Size -= size;
+   result->Size = size;
+   result->End = pool->End;
+   result->Start = pool->End -= size;
+
+   return 1;
+}
+
+
+/**
+ * \brief Wait for free FIFO entries.
+ *
+ * \param ctx display handle.
+ * \param entries number of free entries to wait.
+ *
+ * It polls the free entries from the chip until it reaches the requested value
+ * or a timeout (3000 tries) occurs. Aborts the program if the FIFO times out.
+ */
+static void I810WaitForFifo( const DRIDriverContext *ctx,
+			       int entries )
+{
+}
+
+/**
+ * \brief Reset graphics card to known state.
+ *
+ * \param ctx display handle.
+ *
+ * Resets the values of several I810 registers.
+ */
+static void I810EngineReset( const DRIDriverContext *ctx )
+{
+   unsigned char *I810MMIO = ctx->MMIOAddress;
+}
+
+/**
+ * \brief Restore the drawing engine.
+ *
+ * \param ctx display handle
+ *
+ * Resets the graphics card and sets initial values for several registers of
+ * the card's drawing engine.
+ *
+ * Turns on the i810 command processor engine (i.e., the ringbuffer).
+ */
+static int I810EngineRestore( const DRIDriverContext *ctx )
+{
+   I810Ptr info = ctx->driverPrivate;
+   unsigned char *I810MMIO = ctx->MMIOAddress;
+
+   fprintf(stderr, "%s\n", __FUNCTION__);
+
+   return 1;
+}
+
+
+/**
+ * \brief Shutdown the drawing engine.
+ *
+ * \param ctx display handle
+ *
+ * Turns off the command processor engine & restores the graphics card
+ * to a state that fbdev understands.
+ */
+static int I810EngineShutdown( const DRIDriverContext *ctx )
+{
+  drmI810Init info;
+  int ret;
+
+  memset(&info, 0, sizeof(drmI810Init));
+  info.func = I810_CLEANUP_DMA;
+  
+  ret = drmCommandWrite(ctx->drmFD, DRM_I810_INIT, &info, sizeof(drmI810Init));
+  if (ret>0)
+  {
+    fprintf(stderr,"[dri] I810 DMA Cleanup failed\n");
+    return -errno;
+  }
+  return 0;
+}
+
+/**
+ * \brief Compute base 2 logarithm.
+ *
+ * \param val value.
+ * 
+ * \return base 2 logarithm of \p val.
+ */
+static int I810MinBits(int val)
+{
+   int  bits;
+
+   if (!val) return 1;
+   for (bits = 0; val; val >>= 1, ++bits);
+   return bits;
+}
+
+static int I810DRIAgpPreInit( const DRIDriverContext *ctx, I810Ptr info)
+{
+
+  if (drmAgpAcquire(ctx->drmFD) < 0) {
+    fprintf(stderr, "[gart] AGP not available\n");
+    return 0;
+  }
+  
+  
+  if (drmAgpEnable(ctx->drmFD, 0) < 0) {
+    fprintf(stderr, "[gart] AGP not enabled\n");
+    drmAgpRelease(ctx->drmFD);
+    return 0;
+  }
+}
+
+/**
+ * \brief Initialize the AGP state
+ *
+ * \param ctx display handle.
+ * \param info driver private data.
+ *
+ * \return one on success, or zero on failure.
+ * 
+ * Acquires and enables the AGP device. Reserves memory in the AGP space for
+ * the ring buffer, vertex buffers and textures. Initialize the I810
+ * registers to point to that memory and add client mappings.
+ */
+static int I810DRIAgpInit( const DRIDriverContext *ctx, I810Ptr info)
+{
+   unsigned char *I810MMIO = ctx->MMIOAddress;
+   int            ret;
+   int            s, l;
+   unsigned long dcacheHandle;
+   unsigned long agpHandle;
+   int pitch_idx = 0;
+   int back_size = 0;
+   int sysmem_size = 0;
+   int width = ctx->shared.virtualWidth * ctx->cpp;
+
+
+   info->backHandle = DRM_AGP_NO_HANDLE;
+   info->zHandle = DRM_AGP_NO_HANDLE;
+   info->sysmemHandle = DRM_AGP_NO_HANDLE;
+   info->dcacheHandle = DRM_AGP_NO_HANDLE;
+
+   memset(&info->DcacheMem, 0, sizeof(I810MemRange));
+   memset(&info->BackBuffer, 0, sizeof(I810MemRange));
+   memset(&info->DepthBuffer, 0, sizeof(I810MemRange));
+   
+   drmAgpAlloc(ctx->drmFD, 4096 * 1024, 1, NULL, &dcacheHandle);
+   info->dcacheHandle = dcacheHandle;
+   
+   fprintf(stderr, "[agp] dcacheHandle : 0x%x\n", dcacheHandle);
+
+#define Elements(x) sizeof(x)/sizeof(*x)
+   for (pitch_idx = 0; pitch_idx < Elements(i810_pitches); pitch_idx++)
+     if (width <= i810_pitches[pitch_idx])
+       break;
+   
+   if (pitch_idx == Elements(i810_pitches)) {
+     fprintf(stderr,"[dri] Couldn't find depth/back buffer pitch\n");
+     exit(-1);
+   }
+   else
+   {
+     int lines = (ctx->shared.virtualWidth + 15) / 16 * 16;
+     back_size = i810_pitches[pitch_idx] * lines;
+     back_size = ((back_size + 4096 - 1) / 4096) * 4096;
+   }
+
+   sysmem_size = ctx->shared.fbSize;
+   fprintf(stderr,"sysmem_size is %lu back_size is %lu\n", sysmem_size, back_size);
+   if (dcacheHandle != DRM_AGP_NO_HANDLE) {
+     if (back_size > 4 * 1024 * 1024) {
+       fprintf(stderr,"[dri] Backsize is larger then 4 meg\n");
+       sysmem_size = sysmem_size - 2 * back_size;
+       drmAgpFree(ctx->drmFD, dcacheHandle);
+       info->dcacheHandle = dcacheHandle = DRM_AGP_NO_HANDLE;
+     } else {
+       sysmem_size = sysmem_size - back_size;
+     }
+   } else {
+     sysmem_size = sysmem_size - 2 * back_size;
+   }
+   
+   info->SysMem.Start=0;
+   info->SysMem.Size = sysmem_size;
+   info->SysMem.End = sysmem_size;
+   
+   if (dcacheHandle != DRM_AGP_NO_HANDLE) {
+      if (drmAgpBind(ctx->drmFD, dcacheHandle, info->DepthOffset) == 0) {
+	memset(&info->DcacheMem, 0, sizeof(I810MemRange));
+	fprintf(stderr,"[agp] GART: Found 4096K Z buffer memory\n");
+	info->DcacheMem.Start = info->DepthOffset;
+	 info->DcacheMem.Size = 1024 * 4096;
+	 info->DcacheMem.End =  info->DcacheMem.Start + info->DcacheMem.Size;
+      } else {
+	fprintf(stderr, "[agp] GART: dcache bind failed\n");
+	drmAgpFree(ctx->drmFD, dcacheHandle);
+	info->dcacheHandle = dcacheHandle = DRM_AGP_NO_HANDLE;
+      }
+   } else {
+     fprintf(stderr, "[agp] GART: no dcache memory found\n");
+   }
+   
+   drmAgpAlloc(ctx->drmFD, back_size, 0, NULL, &agpHandle);
+   info->backHandle = agpHandle;
+
+   if (agpHandle != DRM_AGP_NO_HANDLE) {
+      if (drmAgpBind(ctx->drmFD, agpHandle, info->BackOffset) == 0) {
+	fprintf(stderr, "[agp] Bound backbuffer memory\n");
+
+	info->BackBuffer.Start = info->BackOffset;
+	info->BackBuffer.Size = back_size;
+	info->BackBuffer.End = (info->BackBuffer.Start +
+				 info->BackBuffer.Size);
+      } else {
+	fprintf(stderr,"[agp] Unable to bind backbuffer.  Disabling DRI.\n");
+	return 0;
+      }
+   } else {
+     fprintf(stderr, "[dri] Unable to allocate backbuffer memory.  Disabling DRI.\n");
+     return 0;
+   }
+
+   if (dcacheHandle == DRM_AGP_NO_HANDLE) {
+     drmAgpAlloc(ctx->drmFD, back_size, 0, NULL, &agpHandle);
+
+     info->zHandle = agpHandle;
+
+     if (agpHandle != DRM_AGP_NO_HANDLE) {
+       if (drmAgpBind(ctx->drmFD, agpHandle, info->DepthOffset) == 0) {
+	 fprintf(stderr,"[agp] Bound depthbuffer memory\n");
+	 info->DepthBuffer.Start = info->DepthOffset;
+	 info->DepthBuffer.Size = back_size;
+	 info->DepthBuffer.End = (info->DepthBuffer.Start +
+				   info->DepthBuffer.Size);
+       } else {
+	 fprintf(stderr,"[agp] Unable to bind depthbuffer.  Disabling DRI.\n");
+	 return 0;
+       }
+     } else {
+       fprintf(stderr,"[agp] Unable to allocate depthbuffer memory.  Disabling DRI.\n");
+       return 0;
+     }
+   }
+
+   /* Now allocate and bind the agp space.  This memory will include the
+    * regular framebuffer as well as texture memory.
+    */
+   drmAgpAlloc(ctx->drmFD, sysmem_size, 0, NULL, &agpHandle);
+   info->sysmemHandle = agpHandle;
+   
+   if (agpHandle != DRM_AGP_NO_HANDLE) {
+     if (drmAgpBind(ctx->drmFD, agpHandle, 0) == 0) {
+       fprintf(stderr, "[agp] Bound System Texture Memory\n");
+     } else {
+       fprintf(stderr, "[agp] Unable to bind system texture memory. Disabling DRI.\n");
+       return 0;
+     }
+   } else {
+     fprintf(stderr, "[agp] Unable to allocate system texture memory. Disabling DRI.\n");
+     return 0;
+   }
+   
+   info->auxPitch = i810_pitches[pitch_idx];
+   info->auxPitchBits = i810_pitch_flags[pitch_idx];
+   
+   return 1;
+}
+
+
+/**
+ * \brief Initialize the kernel data structures and enable the CP engine.
+ *
+ * \param ctx display handle.
+ * \param info driver private data.
+ *
+ * \return non-zero on success, or zero on failure.
+ *
+ * This function is a wrapper around the DRM_I810_CP_INIT command, passing
+ * all the parameters in a drmI810Init structure.
+ */
+static int I810DRIKernelInit( const DRIDriverContext *ctx,
+			       I810Ptr info)
+{
+   int cpp = ctx->bpp / 8;
+   drmI810Init  drmInfo;
+   int ret;
+   I810RingBuffer *ring = &(info->LpRing);
+
+   /* This is the struct passed to the kernel module for its initialization */
+   memset(&drmInfo, 0, sizeof(drmI810Init));
+   
+   /* make sure we have at least 1.4 */
+   drmInfo.func             = I810_INIT_DMA_1_4;
+
+   drmInfo.ring_start = ring->mem.Start;
+   drmInfo.ring_end = ring->mem.End;
+   drmInfo.ring_size = ring->mem.Size;
+
+   drmInfo.mmio_offset         = (unsigned int)info->regs;
+   drmInfo.buffers_offset      = (unsigned int)info->buffer_map;
+   drmInfo.sarea_priv_offset   = sizeof(drm_sarea_t);
+
+   drmInfo.front_offset        = 0;
+   drmInfo.back_offset         = info->BackBuffer.Start;
+   drmInfo.depth_offset        = info->DepthBuffer.Start;
+
+   drmInfo.w                   = ctx->shared.virtualWidth;
+   drmInfo.h                   = ctx->shared.virtualHeight;
+   drmInfo.pitch               = info->auxPitch;
+   drmInfo.pitch_bits          = info->auxPitchBits;
+   
+
+   ret = drmCommandWrite(ctx->drmFD, DRM_I810_INIT, &drmInfo, 
+			 sizeof(drmI810Init));
+
+   return ret >= 0;
+}
+
+
+/**
+ * \brief Add a map for the vertex buffers that will be accessed by any
+ * DRI-based clients.
+ * 
+ * \param ctx display handle.
+ * \param info driver private data.
+ *
+ * \return one on success, or zero on failure.
+ *
+ * Calls drmAddBufs() with the previously allocated vertex buffers.
+ */
+static int I810DRIBufInit( const DRIDriverContext *ctx, I810Ptr info )
+{
+   /* Initialize vertex buffers */
+   info->bufNumBufs = drmAddBufs(ctx->drmFD,
+				 I810_DMA_BUF_NR,
+				 I810_DMA_BUF_SZ,
+				 DRM_AGP_BUFFER,
+				 info->BufferMem.Start);
+
+   if (info->bufNumBufs <= 0) {
+      fprintf(stderr,
+	      "[drm] Could not create vertex/indirect buffers list\n");
+      return 0;
+   }
+   fprintf(stderr,
+	   "[drm] Added %d %d byte vertex/indirect buffers\n",
+	   info->bufNumBufs, I810_DMA_BUF_SZ);
+   
+   return 1;
+}
+
+/**
+ * \brief Install an IRQ handler.
+ * 
+ * \param ctx display handle.
+ * \param info driver private data.
+ *
+ * Attempts to install an IRQ handler via drmCtlInstHandler(), falling back to
+ * IRQ-free operation on failure.
+ */
+static void I810DRIIrqInit(const DRIDriverContext *ctx,
+			     I810Ptr info)
+{
+   if (!info->irq) {
+      info->irq = drmGetInterruptFromBusID(ctx->drmFD,
+					   ctx->pciBus,
+					   ctx->pciDevice,
+					   ctx->pciFunc);
+
+      if ((drmCtlInstHandler(ctx->drmFD, info->irq)) != 0) {
+	 fprintf(stderr,
+		 "[drm] failure adding irq handler, "
+		 "there is a device already using that irq\n"
+		 "[drm] falling back to irq-free operation\n");
+	 info->irq = 0;
+      }
+   }
+
+   if (info->irq)
+      fprintf(stderr,
+	      "[drm] dma control initialized, using IRQ %d\n",
+	      info->irq);
+}
+
+static int I810CheckDRMVersion( const DRIDriverContext *ctx,
+				  I810Ptr info )
+{
+   drmVersionPtr  version;
+
+   version = drmGetVersion(ctx->drmFD);
+   if (version) {
+      int req_minor, req_patch;
+
+      req_minor = 4;
+      req_patch = 0;	
+
+      i810_drm_version = (version->version_major<<16) | version->version_minor;
+      if (version->version_major != 1 ||
+	  version->version_minor < req_minor ||
+	  (version->version_minor == req_minor && 
+	   version->version_patchlevel < req_patch)) {
+	 /* Incompatible drm version */
+	 fprintf(stderr,
+		 "[dri] I810DRIScreenInit failed because of a version "
+		 "mismatch.\n"
+		 "[dri] i810.o kernel module version is %d.%d.%d "
+		 "but version 1.%d.%d or newer is needed.\n"
+		 "[dri] Disabling DRI.\n",
+		 version->version_major,
+		 version->version_minor,
+		 version->version_patchlevel,
+		 req_minor,
+		 req_patch);
+	 drmFreeVersion(version);
+	 return 0;
+      }
+
+      info->drmMinor = version->version_minor;
+      drmFreeVersion(version);
+   }
+
+   return 1;
+}
+
+static int I810MemoryInit( const DRIDriverContext *ctx, I810Ptr info )
+{
+   int        width_bytes = ctx->shared.virtualWidth * ctx->cpp;
+   int        cpp         = ctx->cpp;
+   int        bufferSize  = (ctx->shared.virtualHeight * width_bytes);
+   int        depthSize   = (((ctx->shared.virtualHeight+15) & ~15) * width_bytes);
+   int        l;
+
+   if (drmAddMap(ctx->drmFD, (drm_handle_t) info->BackBuffer.Start,
+		 info->BackBuffer.Size, DRM_AGP, 0,
+		 &info->backbuffer) < 0) {
+     fprintf(stderr, "[drm] drmAddMap(backbuffer) failed.  Disabling DRI\n");
+     return 0;
+   }
+   
+   if (drmAddMap(ctx->drmFD, (drm_handle_t) info->DepthBuffer.Start,
+		 info->DepthBuffer.Size, DRM_AGP, 0,
+		 &info->depthbuffer) < 0) {
+     fprintf(stderr, "[drm] drmAddMap(depthbuffer) failed.  Disabling DRI.\n");
+      return 0;
+   }
+
+   if (!I810AllocLow(&(info->FrontBuffer), &(info->SysMem), (((ctx->shared.virtualHeight * width_bytes) + 4095) & ~4095)))
+   {
+     fprintf(stderr,"Framebuffer allocation failed\n");
+     return 0;
+   }
+   else
+     fprintf(stderr,"Frame buffer at 0x%.8x (%luk, %lu bytes)\n",
+	     info->FrontBuffer.Start,
+	     info->FrontBuffer.Size / 1024, info->FrontBuffer.Size);
+   
+   memset(&(info->LpRing), 0, sizeof(I810RingBuffer));
+   if (I810AllocLow(&(info->LpRing.mem), &(info->SysMem), 16 * 4096)) {
+     fprintf(stderr,
+	    "Ring buffer at 0x%.8x (%luk, %lu bytes)\n",
+	     info->LpRing.mem.Start,
+	     info->LpRing.mem.Size / 1024, info->LpRing.mem.Size);
+     
+     info->LpRing.tail_mask = info->LpRing.mem.Size - 1;
+     info->LpRing.virtual_start = info->LpRing.mem.Start;
+     info->LpRing.head = 0;
+     info->LpRing.tail = 0;
+     info->LpRing.space = 0;
+   } else {
+     fprintf(stderr, "Ring buffer allocation failed\n");
+     return (0);
+   }
+
+   /* Allocate buffer memory */
+   I810AllocHigh(&(info->BufferMem), &(info->SysMem),
+		 I810_DMA_BUF_NR * I810_DMA_BUF_SZ);
+   
+
+   fprintf(stderr, "[dri] Buffer map : %lx\n",
+	      info->BufferMem.Start);
+
+   if (info->BufferMem.Start == 0 ||
+       info->BufferMem.End - info->BufferMem.Start >
+       I810_DMA_BUF_NR * I810_DMA_BUF_SZ) {
+     fprintf(stderr,"[dri] Not enough memory for dma buffers.  Disabling DRI.\n");
+     return 0;
+   }
+
+   if (drmAddMap(ctx->drmFD, (drm_handle_t) info->BufferMem.Start,
+		 info->BufferMem.Size, DRM_AGP, 0, &info->buffer_map) < 0) {
+     fprintf(stderr, "[drm] drmAddMap(buffer_map) failed.  Disabling DRI.\n");
+     return 0;
+   }
+
+   if (drmAddMap(ctx->drmFD, (drm_handle_t) info->LpRing.mem.Start,
+		 info->LpRing.mem.Size, DRM_AGP, 0, &info->ring_map) < 0) {
+     fprintf(stderr, "[drm] drmAddMap(ring_map) failed.  Disabling DRI. \n");
+     return 0;
+   }
+
+   /* Front, back and depth buffers - everything else texture??
+    */
+   info->textureSize = info->SysMem.Size;
+
+   if (info->textureSize < 0) 
+      return 0;
+
+   
+   l = I810MinBits((info->textureSize-1) / I810_NR_TEX_REGIONS);
+   if (l < I810_LOG_MIN_TEX_REGION_SIZE) l = I810_LOG_MIN_TEX_REGION_SIZE;
+
+   /* Round the texture size up to the nearest whole number of
+    * texture regions.  Again, be greedy about this, don't
+    * round down.
+    */
+   info->logTextureGranularity = l;
+   info->textureSize = (info->textureSize >> l) << l;
+
+   /* Set a minimum usable local texture heap size.  This will fit
+    * two 256x256x32bpp textures.
+    */
+   if (info->textureSize < 512 * 1024) {
+      info->textureOffset = 0;
+      info->textureSize = 0;
+   }
+
+   I810AllocLow(&(info->TexMem), &(info->SysMem), info->textureSize);
+
+   if (drmAddMap(ctx->drmFD, (drm_handle_t) info->TexMem.Start,
+		 info->TexMem.Size, DRM_AGP, 0, &info->textures) < 0) {
+     fprintf(stderr,
+		 "[drm] drmAddMap(textures) failed.  Disabling DRI.\n");
+      return 0;
+   }
+
+   /* Reserve space for textures */
+   fprintf(stderr, 
+	   "Will use back buffer at offset 0x%x\n",
+	   info->BackOffset);
+   fprintf(stderr, 
+	   "Will use depth buffer at offset 0x%x\n",
+	   info->DepthOffset);
+   fprintf(stderr, 
+	   "Will use %d kb for textures at offset 0x%x\n",
+	   info->TexMem.Size/1024, info->TexMem.Start);
+
+   return 1;
+} 
+
+
+
+/**
+ * Called at the start of each server generation.
+ *
+ * \param ctx display handle.
+ * \param info driver private data.
+ *
+ * \return non-zero on success, or zero on failure.
+ *
+ * Performs static frame buffer allocation. Opens the DRM device and add maps
+ * to the SAREA, framebuffer and MMIO regions. Fills in \p info with more
+ * information. Creates a \e server context to grab the lock for the
+ * initialization ioctls and calls the other initilization functions in this
+ * file. Starts the CP engine via the DRM_I810_CP_START command.
+ *
+ * Setups a I810DRIRec structure to be passed to i810_dri.so for its
+ * initialization.
+ */
+static int I810ScreenInit( DRIDriverContext *ctx, I810Ptr info )
+{
+   I810DRIPtr   pI810DRI;
+   int err;
+
+   usleep(100);
+   /*assert(!ctx->IsClient);*/
+
+   /* from XFree86 driver */
+   info->DepthOffset = 0x3000000;
+   info->BackOffset = 0x3800000;
+   {
+      int  width_bytes = (ctx->shared.virtualWidth * ctx->cpp);
+      int  maxy        = ctx->shared.fbSize / width_bytes;
+
+
+      if (maxy <= ctx->shared.virtualHeight * 3) {
+	 fprintf(stderr, 
+		 "Static buffer allocation failed -- "
+		 "need at least %d kB video memory (have %d kB)\n",
+		 (ctx->shared.virtualWidth * ctx->shared.virtualHeight *
+		  ctx->cpp * 3 + 1023) / 1024,
+		 ctx->shared.fbSize / 1024);
+	 return 0;
+      } 
+   }
+
+
+   info->regsSize = ctx->MMIOSize;
+   ctx->shared.SAREASize = 0x2000;
+
+   /* Note that drmOpen will try to load the kernel module, if needed. */
+   ctx->drmFD = drmOpen("i810", NULL );
+   if (ctx->drmFD < 0) {
+      fprintf(stderr, "[drm] drmOpen failed\n");
+      return 0;
+   }
+
+   if ((err = drmSetBusid(ctx->drmFD, ctx->pciBusID)) < 0) {
+      fprintf(stderr, "[drm] drmSetBusid failed (%d, %s), %s\n",
+	      ctx->drmFD, ctx->pciBusID, strerror(-err));
+      return 0;
+   }
+
+   if (drmAddMap( ctx->drmFD,
+		  0,
+		  ctx->shared.SAREASize,
+		  DRM_SHM,
+		  DRM_CONTAINS_LOCK,
+		  &ctx->shared.hSAREA) < 0)
+   {
+      fprintf(stderr, "[drm] drmAddMap failed\n");
+      return 0;
+   }
+   fprintf(stderr, "[drm] added %d byte SAREA at 0x%08lx\n",
+	   ctx->shared.SAREASize, ctx->shared.hSAREA);
+
+   if (drmMap( ctx->drmFD,
+	       ctx->shared.hSAREA,
+	       ctx->shared.SAREASize,
+	       (drmAddressPtr)(&ctx->pSAREA)) < 0)
+   {
+      fprintf(stderr, "[drm] drmMap failed\n");
+      return 0;
+   }
+   memset(ctx->pSAREA, 0, ctx->shared.SAREASize);
+   fprintf(stderr, "[drm] mapped SAREA 0x%08lx to %p, size %d\n",
+	   ctx->shared.hSAREA, ctx->pSAREA, ctx->shared.SAREASize);
+
+   if (drmAddMap(ctx->drmFD, 
+		 ctx->MMIOStart,
+		 ctx->MMIOSize,
+		 DRM_REGISTERS, 
+		 DRM_READ_ONLY, 
+		 &info->regs) < 0) {
+      fprintf(stderr, "[drm] drmAddMap mmio failed\n");	
+      return 0;
+   }
+   fprintf(stderr,
+	   "[drm] register handle = 0x%08x\n", info->regs);
+
+   I810DRIAgpPreInit(ctx, info);
+   /* Need to AddMap the framebuffer and mmio regions here:
+    */
+   if (drmAddMap( ctx->drmFD,
+		  (drm_handle_t)ctx->FBStart,
+		  ctx->FBSize,
+		  DRM_FRAME_BUFFER,
+#ifndef _EMBEDDED
+		  0,
+#else
+		  DRM_READ_ONLY,
+#endif
+		  &ctx->shared.hFrameBuffer) < 0)
+   {
+      fprintf(stderr, "[drm] drmAddMap framebuffer failed\n");
+      return 0;
+   }
+
+   fprintf(stderr, "[drm] framebuffer handle = 0x%08lx\n",
+	   ctx->shared.hFrameBuffer);
+
+   /* Check the i810 DRM version */
+   if (!I810CheckDRMVersion(ctx, info)) {
+      return 0;
+   }
+
+   /* Initialize AGP */
+   if (!I810DRIAgpInit(ctx, info)) {
+      return 0;
+   }
+
+
+   /* Memory manager setup */
+   if (!I810MemoryInit(ctx, info)) {
+      return 0;
+   }
+
+   /* Initialize the SAREA private data structure */
+   {
+      I810SAREAPtr pSAREAPriv;
+      pSAREAPriv = (I810SAREAPtr)(((char*)ctx->pSAREA) + 
+					sizeof(drm_sarea_t));
+      memset(pSAREAPriv, 0, sizeof(*pSAREAPriv));
+      //      pSAREAPriv->pf_enabled=1;
+   }
+
+
+   /* Create a 'server' context so we can grab the lock for
+    * initialization ioctls.
+    */
+   if ((err = drmCreateContext(ctx->drmFD, &ctx->serverContext)) != 0) {
+      fprintf(stderr, "%s: drmCreateContext failed %d\n", __FUNCTION__, err);
+      return 0;
+   }
+
+   DRM_LOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext, 0); 
+
+   /* Initialize the vertex buffers list */
+   if (!I810DRIBufInit(ctx, info)) {
+      fprintf(stderr, "I810DRIBufInit failed\n");
+      DRM_UNLOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext);
+      return 0;
+   }
+
+   /* Initialize the kernel data structures */
+   if (!I810DRIKernelInit(ctx, info)) {
+      fprintf(stderr, "I810DRIKernelInit failed\n");
+      DRM_UNLOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext);
+      return 0;
+   }
+
+   /* Initialize IRQ */
+   I810DRIIrqInit(ctx, info);
+
+   /* Quick hack to clear the front & back buffers.  Could also use
+    * the clear ioctl to do this, but would need to setup hw state
+    * first.
+    */
+#if 0
+   memset((char *)ctx->FBAddress,
+	  0,
+	  info->auxPitch * ctx->cpp * ctx->shared.virtualHeight );
+
+   memset((char *)info->backbuffer,
+	  0,
+	  info->auxPitch * ctx->cpp * ctx->shared.virtualHeight );
+#endif
+
+   /* This is the struct passed to i810_dri.so for its initialization */
+   ctx->driverClientMsg = malloc(sizeof(I810DRIRec));
+   ctx->driverClientMsgSize = sizeof(I810DRIRec);
+   pI810DRI                    = (I810DRIPtr)ctx->driverClientMsg;
+
+   pI810DRI->regs              = info->regs;
+   pI810DRI->regsSize          = info->regsSize;
+   // regsMap is unused
+
+   pI810DRI->backbufferSize    = info->BackBuffer.Size;
+   pI810DRI->backbuffer        = info->backbuffer;
+
+   pI810DRI->depthbufferSize   = info->DepthBuffer.Size;
+   pI810DRI->depthbuffer       = info->depthbuffer;
+
+   pI810DRI->textures          = info->textures;
+   pI810DRI->textureSize       = info->textureSize;
+
+   pI810DRI->agp_buffers       = info->buffer_map;
+   pI810DRI->agp_buf_size      = info->BufferMem.Size;
+
+   pI810DRI->deviceID          = info->Chipset;
+   pI810DRI->width             = ctx->shared.virtualWidth;
+   pI810DRI->height            = ctx->shared.virtualHeight;
+   pI810DRI->mem               = ctx->shared.fbSize;
+   pI810DRI->cpp               = ctx->bpp / 8;
+   pI810DRI->bitsPerPixel      = ctx->bpp;
+   pI810DRI->fbOffset          = info->FrontBuffer.Start;
+   pI810DRI->fbStride          = info->auxPitch;
+   
+   pI810DRI->backOffset        = info->BackBuffer.Start;
+   pI810DRI->depthOffset       = info->DepthBuffer.Start;
+
+   pI810DRI->auxPitch          = info->auxPitch;
+   pI810DRI->auxPitchBits      = info->auxPitchBits;
+
+   pI810DRI->logTextureGranularity = info->logTextureGranularity;
+   pI810DRI->textureOffset     = info->TexMem.Start;
+  
+   pI810DRI->ringOffset        = info->LpRing.mem.Start;
+   pI810DRI->ringSize          = info->LpRing.mem.Size;
+
+   // drmBufs looks unused 
+   pI810DRI->irq               = info->irq;
+   pI810DRI->sarea_priv_offset = sizeof(drm_sarea_t);
+
+   /* Don't release the lock now - let the VT switch handler do it. */
+   return 1;
+}
+
+
+/**
+ * \brief Validate the fbdev mode.
+ * 
+ * \param ctx display handle.
+ *
+ * \return one on success, or zero on failure.
+ *
+ * Saves some registers and returns 1.
+ *
+ * \sa i810ValidateMode().
+ */
+static int i810ValidateMode( const DRIDriverContext *ctx )
+{
+   unsigned char *I810MMIO = ctx->MMIOAddress;
+   I810Ptr info = ctx->driverPrivate;
+
+   return 1;
+}
+
+
+/**
+ * \brief Examine mode returned by fbdev.
+ * 
+ * \param ctx display handle.
+ *
+ * \return one on success, or zero on failure.
+ *
+ * Restores registers that fbdev has clobbered and returns 1.
+ *
+ * \sa i810ValidateMode().
+ */
+static int i810PostValidateMode( const DRIDriverContext *ctx )
+{
+   unsigned char *I810MMIO = ctx->MMIOAddress;
+   I810Ptr info = ctx->driverPrivate;
+
+   return 1;
+}
+
+
+/**
+ * \brief Initialize the framebuffer device mode
+ *
+ * \param ctx display handle.
+ *
+ * \return one on success, or zero on failure.
+ *
+ * Fills in \p info with some default values and some information from \p ctx
+ * and then calls I810ScreenInit() for the screen initialization.
+ * 
+ * Before exiting clears the framebuffer memory accessing it directly.
+ */
+static int i810InitFBDev( DRIDriverContext *ctx )
+{
+  I810Ptr info = calloc(1, sizeof(*info));
+
+   {
+      int  dummy = ctx->shared.virtualWidth;
+
+      switch (ctx->bpp / 8) {
+      case 1: dummy = (ctx->shared.virtualWidth + 127) & ~127; break;
+      case 2: dummy = (ctx->shared.virtualWidth +  31) &  ~31; break;
+      case 3:
+      case 4: dummy = (ctx->shared.virtualWidth +  15) &  ~15; break;
+      }
+
+      ctx->shared.virtualWidth = dummy;
+   }
+
+   ctx->driverPrivate = (void *)info;
+   
+   info->Chipset = ctx->chipset;
+
+   if (!I810ScreenInit( ctx, info ))
+      return 0;
+
+
+   return 1;
+}
+
+
+/**
+ * \brief The screen is being closed, so clean up any state and free any
+ * resources used by the DRI.
+ *
+ * \param ctx display handle.
+ *
+ * Unmaps the SAREA, closes the DRM device file descriptor and frees the driver
+ * private data.
+ */
+static void i810HaltFBDev( DRIDriverContext *ctx )
+{
+    drmUnmap( ctx->pSAREA, ctx->shared.SAREASize );
+    drmClose(ctx->drmFD);
+
+    if (ctx->driverPrivate) {
+       free(ctx->driverPrivate);
+       ctx->driverPrivate = 0;
+    }
+}
+
+
+extern void i810NotifyFocus( int );
+
+/**
+ * \brief Exported driver interface for Mini GLX.
+ *
+ * \sa DRIDriverRec.
+ */
+const struct DRIDriverRec __driDriver = {
+   i810ValidateMode,
+   i810PostValidateMode,
+   i810InitFBDev,
+   i810HaltFBDev,
+   I810EngineShutdown,
+   I810EngineRestore,  
+#ifndef _EMBEDDED
+   0,
+#else
+   i810NotifyFocus, 
+#endif
+};
diff --git a/src/server/i810_dri.h b/src/server/i810_dri.h
new file mode 100644
index 0000000..408a4eb
--- /dev/null
+++ b/src/server/i810_dri.h
@@ -0,0 +1,128 @@
+/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/i810/i810_dri.h,v 1.10 2002/12/10 01:27:04 dawes Exp $ */
+
+#ifndef _I810_DRI_
+#define _I810_DRI_
+
+#include "xf86drm.h"
+#include "i810_common.h"
+
+#define I810_MAX_DRAWABLES 256
+
+typedef struct {
+   drm_handle_t regs;
+   drmSize regsSize;
+
+   drmSize backbufferSize;
+   drm_handle_t backbuffer;
+
+   drmSize depthbufferSize;
+   drm_handle_t depthbuffer;
+
+   drm_handle_t textures;
+   int textureSize;
+
+   drm_handle_t agp_buffers;
+   drmSize agp_buf_size;
+
+   int deviceID;
+   int width;
+   int height;
+   int mem;
+   int cpp;
+   int bitsPerPixel;
+   int fbOffset;
+   int fbStride;
+
+   int backOffset;
+   int depthOffset;
+
+   int auxPitch;
+   int auxPitchBits;
+
+   int logTextureGranularity;
+   int textureOffset;
+
+   /* For non-dma direct rendering.
+    */
+   int ringOffset;
+   int ringSize;
+
+   drmBufMapPtr drmBufs;
+   int irq;
+   unsigned int sarea_priv_offset;
+
+} I810DRIRec, *I810DRIPtr;
+
+/* WARNING: Do not change the SAREA structure without changing the kernel
+ * as well */
+
+#define I810_UPLOAD_TEX0IMAGE  0x1	/* handled clientside */
+#define I810_UPLOAD_TEX1IMAGE  0x2	/* handled clientside */
+#define I810_UPLOAD_CTX        0x4
+#define I810_UPLOAD_BUFFERS    0x8
+#define I810_UPLOAD_TEX0       0x10
+#define I810_UPLOAD_TEX1       0x20
+#define I810_UPLOAD_CLIPRECTS  0x40
+
+typedef struct {
+   unsigned char next, prev;		/* indices to form a circular LRU  */
+   unsigned char in_use;		/* owned by a client, or free? */
+   int age;				/* tracked by clients to update local LRU's */
+} I810TexRegionRec, *I810TexRegionPtr;
+
+typedef struct {
+   unsigned int ContextState[I810_CTX_SETUP_SIZE];
+   unsigned int BufferState[I810_DEST_SETUP_SIZE];
+   unsigned int TexState[2][I810_TEX_SETUP_SIZE];
+   unsigned int dirty;
+
+   unsigned int nbox;
+   drm_clip_rect_t boxes[I810_NR_SAREA_CLIPRECTS];
+
+   /* Maintain an LRU of contiguous regions of texture space.  If
+    * you think you own a region of texture memory, and it has an
+    * age different to the one you set, then you are mistaken and
+    * it has been stolen by another client.  If global texAge
+    * hasn't changed, there is no need to walk the list.
+    *
+    * These regions can be used as a proxy for the fine-grained
+    * texture information of other clients - by maintaining them
+    * in the same lru which is used to age their own textures,
+    * clients have an approximate lru for the whole of global
+    * texture space, and can make informed decisions as to which
+    * areas to kick out.  There is no need to choose whether to
+    * kick out your own texture or someone else's - simply eject
+    * them all in LRU order.
+    */
+ 
+   drmTextureRegion texList[I810_NR_TEX_REGIONS + 1];
+
+   /* Last elt is sentinal */
+   int texAge;				/* last time texture was uploaded */
+
+   int last_enqueue;			/* last time a buffer was enqueued */
+   int last_dispatch;			/* age of the most recently dispatched buffer */
+   int last_quiescent;			/*  */
+
+   int ctxOwner;			/* last context to upload state */
+
+   int vertex_prim;
+
+   int pf_enabled;                  /* is pageflipping allowed? */
+   int pf_active;                   /* is pageflipping active right now? */
+   int pf_current_page; 	    /* which buffer is being displayed? */
+
+
+} I810SAREARec, *I810SAREAPtr;
+
+typedef struct {
+   /* Nothing here yet */
+   int dummy;
+} I810ConfigPrivRec, *I810ConfigPrivPtr;
+
+typedef struct {
+   /* Nothing here yet */
+   int dummy;
+} I810DRIContextRec, *I810DRIContextPtr;
+
+#endif
diff --git a/src/server/i810_reg.h b/src/server/i810_reg.h
new file mode 100644
index 0000000..c935982
--- /dev/null
+++ b/src/server/i810_reg.h
@@ -0,0 +1,992 @@
+/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/i810/i810_reg.h,v 1.13 2003/02/06 04:18:04 dawes Exp $ */
+/**************************************************************************
+
+Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas.
+All Rights Reserved.
+
+Permission is hereby granted, free of charge, to any person obtaining a
+copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sub license, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial portions
+of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+**************************************************************************/
+
+/*
+ * Authors:
+ *   Keith Whitwell <keith@tungstengraphics.com>
+ *
+ *   based on the i740 driver by
+ *        Kevin E. Martin <kevin@precisioninsight.com> 
+ *   
+ *
+ */
+
+#ifndef _I810_REG_H
+#define _I810_REG_H
+
+/* I/O register offsets
+ */
+#define SRX 0x3C4		/* p208 */
+#define GRX 0x3CE		/* p213 */
+#define ARX 0x3C0		/* p224 */
+
+/* VGA Color Palette Registers */
+#define DACMASK  0x3C6		/* p232 */
+#define DACSTATE 0x3C7		/* p232 */
+#define DACRX    0x3C7		/* p233 */
+#define DACWX    0x3C8		/* p233 */
+#define DACDATA  0x3C9		/* p233 */
+
+/* CRT Controller Registers (CRX) */
+#define START_ADDR_HI        0x0C /* p246 */
+#define START_ADDR_LO        0x0D /* p247 */
+#define VERT_SYNC_END        0x11 /* p249 */
+#define EXT_VERT_TOTAL       0x30 /* p257 */
+#define EXT_VERT_DISPLAY     0x31 /* p258 */
+#define EXT_VERT_SYNC_START  0x32 /* p259 */
+#define EXT_VERT_BLANK_START 0x33 /* p260 */
+#define EXT_HORIZ_TOTAL      0x35 /* p261 */
+#define EXT_HORIZ_BLANK      0x39 /* p261 */
+#define EXT_START_ADDR       0x40 /* p262 */
+#define EXT_START_ADDR_ENABLE    0x80 
+#define EXT_OFFSET           0x41 /* p263 */
+#define EXT_START_ADDR_HI    0x42 /* p263 */
+#define INTERLACE_CNTL       0x70 /* p264 */
+#define INTERLACE_ENABLE         0x80 
+#define INTERLACE_DISABLE        0x00 
+
+/* Miscellaneous Output Register 
+ */
+#define MSR_R          0x3CC	/* p207 */
+#define MSR_W          0x3C2	/* p207 */
+#define IO_ADDR_SELECT     0x01
+
+#define MDA_BASE       0x3B0	/* p207 */
+#define CGA_BASE       0x3D0	/* p207 */
+
+/* CR80 - IO Control, p264
+ */
+#define IO_CTNL            0x80
+#define EXTENDED_ATTR_CNTL     0x02
+#define EXTENDED_CRTC_CNTL     0x01
+
+/* GR10 - Address mapping, p221
+ */
+#define ADDRESS_MAPPING    0x10
+#define PAGE_TO_LOCAL_MEM_ENABLE 0x10
+#define GTT_MEM_MAP_ENABLE     0x08
+#define PACKED_MODE_ENABLE     0x04
+#define LINEAR_MODE_ENABLE     0x02
+#define PAGE_MAPPING_ENABLE    0x01
+
+/* Blitter control, p378
+ */
+#define BITBLT_CNTL        0x7000c
+#define COLEXP_MODE            0x30
+#define COLEXP_8BPP            0x00
+#define COLEXP_16BPP           0x10
+#define COLEXP_24BPP           0x20
+#define COLEXP_RESERVED        0x30
+#define BITBLT_STATUS          0x01
+
+/* p375. 
+ */
+#define DISPLAY_CNTL       0x70008
+#define VGA_WRAP_MODE          0x02
+#define VGA_WRAP_AT_256KB      0x00
+#define VGA_NO_WRAP            0x02
+#define GUI_MODE               0x01
+#define STANDARD_VGA_MODE      0x00
+#define HIRES_MODE             0x01
+
+/* p375
+ */
+#define PIXPIPE_CONFIG_0   0x70009
+#define DAC_8_BIT              0x80
+#define DAC_6_BIT              0x00
+#define HW_CURSOR_ENABLE       0x10
+#define EXTENDED_PALETTE       0x01
+
+/* p375
+ */
+#define PIXPIPE_CONFIG_1   0x7000a
+#define DISPLAY_COLOR_MODE     0x0F
+#define DISPLAY_VGA_MODE       0x00
+#define DISPLAY_8BPP_MODE      0x02
+#define DISPLAY_15BPP_MODE     0x04
+#define DISPLAY_16BPP_MODE     0x05
+#define DISPLAY_24BPP_MODE     0x06
+#define DISPLAY_32BPP_MODE     0x07
+
+/* p375
+ */
+#define PIXPIPE_CONFIG_2   0x7000b
+#define DISPLAY_GAMMA_ENABLE   0x08
+#define DISPLAY_GAMMA_DISABLE  0x00
+#define OVERLAY_GAMMA_ENABLE   0x04
+#define OVERLAY_GAMMA_DISABLE  0x00
+
+
+/* p380
+ */
+#define DISPLAY_BASE       0x70020
+#define DISPLAY_BASE_MASK  0x03fffffc
+
+
+/* Cursor control registers, pp383-384
+ */
+/* Desktop (845G, 865G) */
+#define CURSOR_CONTROL     0x70080
+#define CURSOR_ENABLE          0x80000000
+#define CURSOR_GAMMA_ENABLE    0x40000000
+#define CURSOR_STRIDE_MASK     0x30000000
+#define CURSOR_FORMAT_SHIFT    24
+#define CURSOR_FORMAT_MASK     (0x07 << CURSOR_FORMAT_SHIFT)
+#define CURSOR_FORMAT_2C       (0x00 << CURSOR_FORMAT_SHIFT)
+#define CURSOR_FORMAT_3C       (0x01 << CURSOR_FORMAT_SHIFT)
+#define CURSOR_FORMAT_4C       (0x02 << CURSOR_FORMAT_SHIFT)
+#define CURSOR_FORMAT_ARGB     (0x04 << CURSOR_FORMAT_SHIFT)
+#define CURSOR_FORMAT_XRGB     (0x05 << CURSOR_FORMAT_SHIFT)
+
+/* Mobile and i810 */
+#define CURSOR_A_CONTROL   CURSOR_CONTROL
+#define CURSOR_ORIGIN_SCREEN   0x00	/* i810 only */
+#define CURSOR_ORIGIN_DISPLAY  0x1	/* i810 only */
+#define CURSOR_MODE            0x27
+#define CURSOR_MODE_DISABLE    0x00
+#define CURSOR_MODE_32_4C_AX   0x01	/* i810 only */
+#define CURSOR_MODE_64_3C      0x04
+#define CURSOR_MODE_64_4C_AX   0x05
+#define CURSOR_MODE_64_4C      0x06
+#define CURSOR_MODE_64_32B_AX  0x07
+#define CURSOR_MODE_64_ARGB_AX (0x20 | CURSOR_MODE_64_32B_AX)
+#define MCURSOR_PIPE_SELECT    (1 << 28)
+#define MCURSOR_PIPE_A         0x00
+#define MCURSOR_PIPE_B         (1 << 28)
+#define MCURSOR_GAMMA_ENABLE   (1 << 26)
+#define MCURSOR_MEM_TYPE_LOCAL (1 << 25)
+
+
+#define CURSOR_BASEADDR    0x70084
+#define CURSOR_A_BASE      CURSOR_BASEADDR
+#define CURSOR_BASEADDR_MASK 0x1FFFFF00
+#define CURSOR_A_POSITION  0x70088
+#define CURSOR_POS_SIGN        0x8000
+#define CURSOR_POS_MASK        0x007FF
+#define CURSOR_X_SHIFT	       0
+#define CURSOR_Y_SHIFT         16
+#define CURSOR_X_LO        0x70088
+#define CURSOR_X_HI        0x70089
+#define CURSOR_X_POS           0x00
+#define CURSOR_X_NEG           0x80
+#define CURSOR_Y_LO        0x7008A
+#define CURSOR_Y_HI        0x7008B
+#define CURSOR_Y_POS           0x00
+#define CURSOR_Y_NEG           0x80
+
+#define CURSOR_A_PALETTE0  0x70090
+#define CURSOR_A_PALETTE1  0x70094
+#define CURSOR_A_PALETTE2  0x70098
+#define CURSOR_A_PALETTE3  0x7009C
+
+#define CURSOR_SIZE	   0x700A0
+#define CURSOR_SIZE_MASK       0x3FF
+#define CURSOR_SIZE_HSHIFT     0
+#define CURSOR_SIZE_VSHIFT     12
+
+
+/* Similar registers exist in Device 0 on the i810 (pp55-65), but I'm
+ * not sure they refer to local (graphics) memory.
+ *
+ * These details are for the local memory control registers,
+ * (pp301-310).  The test machines are not equiped with local memory,
+ * so nothing is tested.  Only a single row seems to be supported.
+ */
+#define DRAM_ROW_TYPE      0x3000
+#define DRAM_ROW_0             0x01
+#define DRAM_ROW_0_SDRAM       0x01
+#define DRAM_ROW_0_EMPTY       0x00
+#define DRAM_ROW_CNTL_LO   0x3001
+#define DRAM_PAGE_MODE_CTRL    0x10
+#define DRAM_RAS_TO_CAS_OVRIDE 0x08
+#define DRAM_CAS_LATENCY       0x04
+#define DRAM_RAS_TIMING        0x02
+#define DRAM_RAS_PRECHARGE     0x01
+#define DRAM_ROW_CNTL_HI   0x3002
+#define DRAM_REFRESH_RATE      0x18
+#define DRAM_REFRESH_DISABLE   0x00
+#define DRAM_REFRESH_60HZ      0x08
+#define DRAM_REFRESH_FAST_TEST 0x10
+#define DRAM_REFRESH_RESERVED  0x18
+#define DRAM_SMS               0x07
+#define DRAM_SMS_NORMAL        0x00
+#define DRAM_SMS_NOP_ENABLE    0x01
+#define DRAM_SMS_ABPCE         0x02
+#define DRAM_SMS_MRCE          0x03
+#define DRAM_SMS_CBRCE         0x04
+
+/* p307
+ */
+#define DPMS_SYNC_SELECT   0x5002
+#define VSYNC_CNTL             0x08
+#define VSYNC_ON               0x00
+#define VSYNC_OFF              0x08
+#define HSYNC_CNTL             0x02
+#define HSYNC_ON               0x00
+#define HSYNC_OFF              0x02
+
+
+
+/* p317, 319
+ */
+#define VCLK2_VCO_M        0x6008 /* treat as 16 bit? (includes msbs) */
+#define VCLK2_VCO_N        0x600a
+#define VCLK2_VCO_DIV_SEL  0x6012
+
+#define VCLK_DIVISOR_VGA0   0x6000
+#define VCLK_DIVISOR_VGA1   0x6004
+#define VCLK_POST_DIV	    0x6010
+
+#define POST_DIV_SELECT        0x70
+#define POST_DIV_1             0x00
+#define POST_DIV_2             0x10
+#define POST_DIV_4             0x20
+#define POST_DIV_8             0x30
+#define POST_DIV_16            0x40
+#define POST_DIV_32            0x50
+#define VCO_LOOP_DIV_BY_4M     0x00
+#define VCO_LOOP_DIV_BY_16M    0x04
+
+
+/* Instruction Parser Mode Register 
+ *    - p281
+ *    - 2 new bits.
+ */
+#define INST_PM                  0x20c0	
+#define AGP_SYNC_PACKET_FLUSH_ENABLE 0x20 /* reserved */
+#define SYNC_PACKET_FLUSH_ENABLE     0x10
+#define TWO_D_INST_DISABLE           0x08
+#define THREE_D_INST_DISABLE         0x04
+#define STATE_VAR_UPDATE_DISABLE     0x02
+#define PAL_STIP_DISABLE             0x01
+
+#define INST_DONE                0x2090
+#define INST_PS                  0x20c4
+
+#define MEMMODE                  0x20dc
+
+
+/* Instruction parser error register.  p279
+ */
+#define IPEIR                  0x2088
+#define IPEHR                  0x208C
+
+
+/* General error reporting regs, p296
+ */
+#define EIR               0x20B0
+#define EMR               0x20B4
+#define ESR               0x20B8
+#define IP_ERR                    0x0001
+#define ERROR_RESERVED            0xffc6
+
+
+/* Interrupt Control Registers 
+ *   - new bits for i810
+ *   - new register hwstam (mask)
+ */
+#define HWSTAM               0x2098 /* p290 */
+#define IER                  0x20a0 /* p291 */
+#define IIR                  0x20a4 /* p292 */
+#define IMR                  0x20a8 /* p293 */
+#define ISR                  0x20ac /* p294 */
+#define HW_ERROR                 0x8000
+#define SYNC_STATUS_TOGGLE       0x1000
+#define DPY_0_FLIP_PENDING       0x0800
+#define DPY_1_FLIP_PENDING       0x0400	/* not implemented on i810 */
+#define OVL_0_FLIP_PENDING       0x0200
+#define OVL_1_FLIP_PENDING       0x0100	/* not implemented on i810 */
+#define DPY_0_VBLANK             0x0080
+#define DPY_0_EVENT              0x0040
+#define DPY_1_VBLANK             0x0020	/* not implemented on i810 */
+#define DPY_1_EVENT              0x0010	/* not implemented on i810 */
+#define HOST_PORT_EVENT          0x0008	/*  */
+#define CAPTURE_EVENT            0x0004	/*  */
+#define USER_DEFINED             0x0002
+#define BREAKPOINT               0x0001
+
+
+#define INTR_RESERVED            (0x6000 | 		\
+				  DPY_1_FLIP_PENDING |	\
+				  OVL_1_FLIP_PENDING |	\
+				  DPY_1_VBLANK |	\
+				  DPY_1_EVENT |		\
+				  HOST_PORT_EVENT |	\
+				  CAPTURE_EVENT )
+
+/* FIFO Watermark and Burst Length Control Register 
+ *
+ * - different offset and contents on i810 (p299) (fewer bits per field)
+ * - some overlay fields added
+ * - what does it all mean?
+ */
+#define FWATER_BLC       0x20d8
+#define FWATER_BLC2	 0x20dc
+#define MM_BURST_LENGTH     0x00700000
+#define MM_FIFO_WATERMARK   0x0001F000
+#define LM_BURST_LENGTH     0x00000700
+#define LM_FIFO_WATERMARK   0x0000001F
+
+
+/* Fence/Tiling ranges [0..7]
+ */
+#define FENCE            0x2000
+#define FENCE_NR         8
+
+#define I830_FENCE_START_MASK	0x07f80000
+
+#define FENCE_START_MASK    0x03F80000
+#define FENCE_X_MAJOR       0x00000000
+#define FENCE_Y_MAJOR       0x00001000
+#define FENCE_SIZE_MASK     0x00000700
+#define FENCE_SIZE_512K     0x00000000
+#define FENCE_SIZE_1M       0x00000100
+#define FENCE_SIZE_2M       0x00000200
+#define FENCE_SIZE_4M       0x00000300
+#define FENCE_SIZE_8M       0x00000400
+#define FENCE_SIZE_16M      0x00000500
+#define FENCE_SIZE_32M      0x00000600
+#define FENCE_SIZE_64M	    0x00000700
+#define FENCE_PITCH_MASK    0x00000070
+#define FENCE_PITCH_1       0x00000000
+#define FENCE_PITCH_2       0x00000010
+#define FENCE_PITCH_4       0x00000020
+#define FENCE_PITCH_8       0x00000030
+#define FENCE_PITCH_16      0x00000040
+#define FENCE_PITCH_32      0x00000050
+#define FENCE_PITCH_64	    0x00000060
+#define FENCE_VALID         0x00000001
+
+
+/* Registers to control page table, p274
+ */
+#define PGETBL_CTL       0x2020
+#define PGETBL_ADDR_MASK    0xFFFFF000
+#define PGETBL_ENABLE_MASK  0x00000001
+#define PGETBL_ENABLED      0x00000001
+
+/* Register containing pge table error results, p276
+ */
+#define PGE_ERR          0x2024
+#define PGE_ERR_ADDR_MASK   0xFFFFF000
+#define PGE_ERR_ID_MASK     0x00000038
+#define PGE_ERR_CAPTURE     0x00000000
+#define PGE_ERR_OVERLAY     0x00000008
+#define PGE_ERR_DISPLAY     0x00000010
+#define PGE_ERR_HOST        0x00000018
+#define PGE_ERR_RENDER      0x00000020
+#define PGE_ERR_BLITTER     0x00000028
+#define PGE_ERR_MAPPING     0x00000030
+#define PGE_ERR_CMD_PARSER  0x00000038
+#define PGE_ERR_TYPE_MASK   0x00000007
+#define PGE_ERR_INV_TABLE   0x00000000
+#define PGE_ERR_INV_PTE     0x00000001
+#define PGE_ERR_MIXED_TYPES 0x00000002
+#define PGE_ERR_PAGE_MISS   0x00000003
+#define PGE_ERR_ILLEGAL_TRX 0x00000004
+#define PGE_ERR_LOCAL_MEM   0x00000005
+#define PGE_ERR_TILED       0x00000006
+
+
+
+/* Page table entries loaded via mmio region, p323
+ */
+#define PTE_BASE         0x10000
+#define PTE_ADDR_MASK       0x3FFFF000
+#define PTE_TYPE_MASK       0x00000006
+#define PTE_LOCAL           0x00000002
+#define PTE_MAIN_UNCACHED   0x00000000
+#define PTE_MAIN_CACHED     0x00000006
+#define PTE_VALID_MASK      0x00000001
+#define PTE_VALID           0x00000001
+
+
+/* Ring buffer registers, p277, overview p19
+ */
+#define LP_RING     0x2030
+#define HP_RING     0x2040
+
+#define RING_TAIL      0x00
+#define TAIL_ADDR           0x000FFFF8
+#define I830_TAIL_MASK	    0x001FFFF8
+
+#define RING_HEAD      0x04
+#define HEAD_WRAP_COUNT     0xFFE00000
+#define HEAD_WRAP_ONE       0x00200000
+#define HEAD_ADDR           0x001FFFFC
+#define I830_HEAD_MASK      0x001FFFFC
+
+#define RING_START     0x08
+#define START_ADDR          0x00FFFFF8
+#define I830_RING_START_MASK	0xFFFFF000
+
+#define RING_LEN       0x0C
+#define RING_NR_PAGES       0x000FF000 
+#define I830_RING_NR_PAGES	0x001FF000
+#define RING_REPORT_MASK    0x00000006
+#define RING_REPORT_64K     0x00000002
+#define RING_REPORT_128K    0x00000004
+#define RING_NO_REPORT      0x00000000
+#define RING_VALID_MASK     0x00000001
+#define RING_VALID          0x00000001
+#define RING_INVALID        0x00000000
+
+
+
+/* BitBlt Instructions
+ *
+ * There are many more masks & ranges yet to add.
+ */
+#define BR00_BITBLT_CLIENT   0x40000000
+#define BR00_OP_COLOR_BLT    0x10000000
+#define BR00_OP_SRC_COPY_BLT 0x10C00000
+#define BR00_OP_FULL_BLT     0x11400000
+#define BR00_OP_MONO_SRC_BLT 0x11800000
+#define BR00_OP_MONO_SRC_COPY_BLT 0x11000000
+#define BR00_OP_MONO_PAT_BLT 0x11C00000
+#define BR00_OP_MONO_SRC_COPY_IMMEDIATE_BLT (0x61 << 22)
+#define BR00_OP_TEXT_IMMEDIATE_BLT 0xc000000
+
+
+#define BR00_TPCY_DISABLE    0x00000000
+#define BR00_TPCY_ENABLE     0x00000010
+
+#define BR00_TPCY_ROP        0x00000000
+#define BR00_TPCY_NO_ROP     0x00000020
+#define BR00_TPCY_EQ         0x00000000
+#define BR00_TPCY_NOT_EQ     0x00000040
+
+#define BR00_PAT_MSB_FIRST   0x00000000	/* ? */
+
+#define BR00_PAT_VERT_ALIGN  0x000000e0
+
+#define BR00_LENGTH          0x0000000F
+
+#define BR09_DEST_ADDR       0x03FFFFFF
+
+#define BR11_SOURCE_PITCH    0x00003FFF
+
+#define BR12_SOURCE_ADDR     0x03FFFFFF
+
+#define BR13_SOLID_PATTERN   0x80000000
+#define BR13_RIGHT_TO_LEFT   0x40000000
+#define BR13_LEFT_TO_RIGHT   0x00000000
+#define BR13_MONO_TRANSPCY   0x20000000
+#define BR13_USE_DYN_DEPTH   0x04000000
+#define BR13_DYN_8BPP        0x00000000
+#define BR13_DYN_16BPP       0x01000000
+#define BR13_DYN_24BPP       0x02000000
+#define BR13_ROP_MASK        0x00FF0000
+#define BR13_DEST_PITCH      0x0000FFFF
+#define BR13_PITCH_SIGN_BIT  0x00008000
+
+#define BR14_DEST_HEIGHT     0xFFFF0000
+#define BR14_DEST_WIDTH      0x0000FFFF
+
+#define BR15_PATTERN_ADDR    0x03FFFFFF
+
+#define BR16_SOLID_PAT_COLOR 0x00FFFFFF
+#define BR16_BACKGND_PAT_CLR 0x00FFFFFF
+
+#define BR17_FGND_PAT_CLR    0x00FFFFFF
+
+#define BR18_SRC_BGND_CLR    0x00FFFFFF
+#define BR19_SRC_FGND_CLR    0x00FFFFFF
+
+
+/* Instruction parser instructions
+ */
+
+#define INST_PARSER_CLIENT   0x00000000
+#define INST_OP_FLUSH        0x02000000
+#define INST_FLUSH_MAP_CACHE 0x00000001
+
+
+#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
+
+
+/* Registers in the i810 host-pci bridge pci config space which affect
+ * the i810 graphics operations.  
+ */
+#define SMRAM_MISCC         0x70
+#define GMS                    0x000000c0
+#define GMS_DISABLE            0x00000000
+#define GMS_ENABLE_BARE        0x00000040
+#define GMS_ENABLE_512K        0x00000080
+#define GMS_ENABLE_1M          0x000000c0
+#define USMM                   0x00000030 
+#define USMM_DISABLE           0x00000000
+#define USMM_TSEG_ZERO         0x00000010
+#define USMM_TSEG_512K         0x00000020
+#define USMM_TSEG_1M           0x00000030  
+#define GFX_MEM_WIN_SIZE       0x00010000
+#define GFX_MEM_WIN_32M        0x00010000
+#define GFX_MEM_WIN_64M        0x00000000
+
+/* Overkill?  I don't know.  Need to figure out top of mem to make the
+ * SMRAM calculations come out.  Linux seems to have problems
+ * detecting it all on its own, so this seems a reasonable double
+ * check to any user supplied 'mem=...' boot param.
+ *
+ * ... unfortunately this reg doesn't work according to spec on the
+ * test hardware.
+ */
+#define WHTCFG_PAMR_DRP      0x50
+#define SYS_DRAM_ROW_0_SHIFT    16
+#define SYS_DRAM_ROW_1_SHIFT    20
+#define DRAM_MASK           0x0f
+#define DRAM_VALUE_0        0
+#define DRAM_VALUE_1        8
+/* No 2 value defined */
+#define DRAM_VALUE_3        16
+#define DRAM_VALUE_4        16
+#define DRAM_VALUE_5        24
+#define DRAM_VALUE_6        32
+#define DRAM_VALUE_7        32
+#define DRAM_VALUE_8        48
+#define DRAM_VALUE_9        64
+#define DRAM_VALUE_A        64
+#define DRAM_VALUE_B        96
+#define DRAM_VALUE_C        128
+#define DRAM_VALUE_D        128
+#define DRAM_VALUE_E        192
+#define DRAM_VALUE_F        256	/* nice one, geezer */
+#define LM_FREQ_MASK        0x10
+#define LM_FREQ_133         0x10
+#define LM_FREQ_100         0x00
+
+
+
+
+/* These are 3d state registers, but the state is invarient, so we let
+ * the X server handle it:
+ */
+
+
+
+/* GFXRENDERSTATE_COLOR_CHROMA_KEY, p135
+ */
+#define GFX_OP_COLOR_CHROMA_KEY  ((0x3<<29)|(0x1d<<24)|(0x2<<16)|0x1)
+#define CC1_UPDATE_KILL_WRITE    (1<<28)
+#define CC1_ENABLE_KILL_WRITE    (1<<27)
+#define CC1_DISABLE_KILL_WRITE    0
+#define CC1_UPDATE_COLOR_IDX     (1<<26)
+#define CC1_UPDATE_CHROMA_LOW    (1<<25)
+#define CC1_UPDATE_CHROMA_HI     (1<<24)
+#define CC1_CHROMA_LOW_MASK      ((1<<24)-1)
+#define CC2_COLOR_IDX_SHIFT      24
+#define CC2_COLOR_IDX_MASK       (0xff<<24)
+#define CC2_CHROMA_HI_MASK       ((1<<24)-1)
+
+
+#define GFX_CMD_CONTEXT_SEL      ((0<<29)|(0x5<<23))
+#define CS_UPDATE_LOAD           (1<<17)
+#define CS_UPDATE_USE            (1<<16)
+#define CS_UPDATE_LOAD           (1<<17)
+#define CS_LOAD_CTX0             0
+#define CS_LOAD_CTX1             (1<<8)
+#define CS_USE_CTX0              0
+#define CS_USE_CTX1              (1<<0)
+
+/* I810 LCD/TV registers */
+#define LCD_TV_HTOTAL	0x60000
+#define LCD_TV_C	0x60018
+#define LCD_TV_OVRACT   0x6001C
+
+#define LCD_TV_ENABLE (1 << 31)
+#define LCD_TV_VGAMOD (1 << 28)
+
+/* I830 CRTC registers */
+#define HTOTAL_A	0x60000
+#define HBLANK_A	0x60004
+#define HSYNC_A 	0x60008
+#define VTOTAL_A	0x6000c
+#define VBLANK_A	0x60010
+#define VSYNC_A 	0x60014
+#define PIPEASRC	0x6001c
+#define BCLRPAT_A	0x60020
+
+#define HTOTAL_B	0x61000
+#define HBLANK_B	0x61004
+#define HSYNC_B 	0x61008
+#define VTOTAL_B	0x6100c
+#define VBLANK_B	0x61010
+#define VSYNC_B 	0x61014
+#define PIPEBSRC	0x6101c
+#define BCLRPAT_B	0x61020
+
+#define DPLL_A		0x06014
+#define DPLL_B		0x06018
+#define FPA0		0x06040
+#define FPA1		0x06044
+
+#define I830_HTOTAL_MASK 	0xfff0000
+#define I830_HACTIVE_MASK	0x7ff
+
+#define I830_HBLANKEND_MASK	0xfff0000
+#define I830_HBLANKSTART_MASK    0xfff
+
+#define I830_HSYNCEND_MASK	0xfff0000
+#define I830_HSYNCSTART_MASK    0xfff
+
+#define I830_VTOTAL_MASK 	0xfff0000
+#define I830_VACTIVE_MASK	0x7ff
+
+#define I830_VBLANKEND_MASK	0xfff0000
+#define I830_VBLANKSTART_MASK    0xfff
+
+#define I830_VSYNCEND_MASK	0xfff0000
+#define I830_VSYNCSTART_MASK    0xfff
+
+#define I830_PIPEA_HORZ_MASK	0x7ff0000
+#define I830_PIPEA_VERT_MASK	0x7ff
+
+#define ADPA			0x61100
+#define ADPA_DAC_ENABLE 	(1<<31)
+#define ADPA_DAC_DISABLE	0
+#define ADPA_PIPE_SELECT_MASK	(1<<30)
+#define ADPA_PIPE_A_SELECT	0
+#define ADPA_PIPE_B_SELECT	(1<<30)
+#define ADPA_USE_VGA_HVPOLARITY (1<<15)
+#define ADPA_SETS_HVPOLARITY	0
+#define ADPA_VSYNC_CNTL_DISABLE (1<<11)
+#define ADPA_VSYNC_CNTL_ENABLE	0
+#define ADPA_HSYNC_CNTL_DISABLE (1<<10)
+#define ADPA_HSYNC_CNTL_ENABLE	0
+#define ADPA_VSYNC_ACTIVE_HIGH	(1<<4)
+#define ADPA_VSYNC_ACTIVE_LOW	0
+#define ADPA_HSYNC_ACTIVE_HIGH	(1<<3)
+#define ADPA_HSYNC_ACTIVE_LOW	0
+
+
+#define DVOA			0x61120
+#define DVOB			0x61140
+#define DVOC			0x61160
+#define DVO_ENABLE		(1<<31)
+
+#define DVOA_SRCDIM		0x61124
+#define DVOB_SRCDIM		0x61144
+#define DVOC_SRCDIM		0x61164
+
+#define LVDS			0x61180
+
+#define PIPEACONF 0x70008
+#define PIPEACONF_ENABLE	(1<<31)
+#define PIPEACONF_DISABLE	0
+#define PIPEACONF_DOUBLE_WIDE	(1<<30)
+#define PIPEACONF_SINGLE_WIDE	0
+#define PIPEACONF_PIPE_UNLOCKED 0
+#define PIPEACONF_PIPE_LOCKED	(1<<25)
+#define PIPEACONF_PALETTE	0
+#define PIPEACONF_GAMMA 	(1<<24)
+
+#define PIPEBCONF 0x71008
+#define PIPEBCONF_ENABLE	(1<<31)
+#define PIPEBCONF_DISABLE	0
+#define PIPEBCONF_GAMMA 	(1<<24)
+#define PIPEBCONF_PALETTE	0
+
+#define DSPACNTR		0x70180
+#define DSPBCNTR		0x71180
+#define DISPLAY_PLANE_ENABLE 			(1<<31)
+#define DISPLAY_PLANE_DISABLE			0
+#define DISPPLANE_GAMMA_ENABLE			(1<<30)
+#define DISPPLANE_GAMMA_DISABLE			0
+#define DISPPLANE_PIXFORMAT_MASK		(0xf<<26)
+#define DISPPLANE_8BPP				(0x2<<26)
+#define DISPPLANE_15_16BPP			(0x4<<26)
+#define DISPPLANE_16BPP				(0x5<<26)
+#define DISPPLANE_32BPP_NO_ALPHA 		(0x6<<26)
+#define DISPPLANE_32BPP				(0x7<<26)
+#define DISPPLANE_STEREO_ENABLE			(1<<25)
+#define DISPPLANE_STEREO_DISABLE		0
+#define DISPPLANE_SEL_PIPE_MASK			(1<<24)
+#define DISPPLANE_SEL_PIPE_A			0
+#define DISPPLANE_SEL_PIPE_B			(1<<24)
+#define DISPPLANE_SRC_KEY_ENABLE		(1<<22)
+#define DISPPLANE_SRC_KEY_DISABLE		0
+#define DISPPLANE_LINE_DOUBLE			(1<<20)
+#define DISPPLANE_NO_LINE_DOUBLE		0
+#define DISPPLANE_STEREO_POLARITY_FIRST		0
+#define DISPPLANE_STEREO_POLARITY_SECOND	(1<<18)
+/* plane B only */
+#define DISPPLANE_ALPHA_TRANS_ENABLE		(1<<15)
+#define DISPPLANE_ALPHA_TRANS_DISABLE		0
+#define DISPPLANE_SPRITE_ABOVE_DISPLAYA		0
+#define DISPPLANE_SPRITE_ABOVE_OVERLAY		(1)
+
+#define DSPABASE		0x70184
+#define DSPASTRIDE		0x70188
+
+#define DSPBBASE		0x71184
+#define DSPBADDR		DSPBBASE
+#define DSPBSTRIDE		0x71188
+
+/* Various masks for reserved bits, etc. */
+#define I830_FWATER1_MASK        (~((1<<11)|(1<<10)|(1<<9)|      \
+        (1<<8)|(1<<26)|(1<<25)|(1<<24)|(1<<5)|(1<<4)|(1<<3)|    \
+        (1<<2)|(1<<1)|1|(1<<20)|(1<<19)|(1<<18)|(1<<17)|(1<<16)))
+#define I830_FWATER2_MASK ~(0)
+
+#define DV0A_RESERVED ((1<<26)|(1<<25)|(1<<24)|(1<<23)|(1<<22)|(1<<21)|(1<<20)|(1<<19)|(1<<18)|(1<<16)|(1<<5)|(1<<1)|1)
+#define DV0B_RESERVED ((1<<27)|(1<<26)|(1<<25)|(1<<24)|(1<<23)|(1<<22)|(1<<21)|(1<<20)|(1<<19)|(1<<18)|(1<<16)|(1<<5)|(1<<1)|1)
+#define VGA0_N_DIVISOR_MASK     ((1<<21)|(1<<20)|(1<<19)|(1<<18)|(1<<17)|(1<<16))
+#define VGA0_M1_DIVISOR_MASK    ((1<<13)|(1<<12)|(1<<11)|(1<<10)|(1<<9)|(1<<8))
+#define VGA0_M2_DIVISOR_MASK    ((1<<5)|(1<<4)|(1<<3)|(1<<2)|(1<<1)|1)
+#define VGA0_M1M2N_RESERVED	~(VGA0_N_DIVISOR_MASK|VGA0_M1_DIVISOR_MASK|VGA0_M2_DIVISOR_MASK)
+#define VGA0_POSTDIV_MASK       ((1<<7)|(1<<5)|(1<<4)|(1<<3)|(1<<2)|(1<<1)|1)
+#define VGA1_POSTDIV_MASK       ((1<<15)|(1<<13)|(1<<12)|(1<<11)|(1<<10)|(1<<9)|(1<<8))
+#define VGA_POSTDIV_RESERVED	~(VGA0_POSTDIV_MASK|VGA1_POSTDIV_MASK|(1<<7)|(1<<15))
+#define DPLLA_POSTDIV_MASK ((1<<23)|(1<<21)|(1<<20)|(1<<19)|(1<<18)|(1<<17)|(1<<16))
+#define DPLLA_RESERVED     ((1<<27)|(1<<26)|(1<<25)|(1<<24)|(1<<22)|(1<<15)|(1<<12)|(1<<11)|(1<<10)|(1<<9)|(1<<8)|(1<<7)|(1<<6)|(1<<5)|(1<<4)|(1<<3)|(1<<2)|(1<<1)|1)
+#define ADPA_RESERVED	((1<<2)|(1<<1)|1|(1<<9)|(1<<8)|(1<<7)|(1<<6)|(1<<5)|(1<<30)|(1<<29)|(1<<28)|(1<<27)|(1<<26)|(1<<25)|(1<<24)|(1<<23)|(1<<22)|(1<<21)|(1<<20)|(1<<19)|(1<<18)|(1<<17)|(1<<16))
+#define SUPER_WORD              32
+#define BURST_A_MASK    ((1<<11)|(1<<10)|(1<<9)|(1<<8))
+#define BURST_B_MASK    ((1<<26)|(1<<25)|(1<<24))
+#define WATER_A_MASK    ((1<<5)|(1<<4)|(1<<3)|(1<<2)|(1<<1)|1)
+#define WATER_B_MASK    ((1<<20)|(1<<19)|(1<<18)|(1<<17)|(1<<16))
+#define WATER_RESERVED	((1<<31)|(1<<30)|(1<<29)|(1<<28)|(1<<27)|(1<<23)|(1<<22)|(1<<21)|(1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<7)|(1<<6))
+#define PIPEACONF_RESERVED ((1<<29)|(1<<28)|(1<<27)|(1<<23)|(1<<22)|(1<<21)|(1<<20)|(1<<19)|(1<<18)|(1<<17)|(1<<16)|0xffff)
+#define PIPEBCONF_RESERVED ((1<<30)|(1<<29)|(1<<28)|(1<<27)|(1<<26)|(1<<25)|(1<<23)|(1<<22)|(1<<21)|(1<<20)|(1<<19)|(1<<18)|(1<<17)|(1<<16)|0xffff)
+#define DSPACNTR_RESERVED ((1<<23)|(1<<19)|(1<<17)|(1<<16)|0xffff)
+#define DSPBCNTR_RESERVED ((1<<23)|(1<<19)|(1<<17)|(1<<16)|0x7ffe)
+
+#define I830_GMCH_CTRL		0x52
+
+#define I830_GMCH_ENABLED	0x4
+#define I830_GMCH_MEM_MASK	0x1
+#define I830_GMCH_MEM_64M	0x1
+#define I830_GMCH_MEM_128M	0
+
+#define I830_GMCH_GMS_MASK			0x70
+#define I830_GMCH_GMS_DISABLED		0x00
+#define I830_GMCH_GMS_LOCAL			0x10
+#define I830_GMCH_GMS_STOLEN_512	0x20
+#define I830_GMCH_GMS_STOLEN_1024	0x30
+#define I830_GMCH_GMS_STOLEN_8192	0x40
+
+#define I830_RDRAM_CHANNEL_TYPE		0x03010
+#define I830_RDRAM_ND(x)			(((x) & 0x20) >> 5)
+#define I830_RDRAM_DDT(x)			(((x) & 0x18) >> 3)
+
+#define I855_GMCH_GMS_MASK			(0x7 << 4)
+#define I855_GMCH_GMS_DISABLED			0x00
+#define I855_GMCH_GMS_STOLEN_1M			(0x1 << 4)
+#define I855_GMCH_GMS_STOLEN_4M			(0x2 << 4)
+#define I855_GMCH_GMS_STOLEN_8M			(0x3 << 4)
+#define I855_GMCH_GMS_STOLEN_16M		(0x4 << 4)
+#define I855_GMCH_GMS_STOLEN_32M		(0x5 << 4)
+
+#define I85X_CAPID			0x44
+#define I85X_VARIANT_MASK			0x7
+#define I85X_VARIANT_SHIFT			5
+#define I855_GME				0x0
+#define I855_GM					0x4
+#define I852_GME				0x2
+#define I852_GM					0x5
+
+/* BLT commands */
+#define COLOR_BLT_CMD		((2<<29)|(0x40<<22)|(0x3))
+#define COLOR_BLT_WRITE_ALPHA	(1<<21)
+#define COLOR_BLT_WRITE_RGB	(1<<20)
+
+#define XY_COLOR_BLT_CMD		((2<<29)|(0x50<<22)|(0x4))
+#define XY_COLOR_BLT_WRITE_ALPHA	(1<<21)
+#define XY_COLOR_BLT_WRITE_RGB		(1<<20)
+
+#define XY_SETUP_CLIP_BLT_CMD		((2<<29)|(3<<22)|1)
+
+#define XY_SRC_COPY_BLT_CMD		((2<<29)|(0x53<<22)|6)
+#define XY_SRC_COPY_BLT_WRITE_ALPHA	(1<<21)
+#define XY_SRC_COPY_BLT_WRITE_RGB	(1<<20)
+
+#define SRC_COPY_BLT_CMD		((2<<29)|(0x43<<22)|0x4)
+#define SRC_COPY_BLT_WRITE_ALPHA	(1<<21)
+#define SRC_COPY_BLT_WRITE_RGB		(1<<20)
+
+#define XY_MONO_PAT_BLT_CMD		((0x2<<29)|(0x52<<22)|0x7)
+#define XY_MONO_PAT_VERT_SEED		((1<<10)|(1<<9)|(1<<8))
+#define XY_MONO_PAT_HORT_SEED		((1<<14)|(1<<13)|(1<<12))
+#define XY_MONO_PAT_BLT_WRITE_ALPHA	(1<<21)
+#define XY_MONO_PAT_BLT_WRITE_RGB	(1<<20)
+
+#define XY_MONO_SRC_BLT_CMD		((0x2<<29)|(0x54<<22)|(0x6))
+#define XY_MONO_SRC_BLT_WRITE_ALPHA	(1<<21)
+#define XY_MONO_SRC_BLT_WRITE_RGB	(1<<20)
+
+/* 3d state */
+#define STATE3D_FOG_MODE		((3<<29)|(0x1d<<24)|(0x89<<16)|2)
+#define FOG_MODE_VERTEX 		(1<<31)
+#define STATE3D_MAP_COORD_TRANSFORM	((3<<29)|(0x1d<<24)|(0x8c<<16))
+#define DISABLE_TEX_TRANSFORM		(1<<28)
+#define TEXTURE_SET(x)			(x<<29)
+#define STATE3D_RASTERIZATION_RULES	((3<<29)|(0x07<<24))
+#define POINT_RASTER_ENABLE		(1<<15)
+#define POINT_RASTER_OGL		(1<<13)
+#define STATE3D_VERTEX_TRANSFORM	((3<<29)|(0x1d<<24)|(0x8b<<16))
+#define DISABLE_VIEWPORT_TRANSFORM	(1<<31)
+#define DISABLE_PERSPECTIVE_DIVIDE	(1<<29)
+
+#define MI_SET_CONTEXT			(0x18<<23)
+#define CTXT_NO_RESTORE 		(1)
+#define CTXT_PALETTE_SAVE_DISABLE	(1<<3)
+#define CTXT_PALETTE_RESTORE_DISABLE	(1<<2)
+
+/* Dword 0 */
+#define MI_VERTEX_BUFFER		(0x17<<23)
+#define MI_VERTEX_BUFFER_IDX(x) 	(x<<20)
+#define MI_VERTEX_BUFFER_PITCH(x)	(x<<13)
+#define MI_VERTEX_BUFFER_WIDTH(x)	(x<<6)
+/* Dword 1 */
+#define MI_VERTEX_BUFFER_DISABLE	(1)
+
+/* Overlay Flip */
+#define MI_OVERLAY_FLIP			(0x11<<23)
+#define MI_OVERLAY_FLIP_CONTINUE	(0<<21)
+#define MI_OVERLAY_FLIP_ON		(1<<21)
+#define MI_OVERLAY_FLIP_OFF		(2<<21)
+
+/* Wait for Events */
+#define MI_WAIT_FOR_EVENT		(0x03<<23)
+#define MI_WAIT_FOR_OVERLAY_FLIP	(1<<16)
+
+/* Flush */
+#define MI_FLUSH			(0x04<<23)
+#define MI_WRITE_DIRTY_STATE		(1<<4)
+#define MI_END_SCENE			(1<<3)
+#define MI_INHIBIT_RENDER_CACHE_FLUSH	(1<<2)
+#define MI_INVALIDATE_MAP_CACHE		(1<<0)
+
+/* Noop */
+#define MI_NOOP				0x00
+#define MI_NOOP_WRITE_ID		(1<<22)
+#define MI_NOOP_ID_MASK			(1<<22 - 1)
+
+#define STATE3D_COLOR_FACTOR	((0x3<<29)|(0x1d<<24)|(0x01<<16))
+
+/* STATE3D_FOG_MODE stuff */
+#define ENABLE_FOG_SOURCE	(1<<27)
+#define ENABLE_FOG_CONST	(1<<24)
+#define ENABLE_FOG_DENSITY	(1<<23)
+
+
+#define MAX_DISPLAY_PIPES	2
+
+typedef enum {
+   CrtIndex = 0,
+   TvIndex,
+   DfpIndex,
+   LfpIndex,
+   Tv2Index,
+   Dfp2Index,
+   UnknownIndex,
+   Unknown2Index,
+   NumDisplayTypes,
+   NumKnownDisplayTypes = UnknownIndex
+} DisplayType;
+
+/* What's connected to the pipes (as reported by the BIOS) */
+#define PIPE_ACTIVE_MASK		0xff
+#define PIPE_CRT_ACTIVE			(1 << CrtIndex)
+#define PIPE_TV_ACTIVE			(1 << TvIndex)
+#define PIPE_DFP_ACTIVE			(1 << DfpIndex)
+#define PIPE_LCD_ACTIVE			(1 << LfpIndex)
+#define PIPE_TV2_ACTIVE			(1 << Tv2Index)
+#define PIPE_DFP2_ACTIVE		(1 << Dfp2Index)
+#define PIPE_UNKNOWN_ACTIVE		((1 << UnknownIndex) |	\
+					 (1 << Unknown2Index))
+
+#define PIPE_SIZED_DISP_MASK		(PIPE_DFP_ACTIVE |	\
+					 PIPE_LCD_ACTIVE |	\
+					 PIPE_DFP2_ACTIVE)
+
+#define PIPE_A_SHIFT			0
+#define PIPE_B_SHIFT			8
+#define PIPE_SHIFT(n)			((n) == 0 ? \
+					 PIPE_A_SHIFT : PIPE_B_SHIFT)
+
+/*
+ * Some BIOS scratch area registers.  The 845 (and 830?) store the amount
+ * of video memory available to the BIOS in SWF1.
+ */
+
+#define SWF0			0x71410
+#define SWF1			0x71414
+#define SWF2			0x71418
+#define SWF3			0x7141c
+#define SWF4			0x71420
+#define SWF5			0x71424
+#define SWF6			0x71428
+
+/*
+ * 855 scratch registers.
+ */
+#define SWF00			0x70410
+#define SWF01			0x70414
+#define SWF02			0x70418
+#define SWF03			0x7041c
+#define SWF04			0x70420
+#define SWF05			0x70424
+#define SWF06			0x70428
+
+#define SWF10			SWF0
+#define SWF11			SWF1
+#define SWF12			SWF2
+#define SWF13			SWF3
+#define SWF14			SWF4
+#define SWF15			SWF5
+#define SWF16			SWF6
+
+#define SWF30			0x72414
+#define SWF31			0x72418
+#define SWF32			0x7241c
+
+/*
+ * Overlay registers.  These are overlay registers accessed via MMIO.
+ * Those loaded via the overlay register page are defined in i830_video.c.
+ */
+#define OVADD			0x30000
+
+#define DOVSTA			0x30008
+#define OC_BUF			(0x3<<20)
+
+#define OGAMC5			0x30010
+#define OGAMC4			0x30014
+#define OGAMC3			0x30018
+#define OGAMC2			0x3001c
+#define OGAMC1			0x30020
+#define OGAMC0			0x30024
+
+
+/*
+ * Palette registers
+ */
+#define PALETTE_A		0x0a000
+#define PALETTE_B		0x0a800
+
+#endif /* _I810_REG_H */