diff options
| author | Zhigang Gong <zhigang.gong@intel.com> | 2014-09-04 08:01:25 +0800 |
|---|---|---|
| committer | Zhigang Gong <zhigang.gong@intel.com> | 2014-09-04 11:53:04 +0800 |
| commit | 9ce75d4de41e8359f411ce5ab3dbd2cd363364b2 (patch) | |
| tree | 96e63bf32d8826d6de3402373fccdb7674399ea8 /src/cl_command_queue.c | |
| parent | 56d2cf2e02b6933478f080548f6960751ff18741 (diff) | |
GBE: fixup/refine a bug for image1D array's extra binding index handling.
Due to hardware limitation on Gen7/Gen75 when sampling a
surface with clamp address mode and nearest filter mode
on a integer image1Darray type surface, we have to bind
one buffer to to bti. The previous implementation hard
coded it to 128 + original index and when check whether
it is such type bti in driver layer, assume the bti reserved
is 3 which is wrong now.
This patch fixed those hard coded functions and use the
macros defined in the program.h.
Signed-off-by: Zhigang Gong <zhigang.gong@intel.com>
Reviewed-by: "Song, Ruiling" <ruiling.song@intel.com>
Diffstat (limited to 'src/cl_command_queue.c')
| -rw-r--r-- | src/cl_command_queue.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/cl_command_queue.c b/src/cl_command_queue.c index 52e91ae4..4cbb4eb8 100644 --- a/src/cl_command_queue.c +++ b/src/cl_command_queue.c @@ -17,6 +17,7 @@ * Author: Benjamin Segovia <benjamin.segovia@intel.com> */ +#include "program.h" // for BTI_MAX_IMAGE_NUM #include "cl_command_queue.h" #include "cl_context.h" #include "cl_program.h" @@ -142,8 +143,10 @@ cl_command_queue_bind_image(cl_command_queue queue, cl_kernel k) image->intel_fmt, image->image_type, image->w, image->h, image->depth, image->row_pitch, (cl_gpgpu_tiling)image->tiling); + // TODO, this workaround is for GEN7/GEN75 only, we may need to do it in the driver layer + // on demand. if (image->image_type == CL_MEM_OBJECT_IMAGE1D_ARRAY) - cl_gpgpu_bind_image(gpgpu, k->images[i].idx + 128, image->base.bo, image->offset, + cl_gpgpu_bind_image(gpgpu, k->images[i].idx + BTI_MAX_IMAGE_NUM, image->base.bo, image->offset, image->intel_fmt, image->image_type, image->w, image->h, image->depth, image->row_pitch, (cl_gpgpu_tiling)image->tiling); |