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-rw-r--r--include/pci_ids/iris_pci_ids.h11
-rw-r--r--src/intel/dev/gen_device_info.c9
2 files changed, 20 insertions, 0 deletions
diff --git a/include/pci_ids/iris_pci_ids.h b/include/pci_ids/iris_pci_ids.h
index 8a2827b0c35..238cfeeb3a5 100644
--- a/include/pci_ids/iris_pci_ids.h
+++ b/include/pci_ids/iris_pci_ids.h
@@ -4,6 +4,17 @@ CHIPSET(0x4c8c, rkl_gt05, "RKL GT0.5", "Intel(R) Graphics")
CHIPSET(0x4c90, rkl_gt1, "RKL GT1", "Intel(R) Graphics")
CHIPSET(0x4c9a, rkl_gt1, "RKL GT1", "Intel(R) Graphics")
+CHIPSET(0x4680, adl_gt1, "ADL-S GT1", "Intel(R) Graphics")
+CHIPSET(0x4681, adl_gt1, "ADL-S GT1", "Intel(R) Graphics")
+CHIPSET(0x4682, adl_gt1, "ADL-S GT1", "Intel(R) Graphics")
+CHIPSET(0x4683, adl_gt05, "ADL-S GT0.5", "Intel(R) Graphics")
+CHIPSET(0x4690, adl_gt1, "ADL-S GT1", "Intel(R) Graphics")
+CHIPSET(0x4691, adl_gt1, "ADL-S GT1", "Intel(R) Graphics")
+CHIPSET(0x4692, adl_gt1, "ADL-S GT1", "Intel(R) Graphics")
+CHIPSET(0x4693, adl_gt05, "ADL-S GT0.5", "Intel(R) Graphics")
+CHIPSET(0x4698, adl_gt1, "ADL-S GT1", "Intel(R) Graphics")
+CHIPSET(0x4699, adl_gt1, "ADL-S GT1", "Intel(R) Graphics")
+
CHIPSET(0x9A40, tgl_gt2, "TGL GT2", "Intel(R) Xe Graphics")
CHIPSET(0x9A49, tgl_gt2, "TGL GT2", "Intel(R) Xe Graphics")
CHIPSET(0x9A59, tgl_gt2, "TGL GT2", "Intel(R) Graphics")
diff --git a/src/intel/dev/gen_device_info.c b/src/intel/dev/gen_device_info.c
index ceec970e67f..c04953b343d 100644
--- a/src/intel/dev/gen_device_info.c
+++ b/src/intel/dev/gen_device_info.c
@@ -63,6 +63,7 @@ static const struct {
{ "tgl", 0x9a49 },
{ "rkl", 0x4c8a },
{ "dg1", 0x4905 },
+ { "adl", 0x4680 },
};
/**
@@ -959,6 +960,14 @@ static const struct gen_device_info gen_device_info_rkl_gt1 = {
GEN12_GT_FEATURES(1),
};
+static const struct gen_device_info gen_device_info_adl_gt05 = {
+ GEN12_GT05_FEATURES,
+};
+
+static const struct gen_device_info gen_device_info_adl_gt1 = {
+ GEN12_GT_FEATURES(1),
+};
+
#define GEN12_DG1_FEATURES \
GEN12_GT_FEATURES(2), \
.is_dg1 = true, \