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-rw-r--r--src/gallium/drivers/iris/iris_state.c18
-rw-r--r--src/intel/vulkan/genX_cmd_buffer.c23
2 files changed, 39 insertions, 2 deletions
diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index 16e9af0d83e..1710e84cf1f 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -6222,6 +6222,17 @@ iris_upload_dirty_render_state(struct iris_context *ice,
if (ice->state.streamout_active) {
if (dirty & IRIS_DIRTY_SO_BUFFERS) {
+ /* Wa_16011411144
+ * SW must insert a PIPE_CONTROL cmd before and after the
+ * 3dstate_so_buffer_index_0/1/2/3 states to ensure so_buffer_index_* state is
+ * not combined with other state changes.
+ */
+ if (intel_device_info_is_dg2(&batch->screen->devinfo)) {
+ iris_emit_pipe_control_flush(batch,
+ "SO pre change stall WA",
+ PIPE_CONTROL_CS_STALL);
+ }
+
for (int i = 0; i < 4; i++) {
struct iris_stream_output_target *tgt =
(void *) ice->state.so_target[i];
@@ -6251,6 +6262,13 @@ iris_upload_dirty_render_state(struct iris_context *ice,
iris_batch_emit(batch, so_buffers, 4 * dwords);
}
}
+
+ /* Wa_16011411144 */
+ if (intel_device_info_is_dg2(&batch->screen->devinfo)) {
+ iris_emit_pipe_control_flush(batch,
+ "SO post change stall WA",
+ PIPE_CONTROL_CS_STALL);
+ }
}
if ((dirty & IRIS_DIRTY_SO_DECL_LIST) && ice->state.streamout) {
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index a03faa8e2f3..b8fe25044ee 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -3894,6 +3894,19 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
if ((cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_XFB_ENABLE) ||
(GFX_VER == 7 && (cmd_buffer->state.gfx.dirty &
ANV_CMD_DIRTY_PIPELINE))) {
+ /* Wa_16011411144:
+ *
+ * SW must insert a PIPE_CONTROL cmd before and after the
+ * 3dstate_so_buffer_index_0/1/2/3 states to ensure so_buffer_index_*
+ * state is not combined with other state changes.
+ */
+ if (intel_device_info_is_dg2(&cmd_buffer->device->info)) {
+ anv_add_pending_pipe_bits(cmd_buffer,
+ ANV_PIPE_CS_STALL_BIT,
+ "before SO_BUFFER change WA");
+ genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
+ }
+
/* We don't need any per-buffer dirty tracking because you're not
* allowed to bind different XFB buffers while XFB is enabled.
*/
@@ -3931,8 +3944,14 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
}
}
- /* CNL and later require a CS stall after 3DSTATE_SO_BUFFER */
- if (GFX_VER >= 10) {
+ if (intel_device_info_is_dg2(&cmd_buffer->device->info)) {
+ /* Wa_16011411144: also CS_STALL after touching SO_BUFFER change */
+ anv_add_pending_pipe_bits(cmd_buffer,
+ ANV_PIPE_CS_STALL_BIT,
+ "after SO_BUFFER change WA");
+ genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
+ } else if (GFX_VER >= 10) {
+ /* CNL and later require a CS stall after 3DSTATE_SO_BUFFER */
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_CS_STALL_BIT,
"after 3DSTATE_SO_BUFFER call");