diff options
Diffstat (limited to 'src/i965_pciids.h')
| -rw-r--r-- | src/i965_pciids.h | 131 |
1 files changed, 131 insertions, 0 deletions
diff --git a/src/i965_pciids.h b/src/i965_pciids.h new file mode 100644 index 0000000..64973e4 --- /dev/null +++ b/src/i965_pciids.h @@ -0,0 +1,131 @@ +/* + * Copyright © 2014 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Copied and modified from (mesa) include/pci_ids/i965_pci_ids.h + */ + +CHIPSET(0x2A42, g4x, g4x, "Intel(R) GM45 Express Chipset") +CHIPSET(0x2E02, g4x, g4x, "Intel(R) Integrated Graphics Device") +CHIPSET(0x2E12, g4x, g4x, "Intel(R) Q45/Q43") +CHIPSET(0x2E22, g4x, g4x, "Intel(R) G45/G43") +CHIPSET(0x2E32, g4x, g4x, "Intel(R) G41") +CHIPSET(0x2E42, g4x, g4x, "Intel(R) B43") +CHIPSET(0x2E92, g4x, g4x, "Intel(R) B43") +CHIPSET(0x0042, ilk, ilk, "Intel(R) Ironlake Desktop") +CHIPSET(0x0046, ilk, ilk, "Intel(R) Ironlake Mobile") +CHIPSET(0x0102, snb, snb_gt1, "Intel(R) Sandybridge Desktop") +CHIPSET(0x0112, snb, snb_gt2, "Intel(R) Sandybridge Desktop") +CHIPSET(0x0122, snb, snb_gt2, "Intel(R) Sandybridge Desktop") +CHIPSET(0x0106, snb, snb_gt1, "Intel(R) Sandybridge Mobile") +CHIPSET(0x0116, snb, snb_gt2, "Intel(R) Sandybridge Mobile") +CHIPSET(0x0126, snb, snb_gt2, "Intel(R) Sandybridge Mobile") +CHIPSET(0x010A, snb, snb_gt1, "Intel(R) Sandybridge Server") +CHIPSET(0x0152, ivb, ivb_gt1, "Intel(R) Ivybridge Desktop") +CHIPSET(0x0162, ivb, ivb_gt2, "Intel(R) Ivybridge Desktop") +CHIPSET(0x0156, ivb, ivb_gt1, "Intel(R) Ivybridge Mobile") +CHIPSET(0x0166, ivb, ivb_gt2, "Intel(R) Ivybridge Mobile") +CHIPSET(0x015A, ivb, ivb_gt1, "Intel(R) Ivybridge Server") +CHIPSET(0x016A, ivb, ivb_gt2, "Intel(R) Ivybridge Server") +CHIPSET(0x0F31, ivb, byt, "Intel(R) Bay Trail") +CHIPSET(0x0F32, ivb, byt, "Intel(R) Bay Trail") +CHIPSET(0x0F33, ivb, byt, "Intel(R) Bay Trail") +CHIPSET(0x0157, ivb, byt, "Intel(R) Bay Trail") +CHIPSET(0x0155, ivb, byt, "Intel(R) Bay Trail") +CHIPSET(0x0402, hsw, hsw_gt1, "Intel(R) Haswell Desktop") +CHIPSET(0x0412, hsw, hsw_gt2, "Intel(R) Haswell Desktop") +CHIPSET(0x0422, hsw, hsw_gt3, "Intel(R) Haswell Desktop") +CHIPSET(0x0406, hsw, hsw_gt1, "Intel(R) Haswell Mobile") +CHIPSET(0x0416, hsw, hsw_gt2, "Intel(R) Haswell Mobile") +CHIPSET(0x0426, hsw, hsw_gt3, "Intel(R) Haswell Mobile") +CHIPSET(0x040A, hsw, hsw_gt1, "Intel(R) Haswell Server") +CHIPSET(0x041A, hsw, hsw_gt2, "Intel(R) Haswell Server") +CHIPSET(0x042A, hsw, hsw_gt3, "Intel(R) Haswell Server") +CHIPSET(0x040B, hsw, hsw_gt1, "Intel(R) Haswell") +CHIPSET(0x041B, hsw, hsw_gt2, "Intel(R) Haswell") +CHIPSET(0x042B, hsw, hsw_gt3, "Intel(R) Haswell") +CHIPSET(0x040E, hsw, hsw_gt1, "Intel(R) Haswell") +CHIPSET(0x041E, hsw, hsw_gt2, "Intel(R) Haswell") +CHIPSET(0x042E, hsw, hsw_gt3, "Intel(R) Haswell") +CHIPSET(0x0C02, hsw, hsw_gt1, "Intel(R) Haswell Desktop") +CHIPSET(0x0C12, hsw, hsw_gt2, "Intel(R) Haswell Desktop") +CHIPSET(0x0C22, hsw, hsw_gt3, "Intel(R) Haswell Desktop") +CHIPSET(0x0C06, hsw, hsw_gt1, "Intel(R) Haswell Mobile") +CHIPSET(0x0C16, hsw, hsw_gt2, "Intel(R) Haswell Mobile") +CHIPSET(0x0C26, hsw, hsw_gt3, "Intel(R) Haswell Mobile") +CHIPSET(0x0C0A, hsw, hsw_gt1, "Intel(R) Haswell Server") +CHIPSET(0x0C1A, hsw, hsw_gt2, "Intel(R) Haswell Server") +CHIPSET(0x0C2A, hsw, hsw_gt3, "Intel(R) Haswell Server") +CHIPSET(0x0C0B, hsw, hsw_gt1, "Intel(R) Haswell") +CHIPSET(0x0C1B, hsw, hsw_gt2, "Intel(R) Haswell") +CHIPSET(0x0C2B, hsw, hsw_gt3, "Intel(R) Haswell") +CHIPSET(0x0C0E, hsw, hsw_gt1, "Intel(R) Haswell") +CHIPSET(0x0C1E, hsw, hsw_gt2, "Intel(R) Haswell") +CHIPSET(0x0C2E, hsw, hsw_gt3, "Intel(R) Haswell") +CHIPSET(0x0A02, hsw, hsw_gt1, "Intel(R) Haswell Desktop") +CHIPSET(0x0A12, hsw, hsw_gt2, "Intel(R) Haswell Desktop") +CHIPSET(0x0A22, hsw, hsw_gt3, "Intel(R) Haswell Desktop") +CHIPSET(0x0A06, hsw, hsw_gt1, "Intel(R) Haswell Mobile") +CHIPSET(0x0A16, hsw, hsw_gt2, "Intel(R) Haswell Mobile") +CHIPSET(0x0A26, hsw, hsw_gt3, "Intel(R) Haswell Mobile") +CHIPSET(0x0A0A, hsw, hsw_gt1, "Intel(R) Haswell Server") +CHIPSET(0x0A1A, hsw, hsw_gt2, "Intel(R) Haswell Server") +CHIPSET(0x0A2A, hsw, hsw_gt3, "Intel(R) Haswell Server") +CHIPSET(0x0A0B, hsw, hsw_gt1, "Intel(R) Haswell") +CHIPSET(0x0A1B, hsw, hsw_gt2, "Intel(R) Haswell") +CHIPSET(0x0A2B, hsw, hsw_gt3, "Intel(R) Haswell") +CHIPSET(0x0A0E, hsw, hsw_gt1, "Intel(R) Haswell") +CHIPSET(0x0A1E, hsw, hsw_gt2, "Intel(R) Haswell") +CHIPSET(0x0A2E, hsw, hsw_gt3, "Intel(R) Haswell") +CHIPSET(0x0D02, hsw, hsw_gt1, "Intel(R) Haswell Desktop") +CHIPSET(0x0D12, hsw, hsw_gt2, "Intel(R) Haswell Desktop") +CHIPSET(0x0D22, hsw, hsw_gt3, "Intel(R) Haswell Desktop") +CHIPSET(0x0D06, hsw, hsw_gt1, "Intel(R) Haswell Mobile") +CHIPSET(0x0D16, hsw, hsw_gt2, "Intel(R) Haswell Mobile") +CHIPSET(0x0D26, hsw, hsw_gt3, "Intel(R) Haswell Mobile") +CHIPSET(0x0D0A, hsw, hsw_gt1, "Intel(R) Haswell Server") +CHIPSET(0x0D1A, hsw, hsw_gt2, "Intel(R) Haswell Server") +CHIPSET(0x0D2A, hsw, hsw_gt3, "Intel(R) Haswell") +CHIPSET(0x0D0B, hsw, hsw_gt1, "Intel(R) Haswell") +CHIPSET(0x0D1B, hsw, hsw_gt2, "Intel(R) Haswell") +CHIPSET(0x0D2B, hsw, hsw_gt3, "Intel(R) Haswell") +CHIPSET(0x0D0E, hsw, hsw_gt1, "Intel(R) Haswell") +CHIPSET(0x0D1E, hsw, hsw_gt2, "Intel(R) Haswell") +CHIPSET(0x0D2E, hsw, hsw_gt3, "Intel(R) Haswell") +CHIPSET(0x1602, bdw, bdw, "Intel(R) Broadwell") +CHIPSET(0x1606, bdw, bdw, "Intel(R) Broadwell") +CHIPSET(0x160A, bdw, bdw, "Intel(R) Broadwell") +CHIPSET(0x160B, bdw, bdw, "Intel(R) Broadwell") +CHIPSET(0x160D, bdw, bdw, "Intel(R) Broadwell") +CHIPSET(0x160E, bdw, bdw, "Intel(R) Broadwell") +CHIPSET(0x1612, bdw, bdw, "Intel(R) Broadwell") +CHIPSET(0x1616, bdw, bdw, "Intel(R) Broadwell") +CHIPSET(0x161A, bdw, bdw, "Intel(R) Broadwell") +CHIPSET(0x161B, bdw, bdw, "Intel(R) Broadwell") +CHIPSET(0x161D, bdw, bdw, "Intel(R) Broadwell") +CHIPSET(0x161E, bdw, bdw, "Intel(R) Broadwell") +CHIPSET(0x1622, bdw, bdw, "Intel(R) Broadwell") +CHIPSET(0x1626, bdw, bdw, "Intel(R) Broadwell") +CHIPSET(0x162A, bdw, bdw, "Intel(R) Broadwell") +CHIPSET(0x162B, bdw, bdw, "Intel(R) Broadwell") +CHIPSET(0x162D, bdw, bdw, "Intel(R) Broadwell") +CHIPSET(0x162E, bdw, bdw, "Intel(R) Broadwell") |