diff options
| -rw-r--r-- | lib/Target/R600/SIInstrInfo.td | 2 | ||||
| -rw-r--r-- | test/CodeGen/R600/operand-spacing.ll | 15 |
2 files changed, 16 insertions, 1 deletions
diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td index a0c00332948..91e4d0d79d0 100644 --- a/lib/Target/R600/SIInstrInfo.td +++ b/lib/Target/R600/SIInstrInfo.td @@ -442,7 +442,7 @@ class VOPProfile <list<ValueType> _ArgVT> { field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs, HasModifiers>.ret; - field string Asm32 = "_e32 "#getAsm32<NumSrcArgs>.ret; + field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret; field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret; } diff --git a/test/CodeGen/R600/operand-spacing.ll b/test/CodeGen/R600/operand-spacing.ll new file mode 100644 index 00000000000..d9e153d4fe4 --- /dev/null +++ b/test/CodeGen/R600/operand-spacing.ll @@ -0,0 +1,15 @@ +; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI %s + +; Make sure there isn't an extra space between the instruction name and first operands. + +; SI-LABEL: @add_f32 +; SI-DAG: S_LOAD_DWORD [[SREGA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI-DAG: S_LOAD_DWORD [[SREGB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc +; SI: V_MOV_B32_e32 [[VREGB:v[0-9]+]], [[SREGB]] +; SI: V_ADD_F32_e32 [[RESULT:v[0-9]+]], [[SREGA]], [[VREGB]] +; SI: BUFFER_STORE_DWORD [[RESULT]], +define void @add_f32(float addrspace(1)* %out, float %a, float %b) { + %result = fadd float %a, %b + store float %result, float addrspace(1)* %out + ret void +} |