diff options
| -rw-r--r-- | lib/Target/AMDGPU/SIInsertWaits.cpp | 6 | ||||
| -rw-r--r-- | test/CodeGen/AMDGPU/missing-store.ll | 3 | ||||
| -rw-r--r-- | test/CodeGen/AMDGPU/salu-to-valu.ll | 3 |
3 files changed, 4 insertions, 8 deletions
diff --git a/lib/Target/AMDGPU/SIInsertWaits.cpp b/lib/Target/AMDGPU/SIInsertWaits.cpp index 15884732c12..ead4c9ebf18 100644 --- a/lib/Target/AMDGPU/SIInsertWaits.cpp +++ b/lib/Target/AMDGPU/SIInsertWaits.cpp @@ -634,12 +634,6 @@ bool SIInsertWaits::runOnMachineFunction(MachineFunction &MF) { insertDPPWaitStates(I); } - // Insert required wait states for SMRD reading an SGPR written by a VALU - // instruction. - if (ST.getGeneration() <= AMDGPUSubtarget::SOUTHERN_ISLANDS && - I->getOpcode() == AMDGPU::V_READFIRSTLANE_B32) - TII->insertWaitStates(MBB, std::next(I), 4); - // Record pre-existing, explicitly requested waits if (I->getOpcode() == AMDGPU::S_WAITCNT) { handleExistingWait(*I); diff --git a/test/CodeGen/AMDGPU/missing-store.ll b/test/CodeGen/AMDGPU/missing-store.ll index 658666304f6..d608fd14ccf 100644 --- a/test/CodeGen/AMDGPU/missing-store.ll +++ b/test/CodeGen/AMDGPU/missing-store.ll @@ -10,7 +10,8 @@ ; SI: buffer_store_dword ; SI: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}} ; SI: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}} -; SI-NEXT: s_nop +; SI: s_load_dword +; SI: s_nop 2 ; SI: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}} ; SI: buffer_store_dword ; SI: s_endpgm diff --git a/test/CodeGen/AMDGPU/salu-to-valu.ll b/test/CodeGen/AMDGPU/salu-to-valu.ll index bcd20ff5bdb..7d167e5dd44 100644 --- a/test/CodeGen/AMDGPU/salu-to-valu.ll +++ b/test/CodeGen/AMDGPU/salu-to-valu.ll @@ -56,7 +56,8 @@ done: ; preds = %loop ; SI: s_movk_i32 [[OFFSET:s[0-9]+]], 0x2ee0 ; GCN: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}} ; GCN: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}} -; SI-NEXT: s_nop +; SI: s_mov_b32 +; SI: s_nop 2 ; SI: s_load_dword [[OUT:s[0-9]+]], s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, [[OFFSET]] ; CI: s_load_dword [[OUT:s[0-9]+]], s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0xbb8 ; GCN: v_mov_b32_e32 [[V_OUT:v[0-9]+]], [[OUT]] |