summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorKonstantin Zhuravlyov <kzhuravl_dev@outlook.com>2016-05-24 18:37:18 +0000
committerKonstantin Zhuravlyov <kzhuravl_dev@outlook.com>2016-05-24 18:37:18 +0000
commitd7b9b912ddec8e58b132bd726b47613d2e3be9b1 (patch)
tree9ac2dcab63a862972761231b98c1d3fea0140c91
parent7f50c3125ca98cda18636c4239a04d4ac5444031 (diff)
[AMDGPU][NFC] Rename ReserveTrapVGPRs -> ReserveRegs
Differential Revision: http://reviews.llvm.org/D20081 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@270594 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat
-rw-r--r--lib/Target/AMDGPU/AMDGPU.td8
-rw-r--r--lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp11
-rw-r--r--lib/Target/AMDGPU/AMDGPUSubtarget.cpp2
-rw-r--r--lib/Target/AMDGPU/AMDGPUSubtarget.h6
-rw-r--r--lib/Target/AMDGPU/SIMachineFunctionInfo.cpp6
-rw-r--r--lib/Target/AMDGPU/SIMachineFunctionInfo.h9
-rw-r--r--lib/Target/AMDGPU/SIRegisterInfo.cpp6
-rw-r--r--test/CodeGen/AMDGPU/debugger-reserve-regs.ll4
8 files changed, 26 insertions, 26 deletions
diff --git a/lib/Target/AMDGPU/AMDGPU.td b/lib/Target/AMDGPU/AMDGPU.td
index a6e862eb2fb..c827ed77a10 100644
--- a/lib/Target/AMDGPU/AMDGPU.td
+++ b/lib/Target/AMDGPU/AMDGPU.td
@@ -328,11 +328,11 @@ def FeatureDebuggerInsertNops : SubtargetFeature<
"Insert one nop instruction for each high level source statement"
>;
-def FeatureDebuggerReserveTrapRegs : SubtargetFeature<
- "amdgpu-debugger-reserve-trap-regs",
- "DebuggerReserveTrapVGPRs",
+def FeatureDebuggerReserveRegs : SubtargetFeature<
+ "amdgpu-debugger-reserve-regs",
+ "DebuggerReserveRegs",
"true",
- "Reserve VGPRs for trap handler usage"
+ "Reserve registers for debugger usage"
>;
//===----------------------------------------------------------------------===//
diff --git a/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index 73803441f48..f4a17b90411 100644
--- a/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -435,12 +435,13 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
MaxSGPR += ExtraSGPRs;
- // Update necessary Reserved* fields and max VGPRs used if
- // "amdgpu-debugger-reserve-trap-regs" attribute was specified.
- if (STM.debuggerReserveTrapVGPRs()) {
+ // Record first reserved register and reserved register count fields, and
+ // update max register counts if "amdgpu-debugger-reserve-regs" attribute was
+ // specified.
+ if (STM.debuggerReserveRegs()) {
ProgInfo.ReservedVGPRFirst = MaxVGPR + 1;
- ProgInfo.ReservedVGPRCount = MFI->getDebuggerReserveTrapVGPRCount();
- MaxVGPR += MFI->getDebuggerReserveTrapVGPRCount();
+ ProgInfo.ReservedVGPRCount = MFI->getDebuggerReservedVGPRCount();
+ MaxVGPR += MFI->getDebuggerReservedVGPRCount();
}
// We found the maximum register index. They start at 0, so add one to get the
diff --git a/lib/Target/AMDGPU/AMDGPUSubtarget.cpp b/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
index 2357e037458..030bebcd1c0 100644
--- a/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
+++ b/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
@@ -98,7 +98,7 @@ AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
LDSBankCount(0),
IsaVersion(ISAVersion0_0_0),
EnableSIScheduler(false),
- DebuggerInsertNops(false), DebuggerReserveTrapVGPRs(false),
+ DebuggerInsertNops(false), DebuggerReserveRegs(false),
FrameLowering(nullptr),
GISel(),
InstrItins(getInstrItineraryForCPU(GPU)), TargetTriple(TT) {
diff --git a/lib/Target/AMDGPU/AMDGPUSubtarget.h b/lib/Target/AMDGPU/AMDGPUSubtarget.h
index 6cd18454829..ec7da3ac6d6 100644
--- a/lib/Target/AMDGPU/AMDGPUSubtarget.h
+++ b/lib/Target/AMDGPU/AMDGPUSubtarget.h
@@ -96,7 +96,7 @@ private:
unsigned IsaVersion;
bool EnableSIScheduler;
bool DebuggerInsertNops;
- bool DebuggerReserveTrapVGPRs;
+ bool DebuggerReserveRegs;
std::unique_ptr<AMDGPUFrameLowering> FrameLowering;
std::unique_ptr<AMDGPUTargetLowering> TLInfo;
@@ -319,8 +319,8 @@ public:
return DebuggerInsertNops;
}
- bool debuggerReserveTrapVGPRs() const {
- return DebuggerReserveTrapVGPRs;
+ bool debuggerReserveRegs() const {
+ return DebuggerReserveRegs;
}
bool dumpCode() const {
diff --git a/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
index d10a9c1a846..2b7c0f3a2e8 100644
--- a/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
+++ b/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
@@ -49,7 +49,7 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
PSInputAddr(0),
ReturnsVoid(true),
MaximumWorkGroupSize(0),
- DebuggerReserveTrapVGPRCount(0),
+ DebuggerReservedVGPRCount(0),
LDSWaveSpillSize(0),
PSInputEna(0),
NumUserSGPRs(0),
@@ -134,8 +134,8 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
else
MaximumWorkGroupSize = ST.getWavefrontSize();
- if (ST.debuggerReserveTrapVGPRs())
- DebuggerReserveTrapVGPRCount = 4;
+ if (ST.debuggerReserveRegs())
+ DebuggerReservedVGPRCount = 4;
}
unsigned SIMachineFunctionInfo::addPrivateSegmentBuffer(
diff --git a/lib/Target/AMDGPU/SIMachineFunctionInfo.h b/lib/Target/AMDGPU/SIMachineFunctionInfo.h
index 04437f1d894..ee2f722aba5 100644
--- a/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+++ b/lib/Target/AMDGPU/SIMachineFunctionInfo.h
@@ -62,8 +62,8 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
unsigned MaximumWorkGroupSize;
- // Number of reserved VGPRs for trap handler usage.
- unsigned DebuggerReserveTrapVGPRCount;
+ // Number of reserved VGPRs for debugger usage.
+ unsigned DebuggerReservedVGPRCount;
public:
// FIXME: Make private
@@ -329,8 +329,9 @@ public:
ReturnsVoid = Value;
}
- unsigned getDebuggerReserveTrapVGPRCount() const {
- return DebuggerReserveTrapVGPRCount;
+ /// \returns Number of reserved VGPRs for debugger usage.
+ unsigned getDebuggerReservedVGPRCount() const {
+ return DebuggerReservedVGPRCount;
}
unsigned getMaximumWorkGroupSize(const MachineFunction &MF) const;
diff --git a/lib/Target/AMDGPU/SIRegisterInfo.cpp b/lib/Target/AMDGPU/SIRegisterInfo.cpp
index ee371177494..477792da7bf 100644
--- a/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -193,12 +193,12 @@ BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
assert(!isSubRegister(ScratchRSrcReg, ScratchWaveOffsetReg));
}
- // Reserve VGPRs for trap handler usage if "amdgpu-debugger-reserve-trap-regs"
+ // Reserve registers for debugger usage if "amdgpu-debugger-reserve-trap-regs"
// attribute was specified.
const AMDGPUSubtarget &ST = MF.getSubtarget<AMDGPUSubtarget>();
- if (ST.debuggerReserveTrapVGPRs()) {
+ if (ST.debuggerReserveRegs()) {
unsigned ReservedVGPRFirst =
- MaxWorkGroupVGPRCount - MFI->getDebuggerReserveTrapVGPRCount();
+ MaxWorkGroupVGPRCount - MFI->getDebuggerReservedVGPRCount();
for (unsigned i = ReservedVGPRFirst; i < MaxWorkGroupVGPRCount; ++i) {
unsigned Reg = AMDGPU::VGPR_32RegClass.getRegister(i);
reserveRegisterTuples(Reserved, Reg);
diff --git a/test/CodeGen/AMDGPU/debugger-reserve-regs.ll b/test/CodeGen/AMDGPU/debugger-reserve-regs.ll
index 17a36a09606..73a18da9894 100644
--- a/test/CodeGen/AMDGPU/debugger-reserve-regs.ll
+++ b/test/CodeGen/AMDGPU/debugger-reserve-regs.ll
@@ -1,8 +1,6 @@
-; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=+amdgpu-debugger-reserve-trap-regs -verify-machineinstrs < %s | FileCheck %s
-
+; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=+amdgpu-debugger-reserve-regs -verify-machineinstrs < %s | FileCheck %s
; CHECK: reserved_vgpr_first = {{[0-9]+}}
; CHECK-NEXT: reserved_vgpr_count = 4
-
; CHECK: ReservedVGPRFirst: {{[0-9]+}}
; CHECK-NEXT: ReservedVGPRCount: 4
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-29 18:54:53 +0000