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path: root/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
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Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c34
1 files changed, 30 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index dba8a5b25e66..55118fca241d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -218,14 +218,40 @@ void free_gtt_mem(struct kgd_dev *kgd, void *mem_obj)
kfree(mem);
}
-uint64_t get_vmem_size(struct kgd_dev *kgd)
+void get_local_mem_info(struct kgd_dev *kgd,
+ struct kfd_local_mem_info *mem_info)
{
- struct amdgpu_device *rdev =
- (struct amdgpu_device *)kgd;
+ struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
+ uint64_t address_mask;
+ resource_size_t aper_limit;
BUG_ON(kgd == NULL);
+ BUG_ON(mem_info == NULL);
+
+ memset(mem_info, 0, sizeof(*mem_info));
+
+ address_mask = ~((1UL << 40) - 1); /* 0xffffff0000000000 */
+ aper_limit = adev->mc.aper_base + adev->mc.aper_size;
+
+ /* deal with 64 bit PCI aperture base address space on 32 bit systems */
+ if (!(adev->mc.aper_base & address_mask ||
+ aper_limit & address_mask)) {
+ mem_info->local_mem_size_public = adev->mc.visible_vram_size;
+ mem_info->local_mem_size_private = adev->mc.real_vram_size -
+ adev->mc.visible_vram_size;
+ } else {
+ mem_info->local_mem_size_public = 0;
+ mem_info->local_mem_size_private = adev->mc.real_vram_size;
+ }
+ mem_info->vram_width = adev->mc.vram_width;
+
+ if (adev->pp_enabled || rdev->pm.funcs->get_mclk)
+ mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false);
- return rdev->mc.real_vram_size;
+ pr_debug("amdgpu: address base: 0x%llx limit 0x%llx public 0x%llx private 0x%llx\n",
+ adev->mc.aper_base, aper_limit,
+ mem_info->local_mem_size_public,
+ mem_info->local_mem_size_private);
}
uint64_t get_gpu_clock_counter(struct kgd_dev *kgd)