diff options
author | Eric Anholt <eric@anholt.net> | 2011-12-09 11:58:39 -0800 |
---|---|---|
committer | Eric Anholt <eric@anholt.net> | 2011-12-09 12:15:48 -0800 |
commit | b4726ed08fdef78941ba7e372d3a14cc2661ef30 (patch) | |
tree | f3f1183f8c079e531a989a5f458e10550ef2c8c6 | |
parent | 5ad2f234a1c5f2534b59a9f7dad8c6bda488d956 (diff) |
drm/i915: Try adding more dword writesflush-dw-sync-sync-sync
-rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.c | 23 |
1 files changed, 21 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 750b3bc4a95..24deac262f3 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -482,8 +482,9 @@ static int mi_flush_dw_add_request(struct intel_ring_buffer *ring, u32 *seqno) { int ret; + int i; - ret = intel_ring_begin(ring, 12); + ret = intel_ring_begin(ring, 10); if (ret) return ret; @@ -508,10 +509,28 @@ mi_flush_dw_add_request(struct intel_ring_buffer *ring, u32 *seqno) MI_FLUSH_DW_GLOBAL_GTT); /* HWS byte offset */ intel_ring_emit(ring, *seqno); /* QW low */ intel_ring_emit(ring, MI_NOOP); + intel_ring_advance(ring); + + for (i = 0; i < 16; i++) { + ret = intel_ring_begin(ring, 4); + if (ret) + return ret; + intel_ring_emit(ring, + MI_FLUSH_DW | + MI_FLUSH_DW_STORE_DATA_INDEX | + MI_FLUSH_DW_POST_SYNC_WRITE_QW); + intel_ring_emit(ring, + ((i + 1) * 64) | + MI_FLUSH_DW_GLOBAL_GTT); /* HWS byte offset */ + intel_ring_emit(ring, i); /* QW low */ + intel_ring_emit(ring, MI_NOOP); + intel_ring_advance(ring); + } + + ret = intel_ring_begin(ring, 2); intel_ring_emit(ring, MI_USER_INTERRUPT); intel_ring_emit(ring, MI_NOOP); - intel_ring_advance(ring); return 0; |