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authorGareth Hughes <gareth@users.sourceforge.net>2000-12-29 04:46:23 +0000
committerGareth Hughes <gareth@users.sourceforge.net>2000-12-29 04:46:23 +0000
commit7c213c834b226e952faf2e1174e40b39350643d6 (patch)
tree9b374b55e7321bd4d147a343996f76b476536348
parent3b89d5aaa53ddec0047d57631a12e236f9e7dec1 (diff)
Random hacking. Can you say functional Radeon driver?
-rw-r--r--linux-core/radeon_drv.c42
-rw-r--r--linux/drm.h194
-rw-r--r--linux/r128_cce.c44
-rw-r--r--linux/r128_drm.h8
-rw-r--r--linux/r128_state.c12
-rw-r--r--linux/radeon_cp.c220
-rw-r--r--linux/radeon_drm.h98
-rw-r--r--linux/radeon_drv.c42
-rw-r--r--linux/radeon_drv.h171
-rw-r--r--linux/radeon_state.c710
-rw-r--r--linux/sis_drm.h23
-rw-r--r--shared-core/drm.h194
-rw-r--r--shared/drm.h194
13 files changed, 1120 insertions, 832 deletions
diff --git a/linux-core/radeon_drv.c b/linux-core/radeon_drv.c
index 35539766..93ad2f0d 100644
--- a/linux-core/radeon_drv.c
+++ b/linux-core/radeon_drv.c
@@ -34,7 +34,7 @@
#define RADEON_NAME "radeon"
#define RADEON_DESC "ATI Radeon"
-#define RADEON_DATE "20001223"
+#define RADEON_DATE "20001228"
#define RADEON_MAJOR 1
#define RADEON_MINOR 0
#define RADEON_PATCHLEVEL 0
@@ -105,18 +105,20 @@ static drm_ioctl_desc_t radeon_ioctls[] = {
[DRM_IOCTL_NR(DRM_IOCTL_AGP_UNBIND)] = { drm_agp_unbind, 1, 1 },
#endif
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_RESET)] = { radeon_engine_reset, 1, 0 },
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_INIT)] = { radeon_cp_init, 1, 1 },
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_START)] = { radeon_cp_start, 1, 1 },
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_STOP)] = { radeon_cp_stop, 1, 1 },
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_RESET)] = { radeon_cp_reset, 1, 1 },
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_IDLE)] = { radeon_cp_idle, 1, 0 },
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_SWAP)] = { radeon_cp_swap, 1, 0 },
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_CLEAR)] = { radeon_cp_clear, 1, 0 },
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_VERTEX)] = { radeon_cp_vertex, 1, 0 },
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_INDICES)] = { radeon_cp_indices, 1, 0 },
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_BLIT)] = { radeon_cp_blit, 1, 0 },
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_PACKET)] = { radeon_cp_packet, 1, 0 },
+ [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_INIT)] = { radeon_cp_init, 1, 1 },
+ [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_START)]= { radeon_cp_start, 1, 1 },
+ [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_STOP)] = { radeon_cp_stop, 1, 1 },
+ [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_RESET)]= { radeon_cp_reset, 1, 1 },
+ [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_IDLE)] = { radeon_cp_idle, 1, 0 },
+ [DRM_IOCTL_NR(DRM_IOCTL_RADEON_RESET)] = { radeon_engine_reset,1,0 },
+ [DRM_IOCTL_NR(DRM_IOCTL_RADEON_PAGEFLIP)]= { radeon_cp_pageflip,1, 0 },
+ [DRM_IOCTL_NR(DRM_IOCTL_RADEON_SWAP)] = { radeon_cp_swap, 1, 0 },
+ [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CLEAR)] = { radeon_cp_clear, 1, 0 },
+ [DRM_IOCTL_NR(DRM_IOCTL_RADEON_VERTEX)] = { radeon_cp_vertex, 1, 0 },
+ [DRM_IOCTL_NR(DRM_IOCTL_RADEON_INDICES)] = { radeon_cp_indices, 1, 0 },
+ [DRM_IOCTL_NR(DRM_IOCTL_RADEON_BLIT)] = { radeon_cp_blit, 1, 0 },
+ [DRM_IOCTL_NR(DRM_IOCTL_RADEON_STIPPLE)] = { radeon_cp_stipple, 1, 0 },
+ [DRM_IOCTL_NR(DRM_IOCTL_RADEON_PACKET)] = { radeon_cp_packet, 1, 0 },
};
#define RADEON_IOCTL_COUNT DRM_ARRAY_SIZE(radeon_ioctls)
@@ -328,7 +330,7 @@ static int radeon_takedown(drm_device_t *dev)
/* radeon_init is called via init_module at module load time, or via
* linux/init/main.c (this is not currently supported). */
-static int radeon_init(void)
+static int __init radeon_init(void)
{
int retcode;
drm_device_t *dev = &radeon_device;
@@ -392,7 +394,7 @@ static int radeon_init(void)
/* radeon_cleanup is called via cleanup_module at module unload time. */
-static void radeon_cleanup(void)
+static void __exit radeon_cleanup(void)
{
drm_device_t *dev = &radeon_device;
@@ -484,7 +486,17 @@ int radeon_release(struct inode *inode, struct file *filp)
lock_kernel();
dev = priv->dev;
+
DRM_DEBUG("open_count = %d\n", dev->open_count);
+
+ /* Force the cleanup of page flipping when required */
+ if ( dev->dev_private ) {
+ drm_radeon_private_t *dev_priv = dev->dev_private;
+ if ( dev_priv->page_flipping ) {
+ radeon_do_cleanup_pageflip( dev );
+ }
+ }
+
if (!(retcode = drm_release(inode, filp))) {
#if LINUX_VERSION_CODE < 0x020333
MOD_DEC_USE_COUNT; /* Needed before Linux 2.3.51 */
diff --git a/linux/drm.h b/linux/drm.h
index e0496bc7..b892682a 100644
--- a/linux/drm.h
+++ b/linux/drm.h
@@ -296,111 +296,113 @@ typedef struct drm_agp_info {
unsigned short id_device;
} drm_agp_info_t;
-#define DRM_IOCTL_BASE 'd'
-#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
-#define DRM_IOR(nr,size) _IOR(DRM_IOCTL_BASE,nr,size)
-#define DRM_IOW(nr,size) _IOW(DRM_IOCTL_BASE,nr,size)
-#define DRM_IOWR(nr,size) _IOWR(DRM_IOCTL_BASE,nr,size)
-
-
-#define DRM_IOCTL_VERSION DRM_IOWR(0x00, drm_version_t)
-#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, drm_unique_t)
-#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, drm_auth_t)
-#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, drm_irq_busid_t)
-
-#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, drm_unique_t)
-#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, drm_auth_t)
-#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, drm_block_t)
-#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, drm_block_t)
-#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, drm_control_t)
-#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, drm_map_t)
-#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, drm_buf_desc_t)
-#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, drm_buf_desc_t)
-#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, drm_buf_info_t)
-#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, drm_buf_map_t)
-#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, drm_buf_free_t)
-
-#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, drm_ctx_t)
-#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, drm_ctx_t)
-#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, drm_ctx_t)
-#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, drm_ctx_t)
-#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, drm_ctx_t)
-#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, drm_ctx_t)
-#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, drm_ctx_res_t)
-#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, drm_draw_t)
-#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, drm_draw_t)
-#define DRM_IOCTL_DMA DRM_IOWR(0x29, drm_dma_t)
-#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, drm_lock_t)
-#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, drm_lock_t)
-#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, drm_lock_t)
-
-#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
-#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
-#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, drm_agp_mode_t)
-#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, drm_agp_info_t)
-#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, drm_agp_buffer_t)
-#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, drm_agp_buffer_t)
-#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, drm_agp_binding_t)
-#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, drm_agp_binding_t)
+#define DRM_IOCTL_BASE 'd'
+#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
+#define DRM_IOR(nr,size) _IOR(DRM_IOCTL_BASE,nr,size)
+#define DRM_IOW(nr,size) _IOW(DRM_IOCTL_BASE,nr,size)
+#define DRM_IOWR(nr,size) _IOWR(DRM_IOCTL_BASE,nr,size)
+
+
+#define DRM_IOCTL_VERSION DRM_IOWR(0x00, drm_version_t)
+#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, drm_unique_t)
+#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, drm_auth_t)
+#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, drm_irq_busid_t)
+
+#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, drm_unique_t)
+#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, drm_auth_t)
+#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, drm_block_t)
+#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, drm_block_t)
+#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, drm_control_t)
+#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, drm_map_t)
+#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, drm_buf_desc_t)
+#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, drm_buf_desc_t)
+#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, drm_buf_info_t)
+#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, drm_buf_map_t)
+#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, drm_buf_free_t)
+
+#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, drm_ctx_t)
+#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, drm_ctx_t)
+#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, drm_ctx_t)
+#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, drm_ctx_t)
+#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, drm_ctx_t)
+#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, drm_ctx_t)
+#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, drm_ctx_res_t)
+#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, drm_draw_t)
+#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, drm_draw_t)
+#define DRM_IOCTL_DMA DRM_IOWR(0x29, drm_dma_t)
+#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, drm_lock_t)
+#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, drm_lock_t)
+#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, drm_lock_t)
+
+#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
+#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
+#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, drm_agp_mode_t)
+#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, drm_agp_info_t)
+#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, drm_agp_buffer_t)
+#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, drm_agp_buffer_t)
+#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, drm_agp_binding_t)
+#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, drm_agp_binding_t)
/* Mga specific ioctls */
-#define DRM_IOCTL_MGA_INIT DRM_IOW( 0x40, drm_mga_init_t)
-#define DRM_IOCTL_MGA_SWAP DRM_IOW( 0x41, drm_mga_swap_t)
-#define DRM_IOCTL_MGA_CLEAR DRM_IOW( 0x42, drm_mga_clear_t)
-#define DRM_IOCTL_MGA_ILOAD DRM_IOW( 0x43, drm_mga_iload_t)
-#define DRM_IOCTL_MGA_VERTEX DRM_IOW( 0x44, drm_mga_vertex_t)
-#define DRM_IOCTL_MGA_FLUSH DRM_IOW( 0x45, drm_lock_t )
-#define DRM_IOCTL_MGA_INDICES DRM_IOW( 0x46, drm_mga_indices_t)
+#define DRM_IOCTL_MGA_INIT DRM_IOW( 0x40, drm_mga_init_t)
+#define DRM_IOCTL_MGA_SWAP DRM_IOW( 0x41, drm_mga_swap_t)
+#define DRM_IOCTL_MGA_CLEAR DRM_IOW( 0x42, drm_mga_clear_t)
+#define DRM_IOCTL_MGA_ILOAD DRM_IOW( 0x43, drm_mga_iload_t)
+#define DRM_IOCTL_MGA_VERTEX DRM_IOW( 0x44, drm_mga_vertex_t)
+#define DRM_IOCTL_MGA_FLUSH DRM_IOW( 0x45, drm_lock_t )
+#define DRM_IOCTL_MGA_INDICES DRM_IOW( 0x46, drm_mga_indices_t)
/* I810 specific ioctls */
-#define DRM_IOCTL_I810_INIT DRM_IOW( 0x40, drm_i810_init_t)
-#define DRM_IOCTL_I810_VERTEX DRM_IOW( 0x41, drm_i810_vertex_t)
-#define DRM_IOCTL_I810_CLEAR DRM_IOW( 0x42, drm_i810_clear_t)
-#define DRM_IOCTL_I810_FLUSH DRM_IO ( 0x43)
-#define DRM_IOCTL_I810_GETAGE DRM_IO ( 0x44)
-#define DRM_IOCTL_I810_GETBUF DRM_IOWR(0x45, drm_i810_dma_t)
-#define DRM_IOCTL_I810_SWAP DRM_IO ( 0x46)
-#define DRM_IOCTL_I810_COPY DRM_IOW( 0x47, drm_i810_copy_t)
-#define DRM_IOCTL_I810_DOCOPY DRM_IO ( 0x48)
+#define DRM_IOCTL_I810_INIT DRM_IOW( 0x40, drm_i810_init_t)
+#define DRM_IOCTL_I810_VERTEX DRM_IOW( 0x41, drm_i810_vertex_t)
+#define DRM_IOCTL_I810_CLEAR DRM_IOW( 0x42, drm_i810_clear_t)
+#define DRM_IOCTL_I810_FLUSH DRM_IO( 0x43)
+#define DRM_IOCTL_I810_GETAGE DRM_IO( 0x44)
+#define DRM_IOCTL_I810_GETBUF DRM_IOWR(0x45, drm_i810_dma_t)
+#define DRM_IOCTL_I810_SWAP DRM_IO( 0x46)
+#define DRM_IOCTL_I810_COPY DRM_IOW( 0x47, drm_i810_copy_t)
+#define DRM_IOCTL_I810_DOCOPY DRM_IO( 0x48)
/* Rage 128 specific ioctls */
-#define DRM_IOCTL_R128_INIT DRM_IOW( 0x40, drm_r128_init_t)
-#define DRM_IOCTL_R128_CCE_START DRM_IO( 0x41)
-#define DRM_IOCTL_R128_CCE_STOP DRM_IOW( 0x42, drm_r128_cce_stop_t)
-#define DRM_IOCTL_R128_CCE_RESET DRM_IO( 0x43)
-#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( 0x44)
-#define DRM_IOCTL_R128_RESET DRM_IO( 0x46)
-#define DRM_IOCTL_R128_SWAP DRM_IO( 0x47)
-#define DRM_IOCTL_R128_CLEAR DRM_IOW( 0x48, drm_r128_clear_t)
-#define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x49, drm_r128_vertex_t)
-#define DRM_IOCTL_R128_INDICES DRM_IOW( 0x4a, drm_r128_indices_t)
-#define DRM_IOCTL_R128_BLIT DRM_IOW( 0x4b, drm_r128_blit_t)
-#define DRM_IOCTL_R128_DEPTH DRM_IOW( 0x4c, drm_r128_depth_t)
-#define DRM_IOCTL_R128_STIPPLE DRM_IOW( 0x4d, drm_r128_stipple_t)
-#define DRM_IOCTL_R128_PACKET DRM_IOWR(0x4e, drm_r128_packet_t)
+#define DRM_IOCTL_R128_INIT DRM_IOW( 0x40, drm_r128_init_t)
+#define DRM_IOCTL_R128_CCE_START DRM_IO( 0x41)
+#define DRM_IOCTL_R128_CCE_STOP DRM_IOW( 0x42, drm_r128_cce_stop_t)
+#define DRM_IOCTL_R128_CCE_RESET DRM_IO( 0x43)
+#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( 0x44)
+#define DRM_IOCTL_R128_RESET DRM_IO( 0x46)
+#define DRM_IOCTL_R128_SWAP DRM_IO( 0x47)
+#define DRM_IOCTL_R128_CLEAR DRM_IOW( 0x48, drm_r128_clear_t)
+#define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x49, drm_r128_vertex_t)
+#define DRM_IOCTL_R128_INDICES DRM_IOW( 0x4a, drm_r128_indices_t)
+#define DRM_IOCTL_R128_BLIT DRM_IOW( 0x4b, drm_r128_blit_t)
+#define DRM_IOCTL_R128_DEPTH DRM_IOW( 0x4c, drm_r128_depth_t)
+#define DRM_IOCTL_R128_STIPPLE DRM_IOW( 0x4d, drm_r128_stipple_t)
+#define DRM_IOCTL_R128_PACKET DRM_IOWR(0x4e, drm_r128_packet_t)
/* Radeon specific ioctls */
-#define DRM_IOCTL_RADEON_RESET DRM_IO( 0x40)
-#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( 0x41, drm_radeon_init_t)
-#define DRM_IOCTL_RADEON_CP_START DRM_IO( 0x42)
-#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( 0x43, drm_radeon_cp_stop_t)
-#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( 0x44)
-#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( 0x45)
-#define DRM_IOCTL_RADEON_CP_SWAP DRM_IO( 0x46)
-#define DRM_IOCTL_RADEON_CP_CLEAR DRM_IOW( 0x47, drm_radeon_clear_t)
-#define DRM_IOCTL_RADEON_CP_VERTEX DRM_IOW( 0x48, drm_radeon_vertex_t)
-#define DRM_IOCTL_RADEON_CP_INDICES DRM_IOW( 0x49, drm_radeon_indices_t)
-#define DRM_IOCTL_RADEON_CP_BLIT DRM_IOW( 0x4a, drm_radeon_blit_t)
-#define DRM_IOCTL_RADEON_CP_PACKET DRM_IOWR(0x4b, drm_radeon_packet_t)
+#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( 0x40, drm_radeon_init_t)
+#define DRM_IOCTL_RADEON_CP_START DRM_IO( 0x41)
+#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( 0x42, drm_radeon_cp_stop_t)
+#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( 0x43)
+#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( 0x44)
+#define DRM_IOCTL_RADEON_RESET DRM_IO( 0x45)
+#define DRM_IOCTL_RADEON_PAGEFLIP DRM_IOW( 0x46, drm_radeon_pageflip_t)
+#define DRM_IOCTL_RADEON_SWAP DRM_IO( 0x47)
+#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( 0x48, drm_radeon_clear_t)
+#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( 0x49, drm_radeon_vertex_t)
+#define DRM_IOCTL_RADEON_INDICES DRM_IOW( 0x4a, drm_radeon_indices_t)
+#define DRM_IOCTL_RADEON_BLIT DRM_IOW( 0x4b, drm_radeon_blit_t)
+#define DRM_IOCTL_RADEON_STIPPLE DRM_IOWR(0x4c, drm_radeon_stipple_t)
+#define DRM_IOCTL_RADEON_PACKET DRM_IOWR(0x4d, drm_radeon_packet_t)
/* SiS specific ioctls */
-#define SIS_IOCTL_FB_ALLOC DRM_IOWR( 0x44, drm_sis_mem_t)
-#define SIS_IOCTL_FB_FREE DRM_IOW( 0x45, drm_sis_mem_t)
-#define SIS_IOCTL_AGP_INIT DRM_IOWR( 0x53, drm_sis_agp_t)
-#define SIS_IOCTL_AGP_ALLOC DRM_IOWR( 0x54, drm_sis_mem_t)
-#define SIS_IOCTL_AGP_FREE DRM_IOW( 0x55, drm_sis_mem_t)
-#define SIS_IOCTL_FLIP DRM_IOW( 0x48, drm_sis_flip_t)
-#define SIS_IOCTL_FLIP_INIT DRM_IO( 0x49)
-#define SIS_IOCTL_FLIP_FINAL DRM_IO( 0x50)
+#define SIS_IOCTL_FB_ALLOC DRM_IOWR(0x44, drm_sis_mem_t)
+#define SIS_IOCTL_FB_FREE DRM_IOW( 0x45, drm_sis_mem_t)
+#define SIS_IOCTL_AGP_INIT DRM_IOWR(0x53, drm_sis_agp_t)
+#define SIS_IOCTL_AGP_ALLOC DRM_IOWR(0x54, drm_sis_mem_t)
+#define SIS_IOCTL_AGP_FREE DRM_IOW( 0x55, drm_sis_mem_t)
+#define SIS_IOCTL_FLIP DRM_IOW( 0x48, drm_sis_flip_t)
+#define SIS_IOCTL_FLIP_INIT DRM_IO( 0x49)
+#define SIS_IOCTL_FLIP_FINAL DRM_IO( 0x50)
#endif
diff --git a/linux/r128_cce.c b/linux/r128_cce.c
index d978d53e..c2281fc5 100644
--- a/linux/r128_cce.c
+++ b/linux/r128_cce.c
@@ -86,23 +86,23 @@ static u32 r128_cce_microcode[] = {
};
-#define DO_REMAP(_m) (_m)->handle = drm_ioremap((_m)->offset, (_m)->size)
+#define DO_IOREMAP(_m) (_m)->handle = drm_ioremap((_m)->offset, (_m)->size)
-#define DO_REMAPFREE(_m) \
- do { \
- if ((_m)->handle && (_m)->size) \
- drm_ioremapfree((_m)->handle, (_m)->size); \
+#define DO_IOREMAPFREE(_m) \
+ do { \
+ if ((_m)->handle && (_m)->size) \
+ drm_ioremapfree((_m)->handle, (_m)->size); \
} while (0)
-#define DO_FIND_MAP(_m, _o) \
- do { \
- int _i; \
- for (_i = 0; _i < dev->map_count; _i++) { \
- if (dev->maplist[_i]->offset == _o) { \
- _m = dev->maplist[_i]; \
- break; \
- } \
- } \
+#define DO_FIND_MAP(_m, _o) \
+ do { \
+ int _i; \
+ for (_i = 0; _i < dev->map_count; _i++) { \
+ if (dev->maplist[_i]->offset == _o) { \
+ _m = dev->maplist[_i]; \
+ break; \
+ } \
+ } \
} while (0)
@@ -481,12 +481,12 @@ static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init )
(drm_r128_sarea_t *)((u8 *)dev_priv->sarea->handle +
init->sarea_priv_offset);
- DO_REMAP( dev_priv->cce_ring );
- DO_REMAP( dev_priv->ring_rptr );
- DO_REMAP( dev_priv->buffers );
+ DO_IOREMAP( dev_priv->cce_ring );
+ DO_IOREMAP( dev_priv->ring_rptr );
+ DO_IOREMAP( dev_priv->buffers );
#if 0
if ( !dev_priv->is_pci ) {
- DO_REMAP( dev_priv->agp_textures );
+ DO_IOREMAP( dev_priv->agp_textures );
}
#endif
@@ -521,12 +521,12 @@ static int r128_do_cleanup_cce( drm_device_t *dev )
if ( dev->dev_private ) {
drm_r128_private_t *dev_priv = dev->dev_private;
- DO_REMAPFREE( dev_priv->cce_ring );
- DO_REMAPFREE( dev_priv->ring_rptr );
- DO_REMAPFREE( dev_priv->buffers );
+ DO_IOREMAPFREE( dev_priv->cce_ring );
+ DO_IOREMAPFREE( dev_priv->ring_rptr );
+ DO_IOREMAPFREE( dev_priv->buffers );
#if 0
if ( !dev_priv->is_pci ) {
- DO_REMAPFREE( dev_priv->agp_textures );
+ DO_IOREMAPFREE( dev_priv->agp_textures );
}
#endif
diff --git a/linux/r128_drm.h b/linux/r128_drm.h
index 68a55d5d..57cb5c3d 100644
--- a/linux/r128_drm.h
+++ b/linux/r128_drm.h
@@ -98,7 +98,9 @@
#define R128_LOG_TEX_GRANULARITY 16
#define R128_NR_CONTEXT_REGS 12
-#define R128_TEX_MAXLEVELS 11
+
+#define R128_MAX_TEXTURE_LEVELS 11
+#define R128_MAX_TEXTURE_UNITS 2
#endif /* __R128_SAREA_DEFINES__ */
@@ -142,7 +144,7 @@ typedef struct {
unsigned int tex_cntl;
unsigned int tex_combine_cntl;
unsigned int tex_size_pitch;
- unsigned int tex_offset[R128_TEX_MAXLEVELS];
+ unsigned int tex_offset[R128_MAX_TEXTURE_LEVELS];
unsigned int tex_border_color;
} drm_r128_texture_regs_t;
@@ -158,7 +160,7 @@ typedef struct drm_r128_sarea {
* on firing a vertex buffer.
*/
drm_r128_context_regs_t context_state;
- drm_r128_texture_regs_t tex_state[R128_NR_TEX_HEAPS];
+ drm_r128_texture_regs_t tex_state[R128_MAX_TEXTURE_UNITS];
unsigned int dirty;
unsigned int vertsize;
unsigned int vc_format;
diff --git a/linux/r128_state.c b/linux/r128_state.c
index 3f52c14b..cdeb1bb5 100644
--- a/linux/r128_state.c
+++ b/linux/r128_state.c
@@ -181,14 +181,14 @@ static inline void r128_emit_tex0( drm_r128_private_t *dev_priv )
RING_LOCALS;
DRM_DEBUG( " %s\n", __FUNCTION__ );
- BEGIN_RING( 7 + R128_TEX_MAXLEVELS );
+ BEGIN_RING( 7 + R128_MAX_TEXTURE_LEVELS );
OUT_RING( CCE_PACKET0( R128_PRIM_TEX_CNTL_C,
- 2 + R128_TEX_MAXLEVELS ) );
+ 2 + R128_MAX_TEXTURE_LEVELS ) );
OUT_RING( tex->tex_cntl );
OUT_RING( tex->tex_combine_cntl );
OUT_RING( ctx->tex_size_pitch_c );
- for ( i = 0 ; i < R128_TEX_MAXLEVELS ; i++ ) {
+ for ( i = 0 ; i < R128_MAX_TEXTURE_LEVELS ; i++ ) {
OUT_RING( tex->tex_offset[i] );
}
@@ -207,13 +207,13 @@ static inline void r128_emit_tex1( drm_r128_private_t *dev_priv )
RING_LOCALS;
DRM_DEBUG( " %s\n", __FUNCTION__ );
- BEGIN_RING( 5 + R128_TEX_MAXLEVELS );
+ BEGIN_RING( 5 + R128_MAX_TEXTURE_LEVELS );
OUT_RING( CCE_PACKET0( R128_SEC_TEX_CNTL_C,
- 1 + R128_TEX_MAXLEVELS ) );
+ 1 + R128_MAX_TEXTURE_LEVELS ) );
OUT_RING( tex->tex_cntl );
OUT_RING( tex->tex_combine_cntl );
- for ( i = 0 ; i < R128_TEX_MAXLEVELS ; i++ ) {
+ for ( i = 0 ; i < R128_MAX_TEXTURE_LEVELS ; i++ ) {
OUT_RING( tex->tex_offset[i] );
}
diff --git a/linux/radeon_cp.c b/linux/radeon_cp.c
index 087996c1..68a014cf 100644
--- a/linux/radeon_cp.c
+++ b/linux/radeon_cp.c
@@ -298,23 +298,23 @@ static u32 radeon_cp_microcode[][2] = {
};
-#define DO_REMAP(_m) (_m)->handle = drm_ioremap((_m)->offset, (_m)->size)
+#define DO_IOREMAP(_m) (_m)->handle = drm_ioremap((_m)->offset, (_m)->size)
-#define DO_REMAPFREE(_m) \
- do { \
- if ((_m)->handle && (_m)->size) \
- drm_ioremapfree((_m)->handle, (_m)->size); \
+#define DO_IOREMAPFREE(_m) \
+ do { \
+ if ((_m)->handle && (_m)->size) \
+ drm_ioremapfree((_m)->handle, (_m)->size); \
} while (0)
-#define DO_FIND_MAP(_m, _o) \
- do { \
- int _i; \
- for (_i = 0; _i < dev->map_count; _i++) { \
- if (dev->maplist[_i]->offset == _o) { \
- _m = dev->maplist[_i]; \
- break; \
- } \
- } \
+#define DO_FIND_MAP(_m, _o) \
+ do { \
+ int _i; \
+ for (_i = 0; _i < dev->map_count; _i++) { \
+ if (dev->maplist[_i]->offset == _o) { \
+ _m = dev->maplist[_i]; \
+ break; \
+ } \
+ } \
} while (0)
@@ -327,9 +327,9 @@ int RADEON_READ_PLL(drm_device_t *dev, int addr)
}
-#if 0
static void radeon_status( drm_radeon_private_t *dev_priv )
{
+#if 0
printk( "GUI_STAT = 0x%08x\n",
(unsigned int)RADEON_READ( RADEON_GUI_STAT ) );
printk( "PM4_STAT = 0x%08x\n",
@@ -342,9 +342,17 @@ static void radeon_status( drm_radeon_private_t *dev_priv )
(unsigned int)RADEON_READ( RADEON_PM4_MICRO_CNTL ) );
printk( "PM4_BUFFER_CNTL = 0x%08x\n",
(unsigned int)RADEON_READ( RADEON_PM4_BUFFER_CNTL ) );
-}
#endif
+ printk( "%s:\n", __FUNCTION__ );
+ printk( "RBBM_STATUS = 0x%08x\n",
+ (unsigned int)RADEON_READ( RADEON_RBBM_STATUS ) );
+ printk( "CP_RB_RTPR = 0x%08x\n",
+ (unsigned int)RADEON_READ( RADEON_CP_RB_RPTR ) );
+ printk( "CP_RB_WTPR = 0x%08x\n",
+ (unsigned int)RADEON_READ( RADEON_CP_RB_WPTR ) );
+}
+
/* ================================================================
* Engine, FIFO control
@@ -367,11 +375,12 @@ static int radeon_do_pixcache_flush( drm_radeon_private_t *dev_priv )
udelay( 1 );
}
- DRM_ERROR( "%s failed!\n", __FUNCTION__ );
+ DRM_ERROR( "failed!\n" );
return -EBUSY;
}
-static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv, int entries )
+static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv,
+ int entries )
{
int i;
@@ -382,7 +391,10 @@ static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv, int entries
udelay( 1 );
}
- DRM_ERROR( "%s failed!\n", __FUNCTION__ );
+#if 1
+ DRM_ERROR( "failed!\n" );
+ radeon_status( dev_priv );
+#endif
return -EBUSY;
}
@@ -402,7 +414,9 @@ static int radeon_do_wait_for_idle( drm_radeon_private_t *dev_priv )
udelay( 1 );
}
- DRM_ERROR( "%s failed!\n", __FUNCTION__ );
+#if 0
+ DRM_ERROR( "failed!\n" );
+#endif
return -EBUSY;
}
@@ -436,8 +450,8 @@ static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv )
#if 0
u32 tmp;
- tmp = RADEON_READ( RADEON_PM4_BUFFER_DL_WPTR ) | RADEON_PM4_BUFFER_DL_DONE;
- RADEON_WRITE( RADEON_PM4_BUFFER_DL_WPTR, tmp );
+ tmp = RADEON_READ( RADEON_CP_RB_WPTR ) | (1 << 31);
+ RADEON_WRITE( RADEON_CP_RB_WPTR, tmp );
#endif
}
@@ -445,6 +459,12 @@ static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv )
*/
static int radeon_do_cp_idle( drm_radeon_private_t *dev_priv )
{
+ RING_LOCALS;
+
+ RADEON_WAIT_UNTIL_IDLE();
+ RADEON_FLUSH_CACHE();
+ RADEON_FLUSH_ZCACHE();
+
return radeon_do_wait_for_idle( dev_priv );
}
@@ -452,11 +472,17 @@ static int radeon_do_cp_idle( drm_radeon_private_t *dev_priv )
*/
static void radeon_do_cp_start( drm_radeon_private_t *dev_priv )
{
+ RING_LOCALS;
+
radeon_do_wait_for_idle( dev_priv );
RADEON_WRITE( RADEON_CP_CSQ_CNTL, dev_priv->cp_mode );
dev_priv->cp_running = 1;
+
+ RADEON_WAIT_UNTIL_IDLE();
+ RADEON_FLUSH_CACHE();
+ RADEON_FLUSH_ZCACHE();
}
/* Reset the Concurrent Command Engine. This will not flush any pending
@@ -479,6 +505,14 @@ static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv )
*/
static void radeon_do_cp_stop( drm_radeon_private_t *dev_priv )
{
+ if ( dev_priv->cp_running ) {
+ RING_LOCALS;
+
+ RADEON_WAIT_UNTIL_IDLE();
+ RADEON_FLUSH_CACHE();
+ RADEON_FLUSH_ZCACHE();
+ }
+
RADEON_WRITE( RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );
dev_priv->cp_running = 0;
@@ -553,9 +587,11 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev )
dev_priv->agp_size ) & 0xffff0000)
| ( dev_priv->agp_vm_start >> 16 ) ) );
- ring_start = dev_priv->cp_ring->offset - dev->agp->base;
+ ring_start = (dev_priv->cp_ring->offset
+ - dev->agp->base
+ + dev_priv->agp_vm_start);
- RADEON_WRITE( RADEON_CP_RB_BASE, ring_start + dev_priv->agp_vm_start );
+ RADEON_WRITE( RADEON_CP_RB_BASE, ring_start );
/* Set the write pointer delay */
RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 );
@@ -580,6 +616,12 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev )
/* Turn on bus mastering */
tmp = RADEON_READ( RADEON_BUS_CNTL ) & ~RADEON_BUS_MASTER_DIS;
RADEON_WRITE( RADEON_BUS_CNTL, tmp );
+
+ /* Sync everything up */
+ RADEON_WRITE( RADEON_ISYNC_CNTL, (RADEON_ISYNC_ANY2D_IDLE3D |
+ RADEON_ISYNC_ANY3D_IDLE2D |
+ RADEON_ISYNC_WAIT_IDLEGUI |
+ RADEON_ISYNC_CPSCRATCH_IDLEGUI) );
}
static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
@@ -615,7 +657,6 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
}
dev_priv->cp_mode = init->cp_mode;
- dev_priv->cp_secure = init->cp_secure;
/* Simple idle check.
*/
@@ -635,18 +676,19 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
dev_priv->fb_bpp = init->fb_bpp;
dev_priv->front_offset = init->front_offset;
dev_priv->front_pitch = init->front_pitch;
- dev_priv->front_x = init->front_x;
- dev_priv->front_y = init->front_y;
dev_priv->back_offset = init->back_offset;
dev_priv->back_pitch = init->back_pitch;
- dev_priv->back_x = init->back_x;
- dev_priv->back_y = init->back_y;
dev_priv->depth_bpp = init->depth_bpp;
dev_priv->depth_offset = init->depth_offset;
dev_priv->depth_pitch = init->depth_pitch;
- dev_priv->depth_x = init->depth_x;
- dev_priv->depth_y = init->depth_y;
+
+ dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) |
+ (dev_priv->front_offset >> 10));
+ dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) |
+ (dev_priv->back_offset >> 10));
+ dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) |
+ (dev_priv->depth_offset >> 10));
/* FIXME: We want multiple shared areas, including one shared
* only by the X Server and kernel module.
@@ -673,17 +715,20 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
(drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle +
init->sarea_priv_offset);
- DO_REMAP( dev_priv->cp_ring );
- DO_REMAP( dev_priv->ring_rptr );
- DO_REMAP( dev_priv->buffers );
+ DO_IOREMAP( dev_priv->cp_ring );
+ DO_IOREMAP( dev_priv->ring_rptr );
+ DO_IOREMAP( dev_priv->buffers );
#if 0
if ( !dev_priv->is_pci ) {
- DO_REMAP( dev_priv->agp_textures );
+ DO_IOREMAP( dev_priv->agp_textures );
}
#endif
- dev_priv->agp_vm_start = init->agp_vm_start;
dev_priv->agp_size = init->agp_size;
+ dev_priv->agp_vm_start = RADEON_READ( RADEON_CONFIG_APER_SIZE );
+ dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
+ - dev->agp->base
+ + dev_priv->agp_vm_start);
dev_priv->ring.head = ((__volatile__ u32 *)
dev_priv->ring_rptr->handle);
@@ -721,12 +766,12 @@ static int radeon_do_cleanup_cp( drm_device_t *dev )
if ( dev->dev_private ) {
drm_radeon_private_t *dev_priv = dev->dev_private;
- DO_REMAPFREE( dev_priv->cp_ring );
- DO_REMAPFREE( dev_priv->ring_rptr );
- DO_REMAPFREE( dev_priv->buffers );
+ DO_IOREMAPFREE( dev_priv->cp_ring );
+ DO_IOREMAPFREE( dev_priv->ring_rptr );
+ DO_IOREMAPFREE( dev_priv->buffers );
#if 0
if ( !dev_priv->is_pci ) {
- DO_REMAPFREE( dev_priv->agp_textures );
+ DO_IOREMAPFREE( dev_priv->agp_textures );
}
#endif
@@ -898,6 +943,73 @@ int radeon_engine_reset( struct inode *inode, struct file *filp,
/* ================================================================
+ * Page flipping
+ */
+
+static int radeon_do_init_pageflip( drm_device_t *dev )
+{
+ drm_radeon_private_t *dev_priv = dev->dev_private;
+ u32 crtc_offset_cntl;
+ DRM_DEBUG( "%s\n", __FUNCTION__ );
+
+ RADEON_WRITE( RADEON_CRTC_OFFSET, dev_priv->front_offset );
+
+ crtc_offset_cntl = RADEON_READ( RADEON_CRTC_OFFSET_CNTL );
+ RADEON_WRITE( RADEON_CRTC_OFFSET_CNTL,
+ crtc_offset_cntl | RADEON_CRTC_OFFSET_FLIP_CNTL );
+
+ dev_priv->page_flipping = 1;
+ dev_priv->current_page = 0;
+
+ return 0;
+}
+
+int radeon_do_cleanup_pageflip( drm_device_t *dev )
+{
+ drm_radeon_private_t *dev_priv = dev->dev_private;
+ u32 crtc_offset_cntl;
+ DRM_DEBUG( "%s\n", __FUNCTION__ );
+
+ RADEON_WRITE( RADEON_CRTC_OFFSET, dev_priv->front_offset );
+
+ crtc_offset_cntl = RADEON_READ( RADEON_CRTC_OFFSET_CNTL );
+ RADEON_WRITE( RADEON_CRTC_OFFSET_CNTL,
+ crtc_offset_cntl & ~RADEON_CRTC_OFFSET_FLIP_CNTL );
+
+ dev_priv->page_flipping = 0;
+ dev_priv->current_page = 0;
+
+ return 0;
+}
+
+int radeon_cp_pageflip( struct inode *inode, struct file *filp,
+ unsigned int cmd, unsigned long arg )
+{
+ drm_file_t *priv = filp->private_data;
+ drm_device_t *dev = priv->dev;
+ drm_radeon_pageflip_t p;
+
+ if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
+ dev->lock.pid != current->pid ) {
+ DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
+ return -EINVAL;
+ }
+
+ if ( copy_from_user( &p, (drm_radeon_pageflip_t *)arg, sizeof(p) ) )
+ return -EFAULT;
+
+ switch ( p.func ) {
+ case RADEON_INIT_PAGEFLIP:
+ return radeon_do_init_pageflip( dev );
+ case RADEON_CLEANUP_PAGEFLIP:
+ return radeon_do_cleanup_pageflip( dev );
+ }
+
+ return -EINVAL;
+}
+
+
+/* ================================================================
* Freelist management
*/
#define RADEON_BUFFER_USED 0xffffffff
@@ -965,8 +1077,13 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev )
for ( i = 0 ; i < dma->buf_count ; i++ ) {
buf = dma->buflist[i];
buf_priv = buf->dev_private;
- if ( buf->pid == 0 )
+ if ( buf->pid == 0 ) {
+ DRM_DEBUG( " ret buf=%d last=%d pid=0\n",
+ buf->idx, dev_priv->last_buf );
return buf;
+ }
+ DRM_DEBUG( " skipping buf=%d pid=%d\n",
+ buf->idx, buf->pid );
}
#if ROTATE_BUFS
@@ -988,8 +1105,12 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev )
* can now be used.
*/
buf->pending = 0;
+ DRM_DEBUG( " ret buf=%d last=%d age=%d done=%d\n", buf->idx, dev_priv->last_buf, buf_priv->age, done_age );
return buf;
}
+ DRM_DEBUG( " skipping buf=%d age=%d done=%d\n",
+ buf->idx, buf_priv->age,
+ done_age );
#if ROTATE_BUFS
start = 0;
#endif
@@ -1041,6 +1162,7 @@ int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n )
}
/* FIXME: This return value is ignored in the BEGIN_RING macro! */
+ DRM_ERROR( "failed!\n" );
return -EBUSY;
}
@@ -1053,6 +1175,13 @@ void radeon_update_ring_snapshot( drm_radeon_private_t *dev_priv )
atomic_inc( &dev_priv->idle_count );
if ( ring->space <= 0 )
ring->space += ring->size;
+
+ if ( 0 ) {
+ DRM_INFO( "update_ring: size=0x%x space=%d\n",
+ ring->size, ring->space );
+ DRM_INFO( "tail=0x%04x\n", ring->tail );
+ DRM_INFO( "head=0x%04x\n", *ring->head );
+ }
}
#if 0
@@ -1220,7 +1349,7 @@ static int radeon_do_cp_packet( drm_radeon_private_t *dev_priv,
int c;
RING_LOCALS;
- /* FIXME: Optimize!!! */
+ /* FIXME: Optimize!!! GH: Why bother? */
for ( c = 0 ; c < count ; c++ ) {
BEGIN_RING( 1 );
OUT_RING( commands[c] );
@@ -1243,15 +1372,14 @@ int radeon_cp_packet( struct inode *inode, struct file *filp,
u32 *buffer;
int ret;
- if ( dev_priv->cp_secure && !capable( CAP_SYS_ADMIN ) ) {
- DRM_ERROR( "radeon_cp_packet called in secure mode "
- "without permission\n" );
+ if ( !capable( CAP_SYS_ADMIN ) ) {
+ DRM_ERROR( "radeon_cp_packet called without permission\n" );
return -EACCES;
}
if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
dev->lock.pid != current->pid ) {
- DRM_ERROR( "radeon_cp_packet called without lock held\n" );
+ DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
return -EINVAL;
}
diff --git a/linux/radeon_drm.h b/linux/radeon_drm.h
index 3f890661..73eabd9c 100644
--- a/linux/radeon_drm.h
+++ b/linux/radeon_drm.h
@@ -24,13 +24,13 @@
* DEALINGS IN THE SOFTWARE.
*
* Authors:
- * Kevin E. Martin <martin@valinux.com>
* Gareth Hughes <gareth@valinux.com>
+ * Kevin E. Martin <martin@valinux.com>
*
*/
-#ifndef _RADEON_DRM_H_
-#define _RADEON_DRM_H_
+#ifndef __RADEON_DRM_H__
+#define __RADEON_DRM_H__
/* WARNING: If you change any of these defines, make sure to change the
* defines in the X server file (radeon_sarea.h)
@@ -38,7 +38,8 @@
#ifndef __RADEON_SAREA_DEFINES__
#define __RADEON_SAREA_DEFINES__
-/* What needs to be changed for the current vertex buffer? */
+/* What needs to be changed for the current vertex buffer?
+ */
#define RADEON_UPLOAD_CONTEXT 0x00000001
#define RADEON_UPLOAD_VERTFMT 0x00000002
#define RADEON_UPLOAD_LINE 0x00000004
@@ -62,7 +63,8 @@
#define RADEON_BACK 0x2
#define RADEON_DEPTH 0x4
-/* Primitive types */
+/* Primitive types
+ */
#define RADEON_POINTS 0x1
#define RADEON_LINES 0x2
#define RADEON_LINE_STRIP 0x3
@@ -70,21 +72,17 @@
#define RADEON_TRIANGLE_FAN 0x5
#define RADEON_TRIANGLE_STRIP 0x6
-/* Vertex/indirect buffer size */
-#if 1
+/* Vertex/indirect buffer size
+ */
#define RADEON_BUFFER_SIZE 16384
-#else
-#define RADEON_BUFFER_SIZE (128 * 1024)
-#endif
-/* Byte offsets for indirect buffer data */
+/* Byte offsets for indirect buffer data
+ */
#define RADEON_INDEX_PRIM_OFFSET 20
#define RADEON_HOSTDATA_BLIT_OFFSET 32
-/* 2048x2048 @ 32bpp texture requires this many indirect buffers */
-#define RADEON_MAX_BLIT_BUFFERS ((2048 * 2048 * 4)/RADEON_BUFFER_SIZE)
-
-/* Keep these small for testing. */
+/* Keep these small for testing
+ */
#define RADEON_NR_SAREA_CLIPRECTS 12
/* There are 2 heaps (local/AGP). Each region within a heap is a
@@ -93,11 +91,11 @@
#define RADEON_LOCAL_TEX_HEAP 0
#define RADEON_AGP_TEX_HEAP 1
#define RADEON_NR_TEX_HEAPS 2
-#define RADEON_NR_TEX_REGIONS 16
+#define RADEON_NR_TEX_REGIONS 64
#define RADEON_LOG_TEX_GRANULARITY 16
-#define RADEON_NR_CONTEXT_REGS 12
-#define RADEON_TEX_MAXLEVELS 11
+#define RADEON_MAX_TEXTURE_LEVELS 11
+#define RADEON_MAX_TEXTURE_UNITS 3
#endif /* __RADEON_SAREA_DEFINES__ */
@@ -110,7 +108,7 @@ typedef struct {
typedef struct {
/* Context state */
- unsigned int pp_misc; /* 0x1c14 */
+ unsigned int pp_misc; /* 0x1c14 */
unsigned int pp_fog_color;
unsigned int re_solid_color;
unsigned int rb3d_blendcntl;
@@ -118,7 +116,7 @@ typedef struct {
unsigned int rb3d_depthpitch;
unsigned int rb3d_zstencilcntl;
- unsigned int pp_cntl; /* 0x1c38 */
+ unsigned int pp_cntl; /* 0x1c38 */
unsigned int rb3d_cntl;
unsigned int rb3d_coloroffset;
unsigned int re_width_height;
@@ -126,27 +124,30 @@ typedef struct {
unsigned int se_cntl;
/* Vertex format state */
- unsigned int se_coord_fmt; /* 0x1c50 */
+ unsigned int se_coord_fmt; /* 0x1c50 */
/* Line state */
- unsigned int re_line_pattern; /* 0x1cd0 */
+ unsigned int re_line_pattern; /* 0x1cd0 */
unsigned int re_line_state;
- unsigned int se_line_width; /* 0x1db8 */
+ unsigned int se_line_width; /* 0x1db8 */
+
+ /* Texture state */
+ unsigned int pp_tfactor;
/* Bumpmap state */
- unsigned int pp_lum_matrix; /* 0x1d00 */
+ unsigned int pp_lum_matrix; /* 0x1d00 */
- unsigned int pp_rot_matrix_0; /* 0x1d58 */
+ unsigned int pp_rot_matrix_0; /* 0x1d58 */
unsigned int pp_rot_matrix_1;
/* Mask state */
- unsigned int rb3d_stencilrefmask; /* 0x1d7c */
+ unsigned int rb3d_stencilrefmask; /* 0x1d7c */
unsigned int rb3d_ropcntl;
unsigned int rb3d_planemask;
/* Viewport state */
- unsigned int se_vport_xscale; /* 0x1d98 */
+ unsigned int se_vport_xscale; /* 0x1d98 */
unsigned int se_vport_xoffset;
unsigned int se_vport_yscale;
unsigned int se_vport_yoffset;
@@ -154,11 +155,11 @@ typedef struct {
unsigned int se_vport_zoffset;
/* Setup state */
- unsigned int se_cntl_status; /* 0x2140 */
+ unsigned int se_cntl_status; /* 0x2140 */
#ifdef TCL_ENABLE
/* TCL state */
- radeon_color_regs_t se_tcl_material_emmissive; /* 0x2210 */
+ radeon_color_regs_t se_tcl_material_emmissive; /* 0x2210 */
radeon_color_regs_t se_tcl_material_ambient;
radeon_color_regs_t se_tcl_material_diffuse;
radeon_color_regs_t se_tcl_material_specular;
@@ -174,18 +175,18 @@ typedef struct {
#endif
/* Misc state */
- unsigned int re_top_left; /* 0x26c0 */
+ unsigned int re_top_left; /* 0x26c0 */
unsigned int re_misc;
} drm_radeon_context_regs_t;
-/* Setup registers for each texture unit */
+/* Setup registers for each texture unit
+ */
typedef struct {
unsigned int pp_txfilter;
unsigned int pp_txformat;
unsigned int pp_txoffset;
unsigned int pp_txcblend;
unsigned int pp_txablend;
- unsigned int pp_tfactor;
unsigned int pp_border_color;
@@ -206,7 +207,7 @@ typedef struct {
* on firing a vertex buffer.
*/
drm_radeon_context_regs_t context_state;
- drm_radeon_texture_regs_t tex_state[RADEON_NR_TEX_HEAPS];
+ drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
unsigned int dirty;
unsigned int vertsize;
unsigned int vc_format;
@@ -238,19 +239,15 @@ typedef struct drm_radeon_init {
int sarea_priv_offset;
int is_pci;
int cp_mode;
- int cp_secure;
int agp_size;
int ring_size;
int usec_timeout;
unsigned int fb_bpp;
unsigned int front_offset, front_pitch;
- unsigned int front_x, front_y;
unsigned int back_offset, back_pitch;
- unsigned int back_x, back_y;
unsigned int depth_bpp;
unsigned int depth_offset, depth_pitch;
- unsigned int depth_x, depth_y;
unsigned int fb_offset;
unsigned int mmio_offset;
@@ -258,8 +255,6 @@ typedef struct drm_radeon_init {
unsigned int ring_rptr_offset;
unsigned int buffers_offset;
unsigned int agp_textures_offset;
-
- unsigned int agp_vm_start;
} drm_radeon_init_t;
typedef struct drm_radeon_cp_stop {
@@ -267,13 +262,18 @@ typedef struct drm_radeon_cp_stop {
int idle;
} drm_radeon_cp_stop_t;
+typedef struct drm_radeon_pageflip {
+ enum {
+ RADEON_INIT_PAGEFLIP = 0x01,
+ RADEON_CLEANUP_PAGEFLIP = 0x02
+ } func;
+} drm_radeon_pageflip_t;
+
typedef struct drm_radeon_clear {
unsigned int flags;
int x, y, w, h;
unsigned int clear_color;
unsigned int clear_depth;
- unsigned int color_mask;
- unsigned int depth_mask;
} drm_radeon_clear_t;
typedef struct drm_radeon_vertex {
@@ -291,21 +291,19 @@ typedef struct drm_radeon_indices {
int discard; /* Client finished with buffer? */
} drm_radeon_indices_t;
-typedef struct drm_radeon_blit_rect {
- int index;
- unsigned short x, y;
- unsigned short width, height;
- int padding;
-} drm_radeon_blit_rect_t;
-
typedef struct drm_radeon_blit {
+ int idx;
int pitch;
int offset;
int format;
- drm_radeon_blit_rect_t *rects;
- int count;
+ unsigned short x, y;
+ unsigned short width, height;
} drm_radeon_blit_t;
+typedef struct drm_radeon_stipple {
+ unsigned int *mask;
+} drm_radeon_stipple_t;
+
typedef struct drm_radeon_packet {
unsigned int *buffer;
int count;
diff --git a/linux/radeon_drv.c b/linux/radeon_drv.c
index 35539766..93ad2f0d 100644
--- a/linux/radeon_drv.c
+++ b/linux/radeon_drv.c
@@ -34,7 +34,7 @@
#define RADEON_NAME "radeon"
#define RADEON_DESC "ATI Radeon"
-#define RADEON_DATE "20001223"
+#define RADEON_DATE "20001228"
#define RADEON_MAJOR 1
#define RADEON_MINOR 0
#define RADEON_PATCHLEVEL 0
@@ -105,18 +105,20 @@ static drm_ioctl_desc_t radeon_ioctls[] = {
[DRM_IOCTL_NR(DRM_IOCTL_AGP_UNBIND)] = { drm_agp_unbind, 1, 1 },
#endif
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_RESET)] = { radeon_engine_reset, 1, 0 },
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_INIT)] = { radeon_cp_init, 1, 1 },
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_START)] = { radeon_cp_start, 1, 1 },
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_STOP)] = { radeon_cp_stop, 1, 1 },
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_RESET)] = { radeon_cp_reset, 1, 1 },
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_IDLE)] = { radeon_cp_idle, 1, 0 },
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_SWAP)] = { radeon_cp_swap, 1, 0 },
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_CLEAR)] = { radeon_cp_clear, 1, 0 },
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_VERTEX)] = { radeon_cp_vertex, 1, 0 },
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_INDICES)] = { radeon_cp_indices, 1, 0 },
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_BLIT)] = { radeon_cp_blit, 1, 0 },
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_PACKET)] = { radeon_cp_packet, 1, 0 },
+ [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_INIT)] = { radeon_cp_init, 1, 1 },
+ [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_START)]= { radeon_cp_start, 1, 1 },
+ [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_STOP)] = { radeon_cp_stop, 1, 1 },
+ [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_RESET)]= { radeon_cp_reset, 1, 1 },
+ [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_IDLE)] = { radeon_cp_idle, 1, 0 },
+ [DRM_IOCTL_NR(DRM_IOCTL_RADEON_RESET)] = { radeon_engine_reset,1,0 },
+ [DRM_IOCTL_NR(DRM_IOCTL_RADEON_PAGEFLIP)]= { radeon_cp_pageflip,1, 0 },
+ [DRM_IOCTL_NR(DRM_IOCTL_RADEON_SWAP)] = { radeon_cp_swap, 1, 0 },
+ [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CLEAR)] = { radeon_cp_clear, 1, 0 },
+ [DRM_IOCTL_NR(DRM_IOCTL_RADEON_VERTEX)] = { radeon_cp_vertex, 1, 0 },
+ [DRM_IOCTL_NR(DRM_IOCTL_RADEON_INDICES)] = { radeon_cp_indices, 1, 0 },
+ [DRM_IOCTL_NR(DRM_IOCTL_RADEON_BLIT)] = { radeon_cp_blit, 1, 0 },
+ [DRM_IOCTL_NR(DRM_IOCTL_RADEON_STIPPLE)] = { radeon_cp_stipple, 1, 0 },
+ [DRM_IOCTL_NR(DRM_IOCTL_RADEON_PACKET)] = { radeon_cp_packet, 1, 0 },
};
#define RADEON_IOCTL_COUNT DRM_ARRAY_SIZE(radeon_ioctls)
@@ -328,7 +330,7 @@ static int radeon_takedown(drm_device_t *dev)
/* radeon_init is called via init_module at module load time, or via
* linux/init/main.c (this is not currently supported). */
-static int radeon_init(void)
+static int __init radeon_init(void)
{
int retcode;
drm_device_t *dev = &radeon_device;
@@ -392,7 +394,7 @@ static int radeon_init(void)
/* radeon_cleanup is called via cleanup_module at module unload time. */
-static void radeon_cleanup(void)
+static void __exit radeon_cleanup(void)
{
drm_device_t *dev = &radeon_device;
@@ -484,7 +486,17 @@ int radeon_release(struct inode *inode, struct file *filp)
lock_kernel();
dev = priv->dev;
+
DRM_DEBUG("open_count = %d\n", dev->open_count);
+
+ /* Force the cleanup of page flipping when required */
+ if ( dev->dev_private ) {
+ drm_radeon_private_t *dev_priv = dev->dev_private;
+ if ( dev_priv->page_flipping ) {
+ radeon_do_cleanup_pageflip( dev );
+ }
+ }
+
if (!(retcode = drm_release(inode, filp))) {
#if LINUX_VERSION_CODE < 0x020333
MOD_DEC_USE_COUNT; /* Needed before Linux 2.3.51 */
diff --git a/linux/radeon_drv.h b/linux/radeon_drv.h
index 016e24de..93c83e9e 100644
--- a/linux/radeon_drv.h
+++ b/linux/radeon_drv.h
@@ -56,11 +56,11 @@ typedef struct drm_radeon_private {
drm_radeon_ring_buffer_t ring;
drm_radeon_sarea_t *sarea_priv;
- u32 agp_vm_start;
int agp_size;
+ u32 agp_vm_start;
+ u32 agp_buffers_offset;
int cp_mode;
- int cp_secure;
int cp_running;
drm_radeon_freelist_t *head;
@@ -79,21 +79,22 @@ typedef struct drm_radeon_private {
atomic_t idle_count;
+ int page_flipping;
+ int current_page;
+
unsigned int fb_bpp;
unsigned int front_offset;
unsigned int front_pitch;
- unsigned int front_x;
- unsigned int front_y;
unsigned int back_offset;
unsigned int back_pitch;
- unsigned int back_x;
- unsigned int back_y;
unsigned int depth_bpp;
unsigned int depth_offset;
unsigned int depth_pitch;
- unsigned int depth_x;
- unsigned int depth_y;
+
+ u32 front_pitch_offset;
+ u32 back_pitch_offset;
+ u32 depth_pitch_offset;
drm_map_t *sarea;
drm_map_t *fb;
@@ -137,6 +138,8 @@ extern int radeon_cp_idle( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int radeon_engine_reset( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
+extern int radeon_cp_pageflip( struct inode *inode, struct file *filp,
+ unsigned int cmd, unsigned long arg );
extern int radeon_cp_packet( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int radeon_cp_buffers( struct inode *inode, struct file *filp,
@@ -148,6 +151,8 @@ extern drm_buf_t *radeon_freelist_get( drm_device_t *dev );
extern int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n );
extern void radeon_update_ring_snapshot( drm_radeon_private_t *dev_priv );
+extern int radeon_do_cleanup_pageflip( drm_device_t *dev );
+
/* radeon_state.c */
extern int radeon_cp_clear( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
@@ -159,6 +164,8 @@ extern int radeon_cp_indices( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
extern int radeon_cp_blit( struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg );
+extern int radeon_cp_stipple( struct inode *inode, struct file *filp,
+ unsigned int cmd, unsigned long arg );
/* radeon_bufs.c */
extern int radeon_addbufs(struct inode *inode, struct file *filp,
@@ -190,14 +197,24 @@ extern int radeon_context_switch_complete(drm_device_t *dev, int new);
* for Radeon kernel driver.
*/
+#define RADEON_AUX_SCISSOR_CNTL 0x26f0
+# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
+# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
+# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
+# define RADEON_SCISSOR_0_ENABLE (1 << 28)
+# define RADEON_SCISSOR_1_ENABLE (1 << 29)
+# define RADEON_SCISSOR_2_ENABLE (1 << 30)
+
#define RADEON_BUS_CNTL 0x0030
# define RADEON_BUS_MASTER_DIS (1 << 6)
#define RADEON_CLOCK_CNTL_DATA 0x000c
# define RADEON_PLL_WR_EN (1 << 7)
#define RADEON_CLOCK_CNTL_INDEX 0x0008
-
#define RADEON_CONFIG_APER_SIZE 0x0108
+#define RADEON_CRTC_OFFSET 0x0224
+#define RADEON_CRTC_OFFSET_CNTL 0x0228
+# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
#define RADEON_DP_GUI_MASTER_CNTL 0x146c
# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
@@ -224,6 +241,19 @@ extern int radeon_context_switch_complete(drm_device_t *dev, int new);
#define RADEON_GUI_SCRATCH_REG4 0x15f0
#define RADEON_GUI_SCRATCH_REG5 0x15f4
+#define RADEON_HOST_PATH_CNTL 0x0130
+# define RADEON_HDP_SOFT_RESET (1 << 26)
+# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
+# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
+
+#define RADEON_ISYNC_CNTL 0x1724
+# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
+# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
+# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
+# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
+# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
+# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
+
#define RADEON_MC_AGP_LOCATION 0x014c
#define RADEON_MC_FB_LOCATION 0x0148
#define RADEON_MCLK_CNTL 0x0012
@@ -240,6 +270,8 @@ extern int radeon_context_switch_complete(drm_device_t *dev, int new);
#define RADEON_PP_TXFILTER_2 0x1c84
#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
+# define RADEON_RB2D_DC_FLUSH (3 << 0)
+# define RADEON_RB2D_DC_FREE (3 << 2)
# define RADEON_RB2D_DC_FLUSH_ALL 0xf
# define RADEON_RB2D_DC_BUSY (1 << 31)
#define RADEON_RB3D_CNTL 0x1c3c
@@ -248,6 +280,11 @@ extern int radeon_context_switch_complete(drm_device_t *dev, int new);
#define RADEON_RB3D_DEPTHOFFSET 0x1c24
#define RADEON_RB3D_PLANEMASK 0x1d84
#define RADEON_RB3D_STENCILREFMASK 0x1d7c
+#define RADEON_RB3D_ZCACHE_MODE 0x3250
+#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
+# define RADEON_RB3D_ZC_FLUSH (1 << 0)
+# define RADEON_RB3D_ZC_FREE (1 << 2)
+# define RADEON_RB3D_ZC_BUSY (1 << 31)
#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
# define RADEON_Z_TEST_MASK (7 << 4)
# define RADEON_Z_TEST_ALWAYS (7 << 4)
@@ -267,6 +304,12 @@ extern int radeon_context_switch_complete(drm_device_t *dev, int new);
#define RADEON_RE_LINE_PATTERN 0x1cd0
#define RADEON_RE_TOP_LEFT 0x26c0
+#define RADEON_SCISSOR_TL_0 0x1cd8
+#define RADEON_SCISSOR_BR_0 0x1cdc
+#define RADEON_SCISSOR_TL_1 0x1ce0
+#define RADEON_SCISSOR_BR_1 0x1ce4
+#define RADEON_SCISSOR_TL_2 0x1ce8
+#define RADEON_SCISSOR_BR_2 0x1cec
#define RADEON_SE_COORD_FMT 0x1c50
#define RADEON_SE_CNTL 0x1c4c
# define RADEON_BFACE_SOLID (3 << 1)
@@ -278,6 +321,57 @@ extern int radeon_context_switch_complete(drm_device_t *dev, int new);
#define RADEON_SE_CNTL_STATUS 0x2140
#define RADEON_SE_LINE_WIDTH 0x1db8
#define RADEON_SE_VPORT_XSCALE 0x1d98
+#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
+#define RADEON_SURFACE_ACCESS_CLR 0x0bfc
+#define RADEON_SURFACE_CNTL 0x0b00
+# define RADEON_SURF_TRANSLATION_DIS (1 << 8)
+# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
+# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
+# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
+# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
+# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
+# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
+# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
+# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
+#define RADEON_SURFACE0_INFO 0x0b0c
+# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
+# define RADEON_SURF_TILE_MODE_MASK (3 << 16)
+# define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
+# define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
+# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
+# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
+#define RADEON_SURFACE0_LOWER_BOUND 0x0b04
+#define RADEON_SURFACE0_UPPER_BOUND 0x0b08
+#define RADEON_SURFACE1_INFO 0x0b1c
+#define RADEON_SURFACE1_LOWER_BOUND 0x0b14
+#define RADEON_SURFACE1_UPPER_BOUND 0x0b18
+#define RADEON_SURFACE2_INFO 0x0b2c
+#define RADEON_SURFACE2_LOWER_BOUND 0x0b24
+#define RADEON_SURFACE2_UPPER_BOUND 0x0b28
+#define RADEON_SURFACE3_INFO 0x0b3c
+#define RADEON_SURFACE3_LOWER_BOUND 0x0b34
+#define RADEON_SURFACE3_UPPER_BOUND 0x0b38
+#define RADEON_SURFACE4_INFO 0x0b4c
+#define RADEON_SURFACE4_LOWER_BOUND 0x0b44
+#define RADEON_SURFACE4_UPPER_BOUND 0x0b48
+#define RADEON_SURFACE5_INFO 0x0b5c
+#define RADEON_SURFACE5_LOWER_BOUND 0x0b54
+#define RADEON_SURFACE5_UPPER_BOUND 0x0b58
+#define RADEON_SURFACE6_INFO 0x0b6c
+#define RADEON_SURFACE6_LOWER_BOUND 0x0b64
+#define RADEON_SURFACE6_UPPER_BOUND 0x0b68
+#define RADEON_SURFACE7_INFO 0x0b7c
+#define RADEON_SURFACE7_LOWER_BOUND 0x0b74
+#define RADEON_SURFACE7_UPPER_BOUND 0x0b78
+#define RADEON_SW_SEMAPHORE 0x013c
+
+#define RADEON_WAIT_UNTIL 0x1720
+# define RADEON_WAIT_CRTC_PFLIP (1 << 0)
+# define RADEON_WAIT_2D_IDLE (1 << 14)
+# define RADEON_WAIT_3D_IDLE (1 << 15)
+# define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
+# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
+# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
/* CP registers */
@@ -316,6 +410,7 @@ extern int radeon_context_switch_complete(drm_device_t *dev, int new);
#define RADEON_CP_PACKET2 0x80000000
#define RADEON_CP_PACKET3 0xC0000000
# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
+# define RADEON_WAIT_FOR_IDLE 0x00002600
# define RADEON_3D_DRAW_IMMD 0x00002900
# define RADEON_CNTL_HOSTDATA_BLT 0x00009400
# define RADEON_CNTL_PAINT_MULTI 0x00009A00
@@ -351,6 +446,7 @@ extern int radeon_context_switch_complete(drm_device_t *dev, int new);
#define RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE 0x00000100
#define RADEON_CP_VC_CNTL_NUM_SHIFT 16
+#define RADEON_COLOR_FORMAT_CI8 2
#define RADEON_COLOR_FORMAT_ARGB1555 3
#define RADEON_COLOR_FORMAT_RGB565 4
#define RADEON_COLOR_FORMAT_ARGB8888 6
@@ -362,8 +458,17 @@ extern int radeon_context_switch_complete(drm_device_t *dev, int new);
#define RADEON_COLOR_FORMAT_aYUV444 14
#define RADEON_COLOR_FORMAT_ARGB4444 15
+#define RADEON_TXF_8BPP_I 0
+#define RADEON_TXF_16BPP_AI88 1
+#define RADEON_TXF_8BPP_RGB332 2
+#define RADEON_TXF_16BPP_ARGB1555 3
+#define RADEON_TXF_16BPP_RGB565 4
+#define RADEON_TXF_16BPP_ARGB4444 5
+#define RADEON_TXF_32BPP_ARGB8888 6
+#define RADEON_TXF_32BPP_RGBA8888 7
+
/* Constants */
-#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
+#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
#define RADEON_LAST_FRAME_REG RADEON_GUI_SCRATCH_REG0
#define RADEON_LAST_DISPATCH_REG RADEON_GUI_SCRATCH_REG1
@@ -404,6 +509,52 @@ extern int RADEON_READ_PLL(drm_device_t *dev, int addr);
(RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
+/*
+ */
+
+#define RADEON_WAIT_UNTIL_IDLE() \
+do { \
+ BEGIN_RING( 2 ); \
+ \
+ OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
+ OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
+ RADEON_WAIT_3D_IDLECLEAN | \
+ RADEON_WAIT_HOST_IDLECLEAN) ); \
+ \
+ ADVANCE_RING(); \
+} while (0)
+
+#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() \
+do { \
+ BEGIN_RING( 2 ); \
+ \
+ OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
+ OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
+ \
+ ADVANCE_RING(); \
+} while (0)
+
+#define RADEON_FLUSH_CACHE() \
+do { \
+ BEGIN_RING( 2 ); \
+ \
+ OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \
+ OUT_RING( RADEON_RB2D_DC_FLUSH ); \
+ \
+ ADVANCE_RING(); \
+} while (0)
+
+#define RADEON_FLUSH_ZCACHE() \
+do { \
+ BEGIN_RING( 2 ); \
+ \
+ OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
+ OUT_RING( RADEON_RB3D_ZC_FLUSH ); \
+ \
+ ADVANCE_RING(); \
+} while (0)
+
+
#define radeon_flush_write_combine() mb()
diff --git a/linux/radeon_state.c b/linux/radeon_state.c
index 8253e9f2..c99e1ad7 100644
--- a/linux/radeon_state.c
+++ b/linux/radeon_state.c
@@ -23,8 +23,8 @@
* DEALINGS IN THE SOFTWARE.
*
* Authors:
- * Kevin E. Martin <martin@valinux.com>
* Gareth Hughes <gareth@valinux.com>
+ * Kevin E. Martin <martin@valinux.com>
*
*/
@@ -32,11 +32,10 @@
#include "drmP.h"
#include "radeon_drv.h"
#include "drm.h"
+#include <linux/delay.h>
/* This must be defined to 1 for now */
-#define USE_OLD_BLITS 1
-
-static drm_radeon_blit_rect_t rects[RADEON_MAX_BLIT_BUFFERS];
+#define USE_OLD_BLITS 0
/* ================================================================
@@ -47,42 +46,39 @@ static void radeon_emit_clip_rects( drm_radeon_private_t *dev_priv,
drm_clip_rect_t *boxes, int count )
{
#if 0
- unsigned int aux_sc_cntl = 0x00000000;
+ u32 aux_scissor_cntl = 0x00000000;
RING_LOCALS;
- DRM_DEBUG( " %s\n", __FUNCTION__ );
+ DRM_INFO( " %s: count=%d\n", __FUNCTION__, count );
BEGIN_RING( 17 );
if ( count >= 1 ) {
- OUT_RING( CP_PACKET0( RADEON_AUX1_SC_LEFT, 3 ) );
- OUT_RING( boxes[0].x1 );
- OUT_RING( boxes[0].x2 - 1 );
- OUT_RING( boxes[0].y1 );
- OUT_RING( boxes[0].y2 - 1 );
+ OUT_RING( CP_PACKET0( RADEON_SCISSOR_TL_0, 3 ) );
+ OUT_RING( (boxes[0].y1 << 16) | boxes[0].x1 );
+ OUT_RING( ((boxes[0].y2 - 1) << 16) | (boxes[0].x2 - 1) );
- aux_sc_cntl |= (RADEON_AUX1_SC_EN | RADEON_AUX1_SC_MODE_OR);
+ aux_scissor_cntl |= (RADEON_SCISSOR_0_ENABLE |
+ 0 /* RADEON_AUX1_SC_MODE_OR */);
}
if ( count >= 2 ) {
- OUT_RING( CP_PACKET0( RADEON_AUX2_SC_LEFT, 3 ) );
- OUT_RING( boxes[1].x1 );
- OUT_RING( boxes[1].x2 - 1 );
- OUT_RING( boxes[1].y1 );
- OUT_RING( boxes[1].y2 - 1 );
+ OUT_RING( CP_PACKET0( RADEON_SCISSOR_TL_1, 3 ) );
+ OUT_RING( (boxes[1].y1 << 16) | boxes[1].x1 );
+ OUT_RING( ((boxes[1].y2 - 1) << 16) | (boxes[1].x2 - 1) );
- aux_sc_cntl |= (RADEON_AUX2_SC_EN | RADEON_AUX2_SC_MODE_OR);
+ aux_scissor_cntl |= (RADEON_SCISSOR_1_ENABLE |
+ 0 /* RADEON_AUX2_SC_MODE_OR */);
}
if ( count >= 3 ) {
- OUT_RING( CP_PACKET0( RADEON_AUX3_SC_LEFT, 3 ) );
- OUT_RING( boxes[2].x1 );
- OUT_RING( boxes[2].x2 - 1 );
- OUT_RING( boxes[2].y1 );
- OUT_RING( boxes[2].y2 - 1 );
+ OUT_RING( CP_PACKET0( RADEON_SCISSOR_TL_2, 3 ) );
+ OUT_RING( (boxes[2].y1 << 16) | boxes[2].x1 );
+ OUT_RING( ((boxes[2].y2 - 1) << 16) | (boxes[2].x2 - 1) );
- aux_sc_cntl |= (RADEON_AUX3_SC_EN | RADEON_AUX3_SC_MODE_OR);
+ aux_scissor_cntl |= (RADEON_SCISSOR_2_ENABLE |
+ 0 /* RADEON_AUX3_SC_MODE_OR */);
}
- OUT_RING( CP_PACKET0( RADEON_AUX_SC_CNTL, 0 ) );
- OUT_RING( aux_sc_cntl );
+ OUT_RING( CP_PACKET0( RADEON_AUX_SCISSOR_CNTL, 0 ) );
+ OUT_RING( aux_scissor_cntl );
ADVANCE_RING();
#endif
@@ -215,11 +211,11 @@ static inline void radeon_emit_setup( drm_radeon_private_t *dev_priv )
DRM_DEBUG( " %s\n", __FUNCTION__ );
/* Note this duplicates the uploading of se_cntl, which is part
- of the context, but adding it here optimizes the reduced
- primitive change since we currently render points and lines
- with triangles. In the future, we probably won't need this
- optimization. */
-
+ * of the context, but adding it here optimizes the reduced
+ * primitive change since we currently render points and lines
+ * with triangles. In the future, we probably won't need this
+ * optimization.
+ */
#if 0
/* Why doesn't CP_PACKET1 work? */
BEGIN_RING( 3 );
@@ -274,8 +270,9 @@ static inline void radeon_emit_tcl( drm_radeon_private_t *dev_priv )
OUT_RING( ctx->se_tcl_ucp_vert_blend_ctl );
OUT_RING( ctx->se_tcl_texture_proc_ctl );
OUT_RING( ctx->se_tcl_light_model_ctl );
- for (i = 0; i < 4; i++)
+ for ( i = 0 ; i < 4 ; i++ ) {
OUT_RING( ctx->se_tcl_per_light_ctl[i] );
+ }
ADVANCE_RING();
}
@@ -300,9 +297,10 @@ static inline void radeon_emit_misc( drm_radeon_private_t *dev_priv )
static inline void radeon_emit_tex0( drm_radeon_private_t *dev_priv )
{
drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
+ drm_radeon_context_regs_t *ctx = &sarea_priv->context_state;
drm_radeon_texture_regs_t *tex = &sarea_priv->tex_state[0];
RING_LOCALS;
- DRM_DEBUG( " %s\n", __FUNCTION__ );
+ DRM_DEBUG( " %s: offset=0x%x\n", __FUNCTION__, tex->pp_txoffset );
BEGIN_RING( 9 );
@@ -312,7 +310,7 @@ static inline void radeon_emit_tex0( drm_radeon_private_t *dev_priv )
OUT_RING( tex->pp_txoffset );
OUT_RING( tex->pp_txcblend );
OUT_RING( tex->pp_txablend );
- OUT_RING( tex->pp_tfactor );
+ OUT_RING( ctx->pp_tfactor );
OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_0, 0 ) );
OUT_RING( tex->pp_border_color );
@@ -323,9 +321,10 @@ static inline void radeon_emit_tex0( drm_radeon_private_t *dev_priv )
static inline void radeon_emit_tex1( drm_radeon_private_t *dev_priv )
{
drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
+ drm_radeon_context_regs_t *ctx = &sarea_priv->context_state;
drm_radeon_texture_regs_t *tex = &sarea_priv->tex_state[1];
RING_LOCALS;
- DRM_DEBUG( " %s\n", __FUNCTION__ );
+ DRM_DEBUG( " %s: offset=0x%x\n", __FUNCTION__, tex->pp_txoffset );
BEGIN_RING( 9 );
@@ -335,7 +334,7 @@ static inline void radeon_emit_tex1( drm_radeon_private_t *dev_priv )
OUT_RING( tex->pp_txoffset );
OUT_RING( tex->pp_txcblend );
OUT_RING( tex->pp_txablend );
- OUT_RING( tex->pp_tfactor );
+ OUT_RING( ctx->pp_tfactor );
OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_1, 0 ) );
OUT_RING( tex->pp_border_color );
@@ -346,6 +345,7 @@ static inline void radeon_emit_tex1( drm_radeon_private_t *dev_priv )
static inline void radeon_emit_tex2( drm_radeon_private_t *dev_priv )
{
drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
+ drm_radeon_context_regs_t *ctx = &sarea_priv->context_state;
drm_radeon_texture_regs_t *tex = &sarea_priv->tex_state[2];
RING_LOCALS;
DRM_DEBUG( " %s\n", __FUNCTION__ );
@@ -358,7 +358,7 @@ static inline void radeon_emit_tex2( drm_radeon_private_t *dev_priv )
OUT_RING( tex->pp_txoffset );
OUT_RING( tex->pp_txcblend );
OUT_RING( tex->pp_txablend );
- OUT_RING( tex->pp_tfactor );
+ OUT_RING( ctx->pp_tfactor );
OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_2, 0 ) );
OUT_RING( tex->pp_border_color );
@@ -431,8 +431,10 @@ static inline void radeon_emit_state( drm_radeon_private_t *dev_priv )
}
if ( dirty & RADEON_UPLOAD_TEX2 ) {
- radeon_emit_tex1( dev_priv );
- sarea_priv->dirty &= ~RADEON_UPLOAD_TEX1;
+#if 0
+ radeon_emit_tex2( dev_priv );
+#endif
+ sarea_priv->dirty &= ~RADEON_UPLOAD_TEX2;
}
#if 0
@@ -480,12 +482,12 @@ static void radeon_clear_box( drm_radeon_private_t *dev_priv,
BEGIN_RING( 6 );
OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
- OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL
- | RADEON_GMC_BRUSH_SOLID_COLOR
- | fb_bpp
- | RADEON_GMC_SRC_DATATYPE_COLOR
- | RADEON_ROP3_P
- | RADEON_GMC_CLR_CMP_CNTL_DIS );
+ OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
+ RADEON_GMC_BRUSH_SOLID_COLOR |
+ fb_bpp |
+ RADEON_GMC_SRC_DATATYPE_COLOR |
+ RADEON_ROP3_P |
+ RADEON_GMC_CLR_CMP_CNTL_DIS );
OUT_RING( (pitch << 22) | (offset >> 5) );
OUT_RING( color );
@@ -537,9 +539,7 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
unsigned int flags,
int cx, int cy, int cw, int ch,
unsigned int clear_color,
- unsigned int clear_depth,
- unsigned int color_mask,
- unsigned int depth_mask )
+ unsigned int clear_depth )
{
drm_radeon_private_t *dev_priv = dev->dev_private;
drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -572,6 +572,21 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
return;
}
+ if ( dev_priv->page_flipping && dev_priv->current_page == 1) {
+ unsigned int tmp = flags;
+
+ flags &= ~(RADEON_FRONT | RADEON_BACK);
+ if ( tmp & RADEON_FRONT )
+ flags |= RADEON_BACK;
+ if ( tmp & RADEON_BACK )
+ flags |= RADEON_FRONT;
+ }
+
+ RADEON_WAIT_UNTIL_IDLE();
+#if 0
+ RADEON_FLUSH_CACHE();
+#endif
+
for ( i = 0 ; i < nbox ; i++ ) {
int x = pbox[i].x1;
int y = pbox[i].y1;
@@ -586,55 +601,72 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
BEGIN_RING( 2 );
OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) );
- OUT_RING( color_mask );
+ OUT_RING( sarea_priv->context_state.rb3d_planemask );
ADVANCE_RING();
}
-#if USE_OLD_BLITS
if ( flags & RADEON_FRONT ) {
- int fx = x + dev_priv->front_x;
- int fy = y + dev_priv->front_y;
-
- DRM_DEBUG( "clear front: x=%d y=%d\n",
- dev_priv->front_x, dev_priv->front_y );
- BEGIN_RING( 5 );
+ BEGIN_RING( 6 );
- OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 3 ) );
- OUT_RING( RADEON_GMC_BRUSH_SOLID_COLOR
- | fb_bpp
- | RADEON_GMC_SRC_DATATYPE_COLOR
- | RADEON_ROP3_P
- | RADEON_GMC_CLR_CMP_CNTL_DIS );
+ OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
+ OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
+ RADEON_GMC_BRUSH_SOLID_COLOR |
+ fb_bpp |
+ RADEON_GMC_SRC_DATATYPE_COLOR |
+ RADEON_ROP3_P |
+ RADEON_GMC_CLR_CMP_CNTL_DIS );
+
+ OUT_RING( dev_priv->front_pitch_offset );
OUT_RING( clear_color );
- OUT_RING( (fx << 16) | fy );
+
+ OUT_RING( (x << 16) | y );
OUT_RING( (w << 16) | h );
ADVANCE_RING();
}
if ( flags & RADEON_BACK ) {
- int bx = x + dev_priv->back_x;
- int by = y + dev_priv->back_y;
-
- DRM_DEBUG( "clear back: x=%d y=%d\n",
- dev_priv->back_x, dev_priv->back_y );
- BEGIN_RING( 5 );
+ BEGIN_RING( 6 );
- OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 3 ) );
- OUT_RING( RADEON_GMC_BRUSH_SOLID_COLOR
- | fb_bpp
- | RADEON_GMC_SRC_DATATYPE_COLOR
- | RADEON_ROP3_P
- | RADEON_GMC_CLR_CMP_CNTL_DIS );
+ OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
+ OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
+ RADEON_GMC_BRUSH_SOLID_COLOR |
+ fb_bpp |
+ RADEON_GMC_SRC_DATATYPE_COLOR |
+ RADEON_ROP3_P |
+ RADEON_GMC_CLR_CMP_CNTL_DIS );
+
+ OUT_RING( dev_priv->back_pitch_offset );
OUT_RING( clear_color );
- OUT_RING( (bx << 16) | by );
+
+ OUT_RING( (x << 16) | y );
OUT_RING( (w << 16) | h );
ADVANCE_RING();
}
if ( flags & RADEON_DEPTH ) {
+#if 0
+ BEGIN_RING( 6 );
+
+ OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
+ OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
+ RADEON_GMC_BRUSH_SOLID_COLOR |
+ depth_bpp |
+ RADEON_GMC_SRC_DATATYPE_COLOR |
+ RADEON_ROP3_P |
+ RADEON_GMC_CLR_CMP_CNTL_DIS |
+ RADEON_GMC_WR_MSK_DIS );
+
+ OUT_RING( dev_priv->depth_pitch_offset );
+ OUT_RING( clear_depth );
+
+ OUT_RING( (x << 16) | y );
+ OUT_RING( (w << 16) | h );
+
+ ADVANCE_RING();
+#else
int dx = x;
int dy = y;
drm_radeon_context_regs_t *ctx =
@@ -643,22 +675,19 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
u32 rb3d_zstencilcntl = ctx->rb3d_zstencilcntl;
u32 se_cntl = ctx->se_cntl;
- DRM_DEBUG( "clear depth: x=%d y=%d\n",
- dev_priv->depth_x, dev_priv->depth_y );
-
- rb3d_cntl |= ( RADEON_PLANE_MASK_ENABLE
- | RADEON_Z_ENABLE );
+ rb3d_cntl |= ( RADEON_PLANE_MASK_ENABLE |
+ RADEON_Z_ENABLE );
rb3d_zstencilcntl &= ~RADEON_Z_TEST_MASK;
- rb3d_zstencilcntl |= ( RADEON_Z_TEST_ALWAYS
- | RADEON_Z_WRITE_ENABLE );
+ rb3d_zstencilcntl |= ( RADEON_Z_TEST_ALWAYS |
+ RADEON_Z_WRITE_ENABLE );
- se_cntl &= ~( RADEON_VPORT_XY_XFORM_ENABLE
- | RADEON_VPORT_Z_XFORM_ENABLE
- | RADEON_FFACE_CULL_MASK
- | RADEON_BFACE_CULL_MASK );
- se_cntl |= ( RADEON_FFACE_SOLID
- | RADEON_BFACE_SOLID );
+ se_cntl &= ~( RADEON_VPORT_XY_XFORM_ENABLE |
+ RADEON_VPORT_Z_XFORM_ENABLE |
+ RADEON_FFACE_CULL_MASK |
+ RADEON_BFACE_CULL_MASK );
+ se_cntl |= ( RADEON_FFACE_SOLID |
+ RADEON_BFACE_SOLID );
BEGIN_RING( 28 );
@@ -676,19 +705,32 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
/* Draw rectangle */
OUT_RING( CP_PACKET3( RADEON_3D_DRAW_IMMD, 10 ) );
- OUT_RING( RADEON_CP_VC_FRMT_XY
- | RADEON_CP_VC_FRMT_Z);
- OUT_RING( RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE
- | RADEON_CP_VC_CNTL_MAOS_ENABLE
- | RADEON_CP_VC_CNTL_PRIM_WALK_RING
- | RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST
- | ( 3 << RADEON_CP_VC_CNTL_NUM_SHIFT ) );
+ OUT_RING( RADEON_CP_VC_FRMT_XY |
+ RADEON_CP_VC_FRMT_Z );
+ OUT_RING( RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE |
+ RADEON_CP_VC_CNTL_MAOS_ENABLE |
+ RADEON_CP_VC_CNTL_PRIM_WALK_RING |
+ RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST |
+ ( 3 << RADEON_CP_VC_CNTL_NUM_SHIFT ) );
{
union {
float f;
u32 u;
} val;
+
+
+ /*
+ * *************************************************************
+ *
+ * FIXME: GET RID OF THIS!!! WE MUST NOT USE THE FPU IN THE
+ * KERNEL, EVER!!!
+ *
+ * *************************************************************
+ */
+
+
+
val.f = dx; OUT_RING( val.u );
val.f = dy; OUT_RING( val.u );
val.f = clear_depth; OUT_RING( val.u );
@@ -715,75 +757,11 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
OUT_RING( ctx->se_cntl );
ADVANCE_RING();
- }
-#else
- if ( flags & RADEON_FRONT ) {
- BEGIN_RING( 6 );
-
- OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
- OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL
- | RADEON_GMC_BRUSH_SOLID_COLOR
- | fb_bpp
- | RADEON_GMC_SRC_DATATYPE_COLOR
- | RADEON_ROP3_P
- | RADEON_GMC_CLR_CMP_CNTL_DIS );
-
- OUT_RING( ((dev_priv->front_pitch/8) << 21) |
- (dev_priv->front_offset >> 5) );
- OUT_RING( clear_color );
-
- OUT_RING( (x << 16) | y );
- OUT_RING( (w << 16) | h );
-
- ADVANCE_RING();
- }
-
- if ( flags & RADEON_BACK ) {
- BEGIN_RING( 6 );
-
- OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
- OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL
- | RADEON_GMC_BRUSH_SOLID_COLOR
- | fb_bpp
- | RADEON_GMC_SRC_DATATYPE_COLOR
- | RADEON_ROP3_P
- | RADEON_GMC_CLR_CMP_CNTL_DIS );
-
- OUT_RING( ((dev_priv->back_pitch/8) << 21) |
- (dev_priv->back_offset >> 5) );
- OUT_RING( clear_color );
-
- OUT_RING( (x << 16) | y );
- OUT_RING( (w << 16) | h );
-
- ADVANCE_RING();
- }
-
- if ( flags & RADEON_DEPTH ) {
- BEGIN_RING( 8 );
-
- OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) );
- OUT_RING( depth_mask );
-
- OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
- OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL
- | RADEON_GMC_BRUSH_SOLID_COLOR
- | depth_bpp
- | RADEON_GMC_SRC_DATATYPE_COLOR
- | RADEON_ROP3_P
- | RADEON_GMC_CLR_CMP_CNTL_DIS );
-
- OUT_RING( ((dev_priv->depth_pitch/8) << 21) |
- (dev_priv->depth_offset >> 5) );
- OUT_RING( clear_depth );
-
- OUT_RING( (x << 16) | y );
- OUT_RING( (w << 16) | h );
-
- ADVANCE_RING();
- }
#endif
+ }
}
+
+ RADEON_WAIT_UNTIL_IDLE();
}
static void radeon_cp_dispatch_swap( drm_device_t *dev )
@@ -818,61 +796,93 @@ static void radeon_cp_dispatch_swap( drm_device_t *dev )
break;
}
+ RADEON_WAIT_UNTIL_IDLE();
+
for ( i = 0 ; i < nbox ; i++ ) {
- int fx = pbox[i].x1;
- int fy = pbox[i].y1;
- int fw = pbox[i].x2 - fx;
- int fh = pbox[i].y2 - fy;
-#if USE_OLD_BLITS
- int bx = fx + dev_priv->back_x;
- int by = fy + dev_priv->back_y;
-
- fx += dev_priv->front_x;
- fy += dev_priv->front_x;
-
- BEGIN_RING( 5 );
-
- OUT_RING( CP_PACKET3( RADEON_CNTL_BITBLT_MULTI, 3 ) );
- OUT_RING( RADEON_GMC_BRUSH_NONE
- | RADEON_GMC_SRC_DATATYPE_COLOR
- | RADEON_DP_SRC_SOURCE_MEMORY
- | fb_bpp
- | RADEON_ROP3_S
- | RADEON_GMC_CLR_CMP_CNTL_DIS
- | RADEON_GMC_WR_MSK_DIS );
-
- OUT_RING( (bx << 16) | by );
- OUT_RING( (fx << 16) | fy );
- OUT_RING( (fw << 16) | fh );
+ int x = pbox[i].x1;
+ int y = pbox[i].y1;
+ int w = pbox[i].x2 - x;
+ int h = pbox[i].y2 - y;
- ADVANCE_RING();
-#else
BEGIN_RING( 7 );
OUT_RING( CP_PACKET3( RADEON_CNTL_BITBLT_MULTI, 5 ) );
- OUT_RING( RADEON_GMC_SRC_PITCH_OFFSET_CNTL
- | RADEON_GMC_DST_PITCH_OFFSET_CNTL
- | RADEON_GMC_BRUSH_NONE
- | RADEON_GMC_SRC_DATATYPE_COLOR
- | RADEON_DP_SRC_SOURCE_MEMORY
- | fb_bpp
- | RADEON_ROP3_S
- | RADEON_GMC_CLR_CMP_CNTL_DIS
- | RADEON_GMC_WR_MSK_DIS );
-
- OUT_RING( ((dev_priv->back_pitch/8) << 21) |
- (dev_priv->back_offset >> 5) );
- OUT_RING( ((dev_priv->front_pitch/8) << 21) |
- (dev_priv->front_offset >> 5) );
-
- OUT_RING( (fx << 16) | fy );
- OUT_RING( (fx << 16) | fy );
- OUT_RING( (fw << 16) | fh );
+ OUT_RING( RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
+ RADEON_GMC_DST_PITCH_OFFSET_CNTL |
+ RADEON_GMC_BRUSH_NONE |
+ fb_bpp |
+ RADEON_GMC_SRC_DATATYPE_COLOR |
+ RADEON_ROP3_S |
+ RADEON_DP_SRC_SOURCE_MEMORY |
+ RADEON_GMC_CLR_CMP_CNTL_DIS |
+ RADEON_GMC_WR_MSK_DIS );
+
+#if 0
+ OUT_RING( dev_priv->back_pitch_offset );
+ OUT_RING( dev_priv->front_pitch_offset );
+
+ OUT_RING( (x << 16) | y );
+ OUT_RING( (x << 16) | y );
+ OUT_RING( (w << 16) | h );
+#else
+ OUT_RING( dev_priv->depth_pitch_offset );
+ OUT_RING( dev_priv->front_pitch_offset );
+
+ OUT_RING( (0 << 16) | 0 );
+ OUT_RING( (0 << 16) | 0 );
+ OUT_RING( (832 << 16) | 600 );
+#endif
ADVANCE_RING();
+ }
+
+ /* Increment the frame counter. The client-side 3D driver must
+ * throttle the framerate by waiting for this value before
+ * performing the swapbuffer ioctl.
+ */
+ dev_priv->sarea_priv->last_frame++;
+
+ BEGIN_RING( 2 );
+
+ OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) );
+ OUT_RING( dev_priv->sarea_priv->last_frame );
+
+ ADVANCE_RING();
+
+ RADEON_WAIT_UNTIL_IDLE();
+}
+
+static void radeon_cp_dispatch_flip( drm_device_t *dev )
+{
+ drm_radeon_private_t *dev_priv = dev->dev_private;
+ RING_LOCALS;
+ DRM_DEBUG( "%s: page=%d\n", __FUNCTION__, dev_priv->current_page );
+
+ radeon_update_ring_snapshot( dev_priv );
+
+#if RADEON_PERFORMANCE_BOXES
+ /* Do some trivial performance monitoring...
+ */
+ radeon_cp_performance_boxes( dev_priv );
#endif
+
+ RADEON_WAIT_UNTIL_IDLE();
+ RADEON_WAIT_UNTIL_PAGE_FLIPPED();
+
+ BEGIN_RING( 2 );
+
+ OUT_RING( CP_PACKET0( RADEON_CRTC_OFFSET, 0 ) );
+
+ if ( dev_priv->current_page == 0 ) {
+ OUT_RING( dev_priv->back_offset );
+ dev_priv->current_page = 1;
+ } else {
+ OUT_RING( dev_priv->front_offset );
+ dev_priv->current_page = 0;
}
+ ADVANCE_RING();
+
/* Increment the frame counter. The client-side 3D driver must
* throttle the framerate by waiting for this value before
* performing the swapbuffer ioctl.
@@ -893,22 +903,14 @@ static void radeon_cp_dispatch_vertex( drm_device_t *dev,
drm_radeon_private_t *dev_priv = dev->dev_private;
drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
- int vertsize = sarea_priv->vertsize;
int format = sarea_priv->vc_format;
- int index = buf->idx;
- int offset = dev_priv->buffers->offset + buf->offset - dev->agp->base;
+ int offset = dev_priv->agp_buffers_offset + buf->offset;
int size = buf->used;
int prim = buf_priv->prim;
int i = 0;
RING_LOCALS;
DRM_DEBUG( "%s\n", __FUNCTION__ );
- DRM_DEBUG( "vertex buffer index = %d\n", index );
- DRM_DEBUG( "vertex buffer offset = 0x%x\n", offset );
- DRM_DEBUG( "vertex buffer size = %d vertices\n", size );
- DRM_DEBUG( "vertex size = %d\n", vertsize );
- DRM_DEBUG( "vertex format = 0x%x\n", format );
-
radeon_update_ring_snapshot( dev_priv );
if ( 0 )
@@ -925,19 +927,20 @@ static void radeon_cp_dispatch_vertex( drm_device_t *dev,
/* Emit the next set of up to three cliprects */
if ( i < sarea_priv->nbox ) {
radeon_emit_clip_rects( dev_priv,
- &sarea_priv->boxes[i],
- sarea_priv->nbox - i );
+ &sarea_priv->boxes[i],
+ sarea_priv->nbox - i );
}
/* Emit the vertex buffer rendering commands */
BEGIN_RING( 5 );
- OUT_RING( CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM,
- 3 ) );
- OUT_RING( offset + dev_priv->agp_vm_start );
+ OUT_RING( CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, 3 ) );
+ OUT_RING( offset );
OUT_RING( size );
OUT_RING( format );
OUT_RING( prim | RADEON_CP_VC_CNTL_PRIM_WALK_LIST |
+ RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA |
+ RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE |
(size << RADEON_CP_VC_CNTL_NUM_SHIFT) );
ADVANCE_RING();
@@ -958,7 +961,7 @@ static void radeon_cp_dispatch_vertex( drm_device_t *dev,
ADVANCE_RING();
buf->pending = 1;
-
+ buf->used = 0;
/* FIXME: Check dispatched field */
buf_priv->dispatched = 0;
}
@@ -979,8 +982,6 @@ static void radeon_cp_dispatch_vertex( drm_device_t *dev,
}
-
-
static void radeon_cp_dispatch_indirect( drm_device_t *dev,
drm_buf_t *buf,
int start, int end )
@@ -994,7 +995,7 @@ static void radeon_cp_dispatch_indirect( drm_device_t *dev,
radeon_update_ring_snapshot( dev_priv );
if ( start != end ) {
- int offset = (dev_priv->buffers->offset - dev->agp->base
+ int offset = (dev_priv->agp_buffers_offset
+ buf->offset + start);
int dwords = (end - start + 3) / sizeof(u32);
@@ -1009,21 +1010,6 @@ static void radeon_cp_dispatch_indirect( drm_device_t *dev,
data[dwords++] = RADEON_CP_PACKET2;
}
- DRM_DEBUG( "indirect: offset=0x%x dwords=%d\n",
- offset, dwords );
-
- if ( 0 ) {
- u32 *data = (u32 *)
- ((char *)dev_priv->buffers->handle
- + buf->offset + start);
- int i;
- DRM_INFO( "data = %p\n", data );
- for ( i = 0 ; i < dwords ; i++ ) {
- DRM_INFO( "data[0x%x] = 0x%08x\n",
- i, data[i] );
- }
- }
-
buf_priv->dispatched = 1;
/* Fire off the indirect buffer */
@@ -1048,6 +1034,7 @@ static void radeon_cp_dispatch_indirect( drm_device_t *dev,
ADVANCE_RING();
buf->pending = 1;
+ buf->used = 0;
/* FIXME: Check dispatched field */
buf_priv->dispatched = 0;
}
@@ -1066,21 +1053,20 @@ static void radeon_cp_dispatch_indirect( drm_device_t *dev,
static void radeon_cp_dispatch_indices( drm_device_t *dev,
drm_buf_t *buf,
- int start, int end )
+ int start, int end,
+ int count )
{
drm_radeon_private_t *dev_priv = dev->dev_private;
drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
int format = sarea_priv->vc_format;
- int offset = dev_priv->buffers->offset - dev->agp->base;
+ int offset = dev_priv->agp_buffers_offset;
int prim = buf_priv->prim;
-
u32 *data;
-
int dwords;
int i = 0;
RING_LOCALS;
- DRM_DEBUG( "%s: start=%d end=%d\n", __FUNCTION__, start, end );
+ DRM_DEBUG( "indices: s=%d e=%d c=%d\n", start, end, count );
radeon_update_ring_snapshot( dev_priv );
@@ -1094,9 +1080,6 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev,
radeon_emit_state( dev_priv );
}
- /* Adjust start offset to include packet header
- */
- start -= RADEON_INDEX_PRIM_OFFSET;
dwords = (end - start + 3) / sizeof(u32);
data = (u32 *)((char *)dev_priv->buffers->handle
@@ -1104,31 +1087,24 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev,
data[0] = CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, dwords-2 );
- data[1] = offset + dev_priv->agp_vm_start;
+ data[1] = offset;
data[2] = RADEON_MAX_VB_VERTS;
data[3] = format;
data[4] = (prim | RADEON_CP_VC_CNTL_PRIM_WALK_IND |
- (RADEON_MAX_VB_VERTS << 16));
+ RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA |
+ RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE |
+ (count << RADEON_CP_VC_CNTL_NUM_SHIFT) );
- if ( (end - start) & 0x3 ) {
+ if ( count & 0x1 ) {
data[dwords-1] &= 0x0000ffff;
}
- if ( 0 ) {
- int i;
- DRM_INFO( "data = %p\n", data );
- for ( i = 0 ; i < dwords ; i++ ) {
- DRM_INFO( "data[0x%x] = 0x%08x\n",
- i, data[i] );
- }
- }
-
do {
/* Emit the next set of up to three cliprects */
if ( i < sarea_priv->nbox ) {
radeon_emit_clip_rects( dev_priv,
- &sarea_priv->boxes[i],
- sarea_priv->nbox - i );
+ &sarea_priv->boxes[i],
+ sarea_priv->nbox - i );
}
radeon_cp_dispatch_indirect( dev, buf, start, end );
@@ -1169,20 +1145,19 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev,
}
static int radeon_cp_dispatch_blit( drm_device_t *dev,
- int offset, int pitch, int format,
- drm_radeon_blit_rect_t *rects, int count )
+ drm_radeon_blit_t *blit )
{
-#if 0
drm_radeon_private_t *dev_priv = dev->dev_private;
drm_device_dma_t *dma = dev->dma;
drm_buf_t *buf;
drm_radeon_buf_priv_t *buf_priv;
- drm_radeon_blit_rect_t *rect;
+ u32 format;
u32 *data;
int dword_shift, dwords;
- int i;
RING_LOCALS;
- DRM_DEBUG( "%s\n", __FUNCTION__ );
+ DRM_DEBUG( "blit: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n",
+ blit->offset >> 10, blit->pitch, blit->format,
+ blit->x, blit->y, blit->width, blit->height );
radeon_update_ring_snapshot( dev_priv );
@@ -1190,90 +1165,85 @@ static int radeon_cp_dispatch_blit( drm_device_t *dev,
* even if the only legal values are powers of two. Thus, we'll
* use a shift instead.
*/
- switch ( format ) {
- case RADEON_DATATYPE_ARGB1555:
- case RADEON_DATATYPE_RGB565:
- case RADEON_DATATYPE_ARGB4444:
+ switch ( blit->format ) {
+ case RADEON_TXF_32BPP_ARGB8888:
+ case RADEON_TXF_32BPP_RGBA8888:
+ format = RADEON_COLOR_FORMAT_ARGB8888;
+ dword_shift = 0;
+ break;
+ case RADEON_TXF_16BPP_AI88:
+ case RADEON_TXF_16BPP_ARGB1555:
+ case RADEON_TXF_16BPP_RGB565:
+ case RADEON_TXF_16BPP_ARGB4444:
+ format = RADEON_COLOR_FORMAT_RGB565;
dword_shift = 1;
break;
- case RADEON_DATATYPE_ARGB8888:
- dword_shift = 0;
+ case RADEON_TXF_8BPP_I:
+ case RADEON_TXF_8BPP_RGB332:
+ format = RADEON_COLOR_FORMAT_CI8;
+ dword_shift = 2;
break;
default:
- DRM_ERROR( "invalid blit format %d\n", format );
+ DRM_ERROR( "invalid blit format %d\n", blit->format );
return -EINVAL;
}
- /* Flush the pixel cache, and mark the contents as Read Invalid.
- * This ensures no pixel data gets mixed up with the texture
- * data from the host data blit, otherwise part of the texture
- * image may be corrupted.
+ /* Flush the pixel cache. This ensures no pixel data gets mixed
+ * up with the texture data from the host data blit, otherwise
+ * part of the texture image may be corrupted.
*/
- BEGIN_RING( 2 );
+ RADEON_WAIT_UNTIL_IDLE();
+ RADEON_FLUSH_CACHE();
- OUT_RING( CP_PACKET0( RADEON_PC_GUI_CTLSTAT, 0 ) );
- OUT_RING( RADEON_PC_RI_GUI | RADEON_PC_FLUSH_GUI );
+ /* Dispatch the indirect buffer.
+ */
+ buf = dma->buflist[blit->idx];
+ buf_priv = buf->dev_private;
- ADVANCE_RING();
+ if ( buf->pid != current->pid ) {
+ DRM_ERROR( "process %d using buffer owned by %d\n",
+ current->pid, buf->pid );
+ return -EINVAL;
+ }
+ if ( buf->pending ) {
+ DRM_ERROR( "sending pending buffer %d\n", blit->idx );
+ return -EINVAL;
+ }
- /* Dispatch each of the indirect buffers.
- */
- for ( i = 0 ; i < count ; i++ ) {
- rect = &rects[i];
- buf = dma->buflist[rect->index];
- buf_priv = buf->dev_private;
-
- if ( buf->pid != current->pid ) {
- DRM_ERROR( "process %d using buffer owned by %d\n",
- current->pid, buf->pid );
- return -EINVAL;
- }
- if ( buf->pending ) {
- DRM_ERROR( "sending pending buffer %d\n",
- rect->index );
- return -EINVAL;
- }
+ buf_priv->discard = 1;
- buf_priv->discard = 1;
+ dwords = (blit->width * blit->height) >> dword_shift;
+ if ( !dwords ) dwords = 1;
- dwords = (rect->width * rect->height) >> dword_shift;
+ data = (u32 *)((char *)dev_priv->buffers->handle + buf->offset);
- data = (u32 *)((char *)dev_priv->buffers->handle
- + buf->offset);
-
- data[0] = CP_PACKET3( RADEON_CNTL_HOSTDATA_BLT, dwords + 6 );
- data[1] = ( RADEON_GMC_DST_PITCH_OFFSET_CNTL
- | RADEON_GMC_BRUSH_NONE
- | (format << 8)
- | RADEON_GMC_SRC_DATATYPE_COLOR
- | RADEON_ROP3_S
- | RADEON_DP_SRC_SOURCE_HOST_DATA
- | RADEON_GMC_CLR_CMP_CNTL_DIS
- | RADEON_GMC_WR_MSK_DIS );
-
- data[2] = (pitch << 21) | (offset >> 5);
- data[3] = 0xffffffff;
- data[4] = 0xffffffff;
- data[5] = (rect->y << 16) | rect->x;
- data[6] = (rect->height << 16) | rect->width;
- data[7] = dwords;
-
- buf->used = (dwords + 8) * sizeof(u32);
-
- radeon_cp_dispatch_indirect( dev, buf, 0, buf->used );
- }
+ data[0] = CP_PACKET3( RADEON_CNTL_HOSTDATA_BLT, dwords + 6 );
+ data[1] = (RADEON_GMC_DST_PITCH_OFFSET_CNTL |
+ RADEON_GMC_BRUSH_NONE |
+ (format << 8) |
+ RADEON_GMC_SRC_DATATYPE_COLOR |
+ RADEON_ROP3_S |
+ RADEON_DP_SRC_SOURCE_HOST_DATA |
+ RADEON_GMC_CLR_CMP_CNTL_DIS |
+ RADEON_GMC_WR_MSK_DIS);
+
+ data[2] = (blit->pitch << 22) | (blit->offset >> 10);
+ data[3] = 0xffffffff;
+ data[4] = 0xffffffff;
+ data[5] = (blit->y << 16) | blit->x;
+ data[6] = (blit->height << 16) | blit->width;
+ data[7] = dwords;
+
+ buf->used = (dwords + 8) * sizeof(u32);
+
+ radeon_cp_dispatch_indirect( dev, buf, 0, buf->used );
/* Flush the pixel cache after the blit completes. This ensures
* the texture data is written out to memory before rendering
* continues.
*/
- BEGIN_RING( 2 );
-
- OUT_RING( CP_PACKET0( RADEON_PC_GUI_CTLSTAT, 0 ) );
- OUT_RING( RADEON_PC_FLUSH_GUI );
-
- ADVANCE_RING();
-#endif
+ RADEON_WAIT_UNTIL_IDLE();
+ RADEON_FLUSH_CACHE();
return 0;
}
@@ -1295,7 +1265,7 @@ int radeon_cp_clear( struct inode *inode, struct file *filp,
if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
dev->lock.pid != current->pid ) {
- DRM_ERROR( "radeon_cp_clear called without lock held\n" );
+ DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
return -EINVAL;
}
@@ -1307,14 +1277,13 @@ int radeon_cp_clear( struct inode *inode, struct file *filp,
sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
radeon_cp_dispatch_clear( dev, clear.flags,
- clear.x, clear.y, clear.w, clear.h,
- clear.clear_color, clear.clear_depth,
- clear.color_mask, clear.depth_mask );
+ clear.x, clear.y, clear.w, clear.h,
+ clear.clear_color, clear.clear_depth );
/* Make sure we restore the 3D state next time.
*/
- dev_priv->sarea_priv->dirty |= ( RADEON_UPLOAD_CONTEXT
- | RADEON_UPLOAD_MASKS );
+ dev_priv->sarea_priv->dirty |= (RADEON_UPLOAD_CONTEXT |
+ RADEON_UPLOAD_MASKS);
return 0;
}
@@ -1330,19 +1299,20 @@ int radeon_cp_swap( struct inode *inode, struct file *filp,
if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
dev->lock.pid != current->pid ) {
- DRM_ERROR( "radeon_cp_swap called without lock held\n" );
+ DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
return -EINVAL;
}
if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS )
sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
- radeon_cp_dispatch_swap( dev );
-
- /* Make sure we restore the 3D state next time.
- */
- dev_priv->sarea_priv->dirty |= ( RADEON_UPLOAD_CONTEXT
- | RADEON_UPLOAD_MASKS );
+ if ( !dev_priv->page_flipping ) {
+ radeon_cp_dispatch_swap( dev );
+ dev_priv->sarea_priv->dirty |= (RADEON_UPLOAD_CONTEXT |
+ RADEON_UPLOAD_MASKS);
+ } else {
+ radeon_cp_dispatch_flip( dev );
+ }
return 0;
}
@@ -1419,6 +1389,7 @@ int radeon_cp_indices( struct inode *inode, struct file *filp,
drm_buf_t *buf;
drm_radeon_buf_priv_t *buf_priv;
drm_radeon_indices_t elts;
+ int count;
if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
dev->lock.pid != current->pid ) {
@@ -1461,16 +1432,24 @@ int radeon_cp_indices( struct inode *inode, struct file *filp,
DRM_ERROR( "sending pending buffer %d\n", elts.idx );
return -EINVAL;
}
- if ( (buf->offset + elts.start) & 0x3 ) {
- DRM_ERROR( "buffer start 0x%x\n",
- (u32)(buf->offset + elts.start) );
+
+ count = (elts.end - elts.start) / sizeof(u16);
+ elts.start -= RADEON_INDEX_PRIM_OFFSET;
+
+ if ( elts.start & 0x7 ) {
+ DRM_ERROR( "misaligned buffer 0x%x\n", elts.start );
+ return -EINVAL;
+ }
+ if ( elts.start < buf->used ) {
+ DRM_ERROR( "no header 0x%x - 0x%x\n", elts.start, buf->used );
return -EINVAL;
}
+ buf->used = elts.end;
buf_priv->prim = elts.prim;
buf_priv->discard = elts.discard;
- radeon_cp_dispatch_indices( dev, buf, elts.start, elts.end );
+ radeon_cp_dispatch_indices( dev, buf, elts.start, elts.end, count );
return 0;
}
@@ -1493,19 +1472,30 @@ int radeon_cp_blit( struct inode *inode, struct file *filp,
sizeof(blit) ) )
return -EFAULT;
- DRM_DEBUG( "%s: pid=%d count=%d\n",
- __FUNCTION__, current->pid, blit.count );
+ DRM_DEBUG( "%s: pid=%d index=%d\n",
+ __FUNCTION__, current->pid, blit.idx );
- if ( blit.count < 0 || blit.count > dma->buf_count ) {
+ if ( blit.idx < 0 || blit.idx > dma->buf_count ) {
DRM_ERROR( "sending %d buffers (of %d max)\n",
- blit.count, dma->buf_count );
+ blit.idx, dma->buf_count );
return -EINVAL;
}
- if ( copy_from_user( &rects, blit.rects,
- blit.count * sizeof(drm_radeon_blit_rect_t) ) )
- return -EFAULT;
+ return radeon_cp_dispatch_blit( dev, &blit );
+}
+
+int radeon_cp_stipple( struct inode *inode, struct file *filp,
+ unsigned int cmd, unsigned long arg )
+{
+ drm_file_t *priv = filp->private_data;
+ drm_device_t *dev = priv->dev;
+ DRM_DEBUG( "%s\n", __FUNCTION__ );
+
+ if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
+ dev->lock.pid != current->pid ) {
+ DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
+ return -EINVAL;
+ }
- return radeon_cp_dispatch_blit( dev, blit.offset, blit.pitch,
- blit.format, rects, blit.count );
+ return -EINVAL;
}
diff --git a/linux/sis_drm.h b/linux/sis_drm.h
index 73807f31..299143f6 100644
--- a/linux/sis_drm.h
+++ b/linux/sis_drm.h
@@ -2,30 +2,19 @@
#ifndef _sis_drm_public_h_
#define _sis_drm_public_h_
-typedef struct {
+typedef struct {
int context;
unsigned int offset;
unsigned int size;
unsigned int free;
-} drm_sis_mem_t;
+} drm_sis_mem_t;
-typedef struct {
+typedef struct {
unsigned int offset, size;
-} drm_sis_agp_t;
+} drm_sis_agp_t;
-typedef struct {
+typedef struct {
unsigned int left, right;
-} drm_sis_flip_t;
-
-#define SIS_IOCTL_FB_ALLOC DRM_IOWR( 0x44, drm_sis_mem_t)
-#define SIS_IOCTL_FB_FREE DRM_IOW( 0x45, drm_sis_mem_t)
-
-#define SIS_IOCTL_AGP_INIT DRM_IOWR( 0x53, drm_sis_agp_t)
-#define SIS_IOCTL_AGP_ALLOC DRM_IOWR( 0x54, drm_sis_mem_t)
-#define SIS_IOCTL_AGP_FREE DRM_IOW( 0x55, drm_sis_mem_t)
-
-#define SIS_IOCTL_FLIP DRM_IOW( 0x48, drm_sis_flip_t)
-#define SIS_IOCTL_FLIP_INIT DRM_IO( 0x49)
-#define SIS_IOCTL_FLIP_FINAL DRM_IO( 0x50)
+} drm_sis_flip_t;
#endif
diff --git a/shared-core/drm.h b/shared-core/drm.h
index e0496bc7..b892682a 100644
--- a/shared-core/drm.h
+++ b/shared-core/drm.h
@@ -296,111 +296,113 @@ typedef struct drm_agp_info {
unsigned short id_device;
} drm_agp_info_t;
-#define DRM_IOCTL_BASE 'd'
-#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
-#define DRM_IOR(nr,size) _IOR(DRM_IOCTL_BASE,nr,size)
-#define DRM_IOW(nr,size) _IOW(DRM_IOCTL_BASE,nr,size)
-#define DRM_IOWR(nr,size) _IOWR(DRM_IOCTL_BASE,nr,size)
-
-
-#define DRM_IOCTL_VERSION DRM_IOWR(0x00, drm_version_t)
-#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, drm_unique_t)
-#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, drm_auth_t)
-#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, drm_irq_busid_t)
-
-#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, drm_unique_t)
-#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, drm_auth_t)
-#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, drm_block_t)
-#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, drm_block_t)
-#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, drm_control_t)
-#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, drm_map_t)
-#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, drm_buf_desc_t)
-#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, drm_buf_desc_t)
-#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, drm_buf_info_t)
-#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, drm_buf_map_t)
-#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, drm_buf_free_t)
-
-#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, drm_ctx_t)
-#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, drm_ctx_t)
-#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, drm_ctx_t)
-#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, drm_ctx_t)
-#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, drm_ctx_t)
-#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, drm_ctx_t)
-#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, drm_ctx_res_t)
-#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, drm_draw_t)
-#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, drm_draw_t)
-#define DRM_IOCTL_DMA DRM_IOWR(0x29, drm_dma_t)
-#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, drm_lock_t)
-#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, drm_lock_t)
-#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, drm_lock_t)
-
-#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
-#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
-#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, drm_agp_mode_t)
-#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, drm_agp_info_t)
-#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, drm_agp_buffer_t)
-#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, drm_agp_buffer_t)
-#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, drm_agp_binding_t)
-#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, drm_agp_binding_t)
+#define DRM_IOCTL_BASE 'd'
+#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
+#define DRM_IOR(nr,size) _IOR(DRM_IOCTL_BASE,nr,size)
+#define DRM_IOW(nr,size) _IOW(DRM_IOCTL_BASE,nr,size)
+#define DRM_IOWR(nr,size) _IOWR(DRM_IOCTL_BASE,nr,size)
+
+
+#define DRM_IOCTL_VERSION DRM_IOWR(0x00, drm_version_t)
+#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, drm_unique_t)
+#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, drm_auth_t)
+#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, drm_irq_busid_t)
+
+#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, drm_unique_t)
+#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, drm_auth_t)
+#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, drm_block_t)
+#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, drm_block_t)
+#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, drm_control_t)
+#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, drm_map_t)
+#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, drm_buf_desc_t)
+#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, drm_buf_desc_t)
+#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, drm_buf_info_t)
+#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, drm_buf_map_t)
+#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, drm_buf_free_t)
+
+#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, drm_ctx_t)
+#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, drm_ctx_t)
+#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, drm_ctx_t)
+#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, drm_ctx_t)
+#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, drm_ctx_t)
+#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, drm_ctx_t)
+#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, drm_ctx_res_t)
+#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, drm_draw_t)
+#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, drm_draw_t)
+#define DRM_IOCTL_DMA DRM_IOWR(0x29, drm_dma_t)
+#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, drm_lock_t)
+#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, drm_lock_t)
+#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, drm_lock_t)
+
+#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
+#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
+#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, drm_agp_mode_t)
+#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, drm_agp_info_t)
+#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, drm_agp_buffer_t)
+#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, drm_agp_buffer_t)
+#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, drm_agp_binding_t)
+#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, drm_agp_binding_t)
/* Mga specific ioctls */
-#define DRM_IOCTL_MGA_INIT DRM_IOW( 0x40, drm_mga_init_t)
-#define DRM_IOCTL_MGA_SWAP DRM_IOW( 0x41, drm_mga_swap_t)
-#define DRM_IOCTL_MGA_CLEAR DRM_IOW( 0x42, drm_mga_clear_t)
-#define DRM_IOCTL_MGA_ILOAD DRM_IOW( 0x43, drm_mga_iload_t)
-#define DRM_IOCTL_MGA_VERTEX DRM_IOW( 0x44, drm_mga_vertex_t)
-#define DRM_IOCTL_MGA_FLUSH DRM_IOW( 0x45, drm_lock_t )
-#define DRM_IOCTL_MGA_INDICES DRM_IOW( 0x46, drm_mga_indices_t)
+#define DRM_IOCTL_MGA_INIT DRM_IOW( 0x40, drm_mga_init_t)
+#define DRM_IOCTL_MGA_SWAP DRM_IOW( 0x41, drm_mga_swap_t)
+#define DRM_IOCTL_MGA_CLEAR DRM_IOW( 0x42, drm_mga_clear_t)
+#define DRM_IOCTL_MGA_ILOAD DRM_IOW( 0x43, drm_mga_iload_t)
+#define DRM_IOCTL_MGA_VERTEX DRM_IOW( 0x44, drm_mga_vertex_t)
+#define DRM_IOCTL_MGA_FLUSH DRM_IOW( 0x45, drm_lock_t )
+#define DRM_IOCTL_MGA_INDICES DRM_IOW( 0x46, drm_mga_indices_t)
/* I810 specific ioctls */
-#define DRM_IOCTL_I810_INIT DRM_IOW( 0x40, drm_i810_init_t)
-#define DRM_IOCTL_I810_VERTEX DRM_IOW( 0x41, drm_i810_vertex_t)
-#define DRM_IOCTL_I810_CLEAR DRM_IOW( 0x42, drm_i810_clear_t)
-#define DRM_IOCTL_I810_FLUSH DRM_IO ( 0x43)
-#define DRM_IOCTL_I810_GETAGE DRM_IO ( 0x44)
-#define DRM_IOCTL_I810_GETBUF DRM_IOWR(0x45, drm_i810_dma_t)
-#define DRM_IOCTL_I810_SWAP DRM_IO ( 0x46)
-#define DRM_IOCTL_I810_COPY DRM_IOW( 0x47, drm_i810_copy_t)
-#define DRM_IOCTL_I810_DOCOPY DRM_IO ( 0x48)
+#define DRM_IOCTL_I810_INIT DRM_IOW( 0x40, drm_i810_init_t)
+#define DRM_IOCTL_I810_VERTEX DRM_IOW( 0x41, drm_i810_vertex_t)
+#define DRM_IOCTL_I810_CLEAR DRM_IOW( 0x42, drm_i810_clear_t)
+#define DRM_IOCTL_I810_FLUSH DRM_IO( 0x43)
+#define DRM_IOCTL_I810_GETAGE DRM_IO( 0x44)
+#define DRM_IOCTL_I810_GETBUF DRM_IOWR(0x45, drm_i810_dma_t)
+#define DRM_IOCTL_I810_SWAP DRM_IO( 0x46)
+#define DRM_IOCTL_I810_COPY DRM_IOW( 0x47, drm_i810_copy_t)
+#define DRM_IOCTL_I810_DOCOPY DRM_IO( 0x48)
/* Rage 128 specific ioctls */
-#define DRM_IOCTL_R128_INIT DRM_IOW( 0x40, drm_r128_init_t)
-#define DRM_IOCTL_R128_CCE_START DRM_IO( 0x41)
-#define DRM_IOCTL_R128_CCE_STOP DRM_IOW( 0x42, drm_r128_cce_stop_t)
-#define DRM_IOCTL_R128_CCE_RESET DRM_IO( 0x43)
-#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( 0x44)
-#define DRM_IOCTL_R128_RESET DRM_IO( 0x46)
-#define DRM_IOCTL_R128_SWAP DRM_IO( 0x47)
-#define DRM_IOCTL_R128_CLEAR DRM_IOW( 0x48, drm_r128_clear_t)
-#define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x49, drm_r128_vertex_t)
-#define DRM_IOCTL_R128_INDICES DRM_IOW( 0x4a, drm_r128_indices_t)
-#define DRM_IOCTL_R128_BLIT DRM_IOW( 0x4b, drm_r128_blit_t)
-#define DRM_IOCTL_R128_DEPTH DRM_IOW( 0x4c, drm_r128_depth_t)
-#define DRM_IOCTL_R128_STIPPLE DRM_IOW( 0x4d, drm_r128_stipple_t)
-#define DRM_IOCTL_R128_PACKET DRM_IOWR(0x4e, drm_r128_packet_t)
+#define DRM_IOCTL_R128_INIT DRM_IOW( 0x40, drm_r128_init_t)
+#define DRM_IOCTL_R128_CCE_START DRM_IO( 0x41)
+#define DRM_IOCTL_R128_CCE_STOP DRM_IOW( 0x42, drm_r128_cce_stop_t)
+#define DRM_IOCTL_R128_CCE_RESET DRM_IO( 0x43)
+#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( 0x44)
+#define DRM_IOCTL_R128_RESET DRM_IO( 0x46)
+#define DRM_IOCTL_R128_SWAP DRM_IO( 0x47)
+#define DRM_IOCTL_R128_CLEAR DRM_IOW( 0x48, drm_r128_clear_t)
+#define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x49, drm_r128_vertex_t)
+#define DRM_IOCTL_R128_INDICES DRM_IOW( 0x4a, drm_r128_indices_t)
+#define DRM_IOCTL_R128_BLIT DRM_IOW( 0x4b, drm_r128_blit_t)
+#define DRM_IOCTL_R128_DEPTH DRM_IOW( 0x4c, drm_r128_depth_t)
+#define DRM_IOCTL_R128_STIPPLE DRM_IOW( 0x4d, drm_r128_stipple_t)
+#define DRM_IOCTL_R128_PACKET DRM_IOWR(0x4e, drm_r128_packet_t)
/* Radeon specific ioctls */
-#define DRM_IOCTL_RADEON_RESET DRM_IO( 0x40)
-#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( 0x41, drm_radeon_init_t)
-#define DRM_IOCTL_RADEON_CP_START DRM_IO( 0x42)
-#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( 0x43, drm_radeon_cp_stop_t)
-#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( 0x44)
-#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( 0x45)
-#define DRM_IOCTL_RADEON_CP_SWAP DRM_IO( 0x46)
-#define DRM_IOCTL_RADEON_CP_CLEAR DRM_IOW( 0x47, drm_radeon_clear_t)
-#define DRM_IOCTL_RADEON_CP_VERTEX DRM_IOW( 0x48, drm_radeon_vertex_t)
-#define DRM_IOCTL_RADEON_CP_INDICES DRM_IOW( 0x49, drm_radeon_indices_t)
-#define DRM_IOCTL_RADEON_CP_BLIT DRM_IOW( 0x4a, drm_radeon_blit_t)
-#define DRM_IOCTL_RADEON_CP_PACKET DRM_IOWR(0x4b, drm_radeon_packet_t)
+#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( 0x40, drm_radeon_init_t)
+#define DRM_IOCTL_RADEON_CP_START DRM_IO( 0x41)
+#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( 0x42, drm_radeon_cp_stop_t)
+#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( 0x43)
+#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( 0x44)
+#define DRM_IOCTL_RADEON_RESET DRM_IO( 0x45)
+#define DRM_IOCTL_RADEON_PAGEFLIP DRM_IOW( 0x46, drm_radeon_pageflip_t)
+#define DRM_IOCTL_RADEON_SWAP DRM_IO( 0x47)
+#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( 0x48, drm_radeon_clear_t)
+#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( 0x49, drm_radeon_vertex_t)
+#define DRM_IOCTL_RADEON_INDICES DRM_IOW( 0x4a, drm_radeon_indices_t)
+#define DRM_IOCTL_RADEON_BLIT DRM_IOW( 0x4b, drm_radeon_blit_t)
+#define DRM_IOCTL_RADEON_STIPPLE DRM_IOWR(0x4c, drm_radeon_stipple_t)
+#define DRM_IOCTL_RADEON_PACKET DRM_IOWR(0x4d, drm_radeon_packet_t)
/* SiS specific ioctls */
-#define SIS_IOCTL_FB_ALLOC DRM_IOWR( 0x44, drm_sis_mem_t)
-#define SIS_IOCTL_FB_FREE DRM_IOW( 0x45, drm_sis_mem_t)
-#define SIS_IOCTL_AGP_INIT DRM_IOWR( 0x53, drm_sis_agp_t)
-#define SIS_IOCTL_AGP_ALLOC DRM_IOWR( 0x54, drm_sis_mem_t)
-#define SIS_IOCTL_AGP_FREE DRM_IOW( 0x55, drm_sis_mem_t)
-#define SIS_IOCTL_FLIP DRM_IOW( 0x48, drm_sis_flip_t)
-#define SIS_IOCTL_FLIP_INIT DRM_IO( 0x49)
-#define SIS_IOCTL_FLIP_FINAL DRM_IO( 0x50)
+#define SIS_IOCTL_FB_ALLOC DRM_IOWR(0x44, drm_sis_mem_t)
+#define SIS_IOCTL_FB_FREE DRM_IOW( 0x45, drm_sis_mem_t)
+#define SIS_IOCTL_AGP_INIT DRM_IOWR(0x53, drm_sis_agp_t)
+#define SIS_IOCTL_AGP_ALLOC DRM_IOWR(0x54, drm_sis_mem_t)
+#define SIS_IOCTL_AGP_FREE DRM_IOW( 0x55, drm_sis_mem_t)
+#define SIS_IOCTL_FLIP DRM_IOW( 0x48, drm_sis_flip_t)
+#define SIS_IOCTL_FLIP_INIT DRM_IO( 0x49)
+#define SIS_IOCTL_FLIP_FINAL DRM_IO( 0x50)
#endif
diff --git a/shared/drm.h b/shared/drm.h
index e0496bc7..b892682a 100644
--- a/shared/drm.h
+++ b/shared/drm.h
@@ -296,111 +296,113 @@ typedef struct drm_agp_info {
unsigned short id_device;
} drm_agp_info_t;
-#define DRM_IOCTL_BASE 'd'
-#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
-#define DRM_IOR(nr,size) _IOR(DRM_IOCTL_BASE,nr,size)
-#define DRM_IOW(nr,size) _IOW(DRM_IOCTL_BASE,nr,size)
-#define DRM_IOWR(nr,size) _IOWR(DRM_IOCTL_BASE,nr,size)
-
-
-#define DRM_IOCTL_VERSION DRM_IOWR(0x00, drm_version_t)
-#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, drm_unique_t)
-#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, drm_auth_t)
-#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, drm_irq_busid_t)
-
-#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, drm_unique_t)
-#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, drm_auth_t)
-#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, drm_block_t)
-#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, drm_block_t)
-#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, drm_control_t)
-#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, drm_map_t)
-#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, drm_buf_desc_t)
-#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, drm_buf_desc_t)
-#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, drm_buf_info_t)
-#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, drm_buf_map_t)
-#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, drm_buf_free_t)
-
-#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, drm_ctx_t)
-#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, drm_ctx_t)
-#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, drm_ctx_t)
-#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, drm_ctx_t)
-#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, drm_ctx_t)
-#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, drm_ctx_t)
-#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, drm_ctx_res_t)
-#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, drm_draw_t)
-#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, drm_draw_t)
-#define DRM_IOCTL_DMA DRM_IOWR(0x29, drm_dma_t)
-#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, drm_lock_t)
-#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, drm_lock_t)
-#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, drm_lock_t)
-
-#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
-#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
-#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, drm_agp_mode_t)
-#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, drm_agp_info_t)
-#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, drm_agp_buffer_t)
-#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, drm_agp_buffer_t)
-#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, drm_agp_binding_t)
-#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, drm_agp_binding_t)
+#define DRM_IOCTL_BASE 'd'
+#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
+#define DRM_IOR(nr,size) _IOR(DRM_IOCTL_BASE,nr,size)
+#define DRM_IOW(nr,size) _IOW(DRM_IOCTL_BASE,nr,size)
+#define DRM_IOWR(nr,size) _IOWR(DRM_IOCTL_BASE,nr,size)
+
+
+#define DRM_IOCTL_VERSION DRM_IOWR(0x00, drm_version_t)
+#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, drm_unique_t)
+#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, drm_auth_t)
+#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, drm_irq_busid_t)
+
+#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, drm_unique_t)
+#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, drm_auth_t)
+#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, drm_block_t)
+#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, drm_block_t)
+#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, drm_control_t)
+#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, drm_map_t)
+#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, drm_buf_desc_t)
+#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, drm_buf_desc_t)
+#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, drm_buf_info_t)
+#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, drm_buf_map_t)
+#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, drm_buf_free_t)
+
+#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, drm_ctx_t)
+#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, drm_ctx_t)
+#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, drm_ctx_t)
+#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, drm_ctx_t)
+#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, drm_ctx_t)
+#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, drm_ctx_t)
+#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, drm_ctx_res_t)
+#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, drm_draw_t)
+#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, drm_draw_t)
+#define DRM_IOCTL_DMA DRM_IOWR(0x29, drm_dma_t)
+#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, drm_lock_t)
+#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, drm_lock_t)
+#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, drm_lock_t)
+
+#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
+#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
+#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, drm_agp_mode_t)
+#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, drm_agp_info_t)
+#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, drm_agp_buffer_t)
+#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, drm_agp_buffer_t)
+#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, drm_agp_binding_t)
+#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, drm_agp_binding_t)
/* Mga specific ioctls */
-#define DRM_IOCTL_MGA_INIT DRM_IOW( 0x40, drm_mga_init_t)
-#define DRM_IOCTL_MGA_SWAP DRM_IOW( 0x41, drm_mga_swap_t)
-#define DRM_IOCTL_MGA_CLEAR DRM_IOW( 0x42, drm_mga_clear_t)
-#define DRM_IOCTL_MGA_ILOAD DRM_IOW( 0x43, drm_mga_iload_t)
-#define DRM_IOCTL_MGA_VERTEX DRM_IOW( 0x44, drm_mga_vertex_t)
-#define DRM_IOCTL_MGA_FLUSH DRM_IOW( 0x45, drm_lock_t )
-#define DRM_IOCTL_MGA_INDICES DRM_IOW( 0x46, drm_mga_indices_t)
+#define DRM_IOCTL_MGA_INIT DRM_IOW( 0x40, drm_mga_init_t)
+#define DRM_IOCTL_MGA_SWAP DRM_IOW( 0x41, drm_mga_swap_t)
+#define DRM_IOCTL_MGA_CLEAR DRM_IOW( 0x42, drm_mga_clear_t)
+#define DRM_IOCTL_MGA_ILOAD DRM_IOW( 0x43, drm_mga_iload_t)
+#define DRM_IOCTL_MGA_VERTEX DRM_IOW( 0x44, drm_mga_vertex_t)
+#define DRM_IOCTL_MGA_FLUSH DRM_IOW( 0x45, drm_lock_t )
+#define DRM_IOCTL_MGA_INDICES DRM_IOW( 0x46, drm_mga_indices_t)
/* I810 specific ioctls */
-#define DRM_IOCTL_I810_INIT DRM_IOW( 0x40, drm_i810_init_t)
-#define DRM_IOCTL_I810_VERTEX DRM_IOW( 0x41, drm_i810_vertex_t)
-#define DRM_IOCTL_I810_CLEAR DRM_IOW( 0x42, drm_i810_clear_t)
-#define DRM_IOCTL_I810_FLUSH DRM_IO ( 0x43)
-#define DRM_IOCTL_I810_GETAGE DRM_IO ( 0x44)
-#define DRM_IOCTL_I810_GETBUF DRM_IOWR(0x45, drm_i810_dma_t)
-#define DRM_IOCTL_I810_SWAP DRM_IO ( 0x46)
-#define DRM_IOCTL_I810_COPY DRM_IOW( 0x47, drm_i810_copy_t)
-#define DRM_IOCTL_I810_DOCOPY DRM_IO ( 0x48)
+#define DRM_IOCTL_I810_INIT DRM_IOW( 0x40, drm_i810_init_t)
+#define DRM_IOCTL_I810_VERTEX DRM_IOW( 0x41, drm_i810_vertex_t)
+#define DRM_IOCTL_I810_CLEAR DRM_IOW( 0x42, drm_i810_clear_t)
+#define DRM_IOCTL_I810_FLUSH DRM_IO( 0x43)
+#define DRM_IOCTL_I810_GETAGE DRM_IO( 0x44)
+#define DRM_IOCTL_I810_GETBUF DRM_IOWR(0x45, drm_i810_dma_t)
+#define DRM_IOCTL_I810_SWAP DRM_IO( 0x46)
+#define DRM_IOCTL_I810_COPY DRM_IOW( 0x47, drm_i810_copy_t)
+#define DRM_IOCTL_I810_DOCOPY DRM_IO( 0x48)
/* Rage 128 specific ioctls */
-#define DRM_IOCTL_R128_INIT DRM_IOW( 0x40, drm_r128_init_t)
-#define DRM_IOCTL_R128_CCE_START DRM_IO( 0x41)
-#define DRM_IOCTL_R128_CCE_STOP DRM_IOW( 0x42, drm_r128_cce_stop_t)
-#define DRM_IOCTL_R128_CCE_RESET DRM_IO( 0x43)
-#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( 0x44)
-#define DRM_IOCTL_R128_RESET DRM_IO( 0x46)
-#define DRM_IOCTL_R128_SWAP DRM_IO( 0x47)
-#define DRM_IOCTL_R128_CLEAR DRM_IOW( 0x48, drm_r128_clear_t)
-#define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x49, drm_r128_vertex_t)
-#define DRM_IOCTL_R128_INDICES DRM_IOW( 0x4a, drm_r128_indices_t)
-#define DRM_IOCTL_R128_BLIT DRM_IOW( 0x4b, drm_r128_blit_t)
-#define DRM_IOCTL_R128_DEPTH DRM_IOW( 0x4c, drm_r128_depth_t)
-#define DRM_IOCTL_R128_STIPPLE DRM_IOW( 0x4d, drm_r128_stipple_t)
-#define DRM_IOCTL_R128_PACKET DRM_IOWR(0x4e, drm_r128_packet_t)
+#define DRM_IOCTL_R128_INIT DRM_IOW( 0x40, drm_r128_init_t)
+#define DRM_IOCTL_R128_CCE_START DRM_IO( 0x41)
+#define DRM_IOCTL_R128_CCE_STOP DRM_IOW( 0x42, drm_r128_cce_stop_t)
+#define DRM_IOCTL_R128_CCE_RESET DRM_IO( 0x43)
+#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( 0x44)
+#define DRM_IOCTL_R128_RESET DRM_IO( 0x46)
+#define DRM_IOCTL_R128_SWAP DRM_IO( 0x47)
+#define DRM_IOCTL_R128_CLEAR DRM_IOW( 0x48, drm_r128_clear_t)
+#define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x49, drm_r128_vertex_t)
+#define DRM_IOCTL_R128_INDICES DRM_IOW( 0x4a, drm_r128_indices_t)
+#define DRM_IOCTL_R128_BLIT DRM_IOW( 0x4b, drm_r128_blit_t)
+#define DRM_IOCTL_R128_DEPTH DRM_IOW( 0x4c, drm_r128_depth_t)
+#define DRM_IOCTL_R128_STIPPLE DRM_IOW( 0x4d, drm_r128_stipple_t)
+#define DRM_IOCTL_R128_PACKET DRM_IOWR(0x4e, drm_r128_packet_t)
/* Radeon specific ioctls */
-#define DRM_IOCTL_RADEON_RESET DRM_IO( 0x40)
-#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( 0x41, drm_radeon_init_t)
-#define DRM_IOCTL_RADEON_CP_START DRM_IO( 0x42)
-#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( 0x43, drm_radeon_cp_stop_t)
-#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( 0x44)
-#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( 0x45)
-#define DRM_IOCTL_RADEON_CP_SWAP DRM_IO( 0x46)
-#define DRM_IOCTL_RADEON_CP_CLEAR DRM_IOW( 0x47, drm_radeon_clear_t)
-#define DRM_IOCTL_RADEON_CP_VERTEX DRM_IOW( 0x48, drm_radeon_vertex_t)
-#define DRM_IOCTL_RADEON_CP_INDICES DRM_IOW( 0x49, drm_radeon_indices_t)
-#define DRM_IOCTL_RADEON_CP_BLIT DRM_IOW( 0x4a, drm_radeon_blit_t)
-#define DRM_IOCTL_RADEON_CP_PACKET DRM_IOWR(0x4b, drm_radeon_packet_t)
+#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( 0x40, drm_radeon_init_t)
+#define DRM_IOCTL_RADEON_CP_START DRM_IO( 0x41)
+#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( 0x42, drm_radeon_cp_stop_t)
+#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( 0x43)
+#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( 0x44)
+#define DRM_IOCTL_RADEON_RESET DRM_IO( 0x45)
+#define DRM_IOCTL_RADEON_PAGEFLIP DRM_IOW( 0x46, drm_radeon_pageflip_t)
+#define DRM_IOCTL_RADEON_SWAP DRM_IO( 0x47)
+#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( 0x48, drm_radeon_clear_t)
+#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( 0x49, drm_radeon_vertex_t)
+#define DRM_IOCTL_RADEON_INDICES DRM_IOW( 0x4a, drm_radeon_indices_t)
+#define DRM_IOCTL_RADEON_BLIT DRM_IOW( 0x4b, drm_radeon_blit_t)
+#define DRM_IOCTL_RADEON_STIPPLE DRM_IOWR(0x4c, drm_radeon_stipple_t)
+#define DRM_IOCTL_RADEON_PACKET DRM_IOWR(0x4d, drm_radeon_packet_t)
/* SiS specific ioctls */
-#define SIS_IOCTL_FB_ALLOC DRM_IOWR( 0x44, drm_sis_mem_t)
-#define SIS_IOCTL_FB_FREE DRM_IOW( 0x45, drm_sis_mem_t)
-#define SIS_IOCTL_AGP_INIT DRM_IOWR( 0x53, drm_sis_agp_t)
-#define SIS_IOCTL_AGP_ALLOC DRM_IOWR( 0x54, drm_sis_mem_t)
-#define SIS_IOCTL_AGP_FREE DRM_IOW( 0x55, drm_sis_mem_t)
-#define SIS_IOCTL_FLIP DRM_IOW( 0x48, drm_sis_flip_t)
-#define SIS_IOCTL_FLIP_INIT DRM_IO( 0x49)
-#define SIS_IOCTL_FLIP_FINAL DRM_IO( 0x50)
+#define SIS_IOCTL_FB_ALLOC DRM_IOWR(0x44, drm_sis_mem_t)
+#define SIS_IOCTL_FB_FREE DRM_IOW( 0x45, drm_sis_mem_t)
+#define SIS_IOCTL_AGP_INIT DRM_IOWR(0x53, drm_sis_agp_t)
+#define SIS_IOCTL_AGP_ALLOC DRM_IOWR(0x54, drm_sis_mem_t)
+#define SIS_IOCTL_AGP_FREE DRM_IOW( 0x55, drm_sis_mem_t)
+#define SIS_IOCTL_FLIP DRM_IOW( 0x48, drm_sis_flip_t)
+#define SIS_IOCTL_FLIP_INIT DRM_IO( 0x49)
+#define SIS_IOCTL_FLIP_FINAL DRM_IO( 0x50)
#endif