Fix a lot of stencil bugs in tuxracer. Reflections work now, shadows

are almost right.

4 files changed, 40 insertions, 40 deletions

diff --git a/xc/lib/GL/mesa/src/drv/i830/i830_3d_reg.h b/xc/lib/GL/mesa/src/drv/i830/i830_3d_reg.h
index 5cc73d6b3..6d66de9de 100644
--- a/xc/lib/GL/mesa/src/drv/i830/i830_3d_reg.h
+++ b/xc/lib/GL/mesa/src/drv/i830/i830_3d_reg.h
@@ -421,10 +421,11 @@
 #define LOGICOP_OR_RVRSE		0xd
 #define LOGICOP_OR			0xe
 #define LOGICOP_SET			0xf
-#define MODE4_ENABLE_STENCIL_MASK	((1<<17)|(1<<16)|(0xffff))
+#define MODE4_ENABLE_STENCIL_TEST_MASK	((1<<17)|(0xff00))
 #define ENABLE_STENCIL_TEST_MASK	(1<<17)
-#define ENABLE_STENCIL_WRITE_MASK	(1<<16)
 #define STENCIL_TEST_MASK(x)		((x)<<8)
+#define MODE4_ENABLE_STENCIL_WRITE_MASK	((1<<16)|(0x00ff))
+#define ENABLE_STENCIL_WRITE_MASK	(1<<16)
 #define STENCIL_WRITE_MASK(x)		(x)
 
 /* STATE3D_MODES_5, p196 */
diff --git a/xc/lib/GL/mesa/src/drv/i830/i830_context.c b/xc/lib/GL/mesa/src/drv/i830/i830_context.c
index 5ff8f1eb1..74b643dfd 100644
--- a/xc/lib/GL/mesa/src/drv/i830/i830_context.c
+++ b/xc/lib/GL/mesa/src/drv/i830/i830_context.c
@@ -326,7 +326,7 @@ GLboolean i830CreateContext( const __GLcontextModes *mesaVis,
    /* Completely disable stenciling for now, there are some serious issues
     * with stencil.
     */
-#if 1
+#if 0
    imesa->hw_stencil = 0;
 #endif
 
diff --git a/xc/lib/GL/mesa/src/drv/i830/i830_ioctl.c b/xc/lib/GL/mesa/src/drv/i830/i830_ioctl.c
index e18bbbc6c..41d434b29 100644
--- a/xc/lib/GL/mesa/src/drv/i830/i830_ioctl.c
+++ b/xc/lib/GL/mesa/src/drv/i830/i830_ioctl.c
@@ -149,7 +149,7 @@ static void i830ClearWithTris(GLcontext *ctx, GLbitfield mask,
    GLuint old_dirty;
    int x0, y0, x1, y1;
 
-   if (I830_DEBUG & DEBUG_IOCTL)
+   if (I830_DEBUG & DEBUG_IOCTL) 
      fprintf(stderr, "Clearing with triangles\n");
 
    old_dirty = imesa->dirty & ~I830_UPLOAD_CLIPRECTS;
@@ -352,31 +352,36 @@ static void i830ClearWithTris(GLcontext *ctx, GLbitfield mask,
 						     ENABLE_DEPTH_WRITE |
 						     ENABLE_COLOR_WRITE);
 
-      sarea->ContextState[I830_CTXREG_ENABLES_2] |= (ENABLE_STENCIL_WRITE |
-					    DISABLE_DEPTH_WRITE |
-					    (1 << WRITEMASK_RED_SHIFT) |
-					    (1 << WRITEMASK_GREEN_SHIFT) |
-					    (1 << WRITEMASK_BLUE_SHIFT) |
-					    (1 << WRITEMASK_ALPHA_SHIFT) |
-					    ENABLE_COLOR_WRITE);
-
-      sarea->ContextState[I830_CTXREG_STATE4] &= ~MODE4_ENABLE_STENCIL_MASK;
-      sarea->ContextState[I830_CTXREG_STATE4] |= (ENABLE_STENCIL_TEST_MASK |
-						 ENABLE_STENCIL_WRITE_MASK |
-						 STENCIL_TEST_MASK(s_mask) |
-						 STENCIL_WRITE_MASK(s_mask));
-
-      sarea->ContextState[I830_CTXREG_STENCILTST] &= ~(STENCIL_OPS_MASK |
-					       STENCIL_REF_VALUE_MASK |
-					       ENABLE_STENCIL_TEST_FUNC_MASK);
-      sarea->ContextState[I830_CTXREG_STENCILTST] |= (ENABLE_STENCIL_PARMS |
-			      ENABLE_STENCIL_REF_VALUE |
-			      ENABLE_STENCIL_TEST_FUNC |
-			      STENCIL_FAIL_OP(STENCILOP_REPLACE) |
-			      STENCIL_PASS_DEPTH_FAIL_OP(STENCILOP_REPLACE) |
-			      STENCIL_PASS_DEPTH_PASS_OP(STENCILOP_REPLACE) |
-			      STENCIL_REF_VALUE((ctx->Stencil.Clear & 0xff)) |
-			      STENCIL_TEST_FUNC(COMPAREFUNC_ALWAYS));
+      sarea->ContextState[I830_CTXREG_ENABLES_2] |= 
+	 (ENABLE_STENCIL_WRITE |
+	  DISABLE_DEPTH_WRITE |
+	  (1 << WRITEMASK_RED_SHIFT) |
+	  (1 << WRITEMASK_GREEN_SHIFT) |
+	  (1 << WRITEMASK_BLUE_SHIFT) |
+	  (1 << WRITEMASK_ALPHA_SHIFT) |
+	  ENABLE_COLOR_WRITE);
+
+      sarea->ContextState[I830_CTXREG_STATE4] &= 
+	 ~MODE4_ENABLE_STENCIL_WRITE_MASK;
+
+      sarea->ContextState[I830_CTXREG_STATE4] |= 
+	 (ENABLE_STENCIL_WRITE_MASK |
+	  STENCIL_WRITE_MASK(s_mask));
+
+      sarea->ContextState[I830_CTXREG_STENCILTST] &= 
+	 ~(STENCIL_OPS_MASK |
+	   STENCIL_REF_VALUE_MASK |
+	   ENABLE_STENCIL_TEST_FUNC_MASK);
+
+      sarea->ContextState[I830_CTXREG_STENCILTST] |= 
+	 (ENABLE_STENCIL_PARMS |
+	  ENABLE_STENCIL_REF_VALUE |
+	  ENABLE_STENCIL_TEST_FUNC |
+	  STENCIL_FAIL_OP(STENCILOP_REPLACE) |
+	  STENCIL_PASS_DEPTH_FAIL_OP(STENCILOP_REPLACE) |
+	  STENCIL_PASS_DEPTH_PASS_OP(STENCILOP_REPLACE) |
+	  STENCIL_REF_VALUE((ctx->Stencil.Clear & 0xff)) |
+	  STENCIL_TEST_FUNC(COMPAREFUNC_ALWAYS));
 
       if(0) 
 	fprintf(stderr, "Enables_1 (0x%x) Enables_2 (0x%x) StenTst (0x%x)\n"
@@ -459,7 +464,7 @@ static void i830Clear(GLcontext *ctx, GLbitfield mask, GLboolean all,
       } else {
 	 clear.flags |= I830_DEPTH;
 	 clear.clear_depthmask |= imesa->stencil_clear_mask;
-	 clear.clear_depth |= imesa->stencil_clear_mask;
+	 clear.clear_depth |= (ctx->Stencil.Clear & 0xff) << 24;
       }
       mask &= ~DD_STENCIL_BIT;
    }
@@ -467,8 +472,6 @@ static void i830Clear(GLcontext *ctx, GLbitfield mask, GLboolean all,
    /* First check for clears that need to happen with triangles */
    if(tri_mask) {
       i830ClearWithTris(ctx, tri_mask, all, cx, cy, cw, ch);
-   } else {
-      mask |= tri_mask;
    }
 
    if (clear.flags) {
diff --git a/xc/lib/GL/mesa/src/drv/i830/i830_state.c b/xc/lib/GL/mesa/src/drv/i830/i830_state.c
index 8a04d857b..f01f83b1a 100644
--- a/xc/lib/GL/mesa/src/drv/i830/i830_state.c
+++ b/xc/lib/GL/mesa/src/drv/i830/i830_state.c
@@ -123,11 +123,9 @@ static void i830StencilFunc(GLcontext *ctx, GLenum func, GLint ref,
    }
 
    I830_STATECHANGE(imesa, I830_UPLOAD_CTX);
-   imesa->Setup[I830_CTXREG_STATE4] &= ~MODE4_ENABLE_STENCIL_MASK;
+   imesa->Setup[I830_CTXREG_STATE4] &= ~MODE4_ENABLE_STENCIL_TEST_MASK;
    imesa->Setup[I830_CTXREG_STATE4] |= (ENABLE_STENCIL_TEST_MASK |
-					ENABLE_STENCIL_WRITE_MASK |
-					STENCIL_TEST_MASK(mask) |
-					STENCIL_WRITE_MASK(mask));
+					STENCIL_TEST_MASK(mask));
    imesa->Setup[I830_CTXREG_STENCILTST] &= ~(STENCIL_REF_VALUE_MASK |
 					     ENABLE_STENCIL_TEST_FUNC_MASK);
    imesa->Setup[I830_CTXREG_STENCILTST] |= (ENABLE_STENCIL_REF_VALUE |
@@ -146,10 +144,8 @@ static void i830StencilMask(GLcontext *ctx, GLuint mask)
    mask = mask & 0xff;
 
    I830_STATECHANGE(imesa, I830_UPLOAD_CTX);
-   imesa->Setup[I830_CTXREG_STATE4] &= ~MODE4_ENABLE_STENCIL_MASK;
-   imesa->Setup[I830_CTXREG_STATE4] |= (ENABLE_STENCIL_TEST_MASK |
-					ENABLE_STENCIL_WRITE_MASK |
-					STENCIL_TEST_MASK(mask) |
+   imesa->Setup[I830_CTXREG_STATE4] &= ~MODE4_ENABLE_STENCIL_WRITE_MASK;
+   imesa->Setup[I830_CTXREG_STATE4] |= (ENABLE_STENCIL_WRITE_MASK |
 					STENCIL_WRITE_MASK(mask));
 }