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path: root/drivers/gpu/drm/i915
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2013-02-08Merge branch 'fbcon-locking-fixes' of ssh://people.freedesktop.org/~airlied/l...Dave Airlie8-26/+105
2013-02-08Merge tag 'drm-intel-next-2013-02-01' of git://people.freedesktop.org/~danvet...Dave Airlie29-1662/+2165
2013-02-01GPU/i915: Fix acpi_bus_get_device() check in drivers/gpu/drm/i915/intel_opreg...Yasuaki Ishimatsu1-1/+1
2013-01-31drm/i915: Set the SR01 "screen off" bit in i915_redisable_vga() tooVille Syrjälä1-2/+1
2013-01-31drm/i915: Kill IS_DISPLAYREG()Ville Syrjälä1-103/+1
2013-01-31drm/i915: Introduce i915_vgacntrl_reg()Ville Syrjälä4-20/+16
2013-01-31drm/i915: gen6_gmch_remove can be staticChanglong Xie1-1/+1
2013-01-31drm/i915: dynamic Haswell display power well supportDaniel Vetter2-1/+38
2013-01-31drm/i915: check the power down well on assert_pipe()Paulo Zanoni1-3/+9
2013-01-31drm/i915: don't send DP "idle" pattern before "normal" on HSW PORT_APaulo Zanoni1-6/+10
2013-01-31drm/i915: don't run hsw power well code on !hswDaniel Vetter1-0/+3
2013-01-31drm/i915: kill cargo-culted locking from power well codeDaniel Vetter1-4/+0
2013-01-31drm/i915: Only run idle processing from i915_gem_retire_requests_workerChris Wilson3-14/+4
2013-01-31drm/i915: Fix CAGF for HSWBen Widawsky2-3/+9
2013-01-31drm/i915: Reclaim GTT space for failed PPGTTBen Widawsky1-17/+16
2013-01-31drm/i915: remove intel_gtt structureBen Widawsky3-30/+11
2013-01-31drm/i915: Add probe and remove to the gtt opsBen Widawsky3-79/+114
2013-01-31drm/i915: extract hw ppgtt setup/cleanup codeDaniel Vetter2-24/+45
2013-01-31drm/i915: pte_encode is gen6+Daniel Vetter1-10/+14
2013-01-31drm/i915: vfuncs for ppgttDaniel Vetter2-56/+65
2013-01-31drm/i915: vfuncs for gtt_clear_range/insert_entriesDaniel Vetter2-59/+83
2013-01-31drm/i915: Error state should print /sys/kernel/debugBen Widawsky1-1/+2
2013-01-31drm/i915: move DP save/restore into i915_ums.cDaniel Vetter2-28/+25
2013-01-31drm/i915: dont save/restore VGA state for kmsDaniel Vetter3-23/+28
2013-01-31drm/i915: extract ums suspend/resume into i915_ums.cDaniel Vetter4-452/+485
2013-01-28drm/i915: move modeset checks out of save/restore_modeset_regDaniel Vetter1-23/+15
2013-01-28drm/i915: Implement WaVSRefCountFullforceMissDisableBen Widawsky2-0/+5
2013-01-28drm/i915: turn on the power well before suspendingPaulo Zanoni3-1/+4
2013-01-28drm/i915: set TRANSCODER_EDP even earlierPaulo Zanoni1-5/+5
2013-01-28drm/i915: fixup per-crtc locking in intel_release_load_detect_pipeDaniel Vetter1-0/+1
2013-01-26drm/i915: only disable enabled planes on intel_fb_restore_modePaulo Zanoni1-1/+2
2013-01-26drm/i915: fix intel_init_power_wellsPaulo Zanoni4-26/+46
2013-01-26drm/i915: SWF screatch registers need an offset on VLVVille Syrjälä1-13/+13
2013-01-26drm/i915: Include display_mmio_offset in sequencer index/data registersVille Syrjälä1-2/+8
2013-01-26drm/i915: Pass VLV_DISPLAY_BASE + reg to intel_{hdmi, dp}_init on VLVVille Syrjälä1-8/+8
2013-01-26drm/i915: VLV doesn't have SDVOVille Syrjälä1-7/+2
2013-01-26drm/i915: Always use adpa_regVille Syrjälä1-14/+15
2013-01-26drm/i915: PLL registers need an offset on VLVVille Syrjälä1-4/+4
2013-01-24drm/i915: Set display_mmio_offset for VLVVille Syrjälä1-0/+2
2013-01-24drm/i915: GPIO/GMBUS registers need an offset on VLVVille Syrjälä1-0/+2
2013-01-24drm/i915: DPIO registers are VLV only and need an offsetVille Syrjälä1-4/+6
2013-01-24drm/i915: Spell out VLV_DISPLAY_BASE for interrupt registersVille Syrjälä1-5/+5
2013-01-24drm/i915: Make VLV_GUNIT_CLOCK_GATE register value more readableVille Syrjälä1-1/+1
2013-01-24drm/i915: FB_BLC_SELF_VLV is VLV only and needs an offsetVille Syrjälä1-1/+1
2013-01-24drm/i915: Pipe palette registers need an offset on VLVVille Syrjälä1-2/+2
2013-01-24drm/i915: Pipe timing registers need an offset on VLVVille Syrjälä1-18/+18
2013-01-24drm/i915: PORT_HOTPLUG registers need an offset on VLVVille Syrjälä1-2/+2
2013-01-24drm/i915: Panel fitter registers need an offset on VLVVille Syrjälä1-3/+3
2013-01-24drm/i915: DPFLIPSTAT and DPINVGTT registers are VLV only and need an offsetVille Syrjälä1-2/+2
2013-01-24drm/i915: DSPFW registers need an offset on VLVVille Syrjälä1-3/+3
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