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authorGeorge Sapountzis <gsap7@yahoo.gr>2006-12-27 20:56:45 +0200
committerGeorge Sapountzis <gsap7@yahoo.gr>2007-01-28 01:24:18 +0200
commitd350860e29f043e98bfb1da74b26280f1755ab6f (patch)
treef62d6c4ee07751521fbdf49409828afcea1a5dd2
parent5fa77f2d122e7267911a15235338d8d3f9eece2e (diff)
Keep PCI mach64 only (atipreinit.c, atimode.c), drop:
- Chip < ATI_CHIP_88800GXC - Chipset != ATI_CHIPSET_ATI - Adapter != ATI_ADAPTER_MACH64 - depth < 8 atimode.c only: - NewHW.crtc != ATI_CRTC_MACH64 This allows to drop VGACalculate(), VGAWonderCalculate() cruft early.
-rw-r--r--src/Makefile.am1
-rw-r--r--src/atibank.c107
-rw-r--r--src/atibank.h17
-rw-r--r--src/atibus.c2
-rw-r--r--src/atiio.h82
-rw-r--r--src/atimach64io.h17
-rw-r--r--src/atimode.c169
-rw-r--r--src/atipreinit.c591
-rw-r--r--src/atistruct.h5
-rw-r--r--src/ativalid.c32
-rw-r--r--src/ativga.c259
-rw-r--r--src/ativga.h1
-rw-r--r--src/ativgaio.h4
-rw-r--r--src/atiwonder.c132
-rw-r--r--src/atiwonder.h1
15 files changed, 26 insertions, 1394 deletions
diff --git a/src/Makefile.am b/src/Makefile.am
index b1410f73..0b70abd1 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -130,7 +130,6 @@ EXTRA_DIST = \
ati.h \
atii2c.h \
atiident.h \
- atiio.h \
atiload.h \
atilock.h \
atimach64accel.h \
diff --git a/src/atibank.c b/src/atibank.c
index 446c55ff..c53cc545 100644
--- a/src/atibank.c
+++ b/src/atibank.c
@@ -32,45 +32,6 @@
#ifndef AVOID_CPIO
/*
- * ATI VGA Wonder V3 adapters use an ATI 18800 chip and are single-banked.
- * Bank selection is done with bits 0x1E of ATI extended VGA register index
- * 0xB2.
- */
-
-/*
- * ATIV3SetBank --
- *
- * Set an ATI 18800's bank number.
- */
-void
-ATIV3SetBank
-(
- ATIPtr pATI,
- unsigned int iBank
-)
-{
- ATIModifyExtReg(pATI, 0xB2U, -1, (CARD8)(~0x1EU), SetBits(iBank, 0x1EU));
-}
-
-/*
- * ATIV3SetReadWrite --
- *
- * Set an ATI 18800's bank number.
- */
-int
-ATIV3SetReadWrite
-(
- ScreenPtr pScreen,
- unsigned int iBank
-)
-{
- ATIPtr pATI = ATIPTR(XF86SCRNINFO(pScreen));
-
- ATIModifyExtReg(pATI, 0xB2U, -1, (CARD8)(~0x1EU), SetBits(iBank, 0x1EU));
- return 0;
-}
-
-/*
* ATI VGA Wonder V4 and V5 adapters use an ATI 18800-1 chip. Bank selection
* is done with ATI extended VGA register index 0xB2. The format is:
*
@@ -145,22 +106,6 @@ ATIV4V5SetWrite
}
/*
- * ATIV4V5SetReadWrite --
- *
- * Set an ATI 18800-1's read and write bank numbers.
- */
-int
-ATIV4V5SetReadWrite
-(
- ScreenPtr pScreen,
- unsigned int iBank
-)
-{
- ATIV4V5SetBank(ATIPTR(XF86SCRNINFO(pScreen)), iBank);
- return 0;
-}
-
-/*
* In addition to ATI extended register index 0xB2, 28800's, 68800's and
* 88800's define banking bits in bits 0x0F of ATI extended VGA register index
* 0xAE. These are only needed for adapters with more than 1MB of video
@@ -357,56 +302,4 @@ ATIMach64SetBankPlanar
outr(MEM_VGA_WP_SEL, tmp);
}
-/*
- * ATIMach64SetReadPlanar --
- *
- * Set read bank number for small dual paged apertures.
- */
-int
-ATIMach64SetReadPlanar
-(
- ScreenPtr pScreen,
- unsigned int iBank
-)
-{
- ATIPtr pATI = ATIPTR(XF86SCRNINFO(pScreen));
-
- outr(MEM_VGA_RP_SEL, ATIMach64MassagePlanarBankNumber(iBank));
- return 0;
-}
-
-/*
- * ATIMach64SetWritePlanar --
- *
- * Set write bank number for small dual paged apertures.
- */
-int
-ATIMach64SetWritePlanar
-(
- ScreenPtr pScreen,
- unsigned int iBank
-)
-{
- ATIPtr pATI = ATIPTR(XF86SCRNINFO(pScreen));
-
- outr(MEM_VGA_WP_SEL, ATIMach64MassagePlanarBankNumber(iBank));
- return 0;
-}
-
-/*
- * ATIMach64SetReadWritePlanar --
- *
- * Set read and write bank numbers for small dual paged apertures.
- */
-int
-ATIMach64SetReadWritePlanar
-(
- ScreenPtr pScreen,
- unsigned int iBank
-)
-{
- ATIMach64SetBankPlanar(ATIPTR(XF86SCRNINFO(pScreen)), iBank);
- return 0;
-}
-
#endif /* AVOID_CPIO */
diff --git a/src/atibank.h b/src/atibank.h
index 49ffc549..d50aa68f 100644
--- a/src/atibank.h
+++ b/src/atibank.h
@@ -34,19 +34,10 @@
*/
/*
- * Bank selection function for VGA Wonder V3 adapters (which are
- * single-banked).
- */
-#define ATIV3SetRead ATIV3SetReadWrite
-#define ATIV3SetWrite ATIV3SetReadWrite
-extern miBankProc ATIV3SetReadWrite;
-
-/*
* Bank selection functions for VGA Wonder V4 and V5 adapters.
*/
extern miBankProc ATIV4V5SetRead,
- ATIV4V5SetWrite,
- ATIV4V5SetReadWrite;
+ ATIV4V5SetWrite;
/*
* Bank selection functions for 28800-x, 68800-x and 88800 based adapters.
@@ -63,9 +54,6 @@ extern miBankProc ATIx8800SetRead,
extern miBankProc ATIMach64SetReadPacked,
ATIMach64SetWritePacked,
ATIMach64SetReadWritePacked;
-extern miBankProc ATIMach64SetReadPlanar,
- ATIMach64SetWritePlanar,
- ATIMach64SetReadWritePlanar;
/*
* The CRT save/restore code also needs a separate banking interface that can
@@ -75,8 +63,7 @@ extern miBankProc ATIMach64SetReadPlanar,
typedef void ATIBankProc(ATIPtr, unsigned int);
typedef ATIBankProc *ATIBankProcPtr;
-extern ATIBankProc ATIV3SetBank,
- ATIV4V5SetBank,
+extern ATIBankProc ATIV4V5SetBank,
ATIx8800SetBank,
ATIMach64SetBankPacked,
ATIMach64SetBankPlanar;
diff --git a/src/atibus.c b/src/atibus.c
index f20e4725..3636b3bf 100644
--- a/src/atibus.c
+++ b/src/atibus.c
@@ -30,7 +30,7 @@
#include "atiadapter.h"
#include "atibus.h"
#include "atichip.h"
-#include "atiio.h"
+#include "atimach64io.h"
#include "atistruct.h"
#include "ativersion.h"
diff --git a/src/atiio.h b/src/atiio.h
deleted file mode 100644
index 6477f36d..00000000
--- a/src/atiio.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * Copyright 1997 through 2003 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org
- *
- * Permission to use, copy, modify, distribute, and sell this software and its
- * documentation for any purpose is hereby granted without fee, provided that
- * the above copyright notice appear in all copies and that both that copyright
- * notice and this permission notice appear in supporting documentation, and
- * that the name of Marc Aurele La France not be used in advertising or
- * publicity pertaining to distribution of the software without specific,
- * written prior permission. Marc Aurele La France makes no representations
- * about the suitability of this software for any purpose. It is provided
- * "as-is" without express or implied warranty.
- *
- * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
- * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO
- * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR
- * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
- * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef ___ATIIO_H___
-
-#if !defined(___ATI_H___) && defined(XFree86Module)
-# error missing #include "ati.h" before #include "atiio.h"
-# undef XFree86Module
-#endif
-
-#define ___ATIIO_H___ 1
-
-#include "atiregs.h"
-
-#include "compiler.h"
-
-/* I/O decoding definitions */
-typedef enum
-{
- SPARSE_IO,
- BLOCK_IO
-} ATIIODecodingType;
-
-#ifndef AVOID_CPIO
-
-/* Wait until "n" queue entries are free */
-#define ibm8514WaitQueue(_n) \
- { \
- while (inw(GP_STAT) & (0x0100U >> (_n))); \
- }
-#define ATIWaitQueue(_n) \
- { \
- while (inw(EXT_FIFO_STATUS) & (0x010000U >> (_n))); \
- }
-
-/* Wait until GP is idle and queue is empty */
-#define WaitIdleEmpty() \
- { \
- while (inw(GP_STAT) & (GPBUSY | 1)); \
- }
-#define ProbeWaitIdleEmpty() \
- { \
- int _i; \
- CARD16 _value; \
- for (_i = 0; _i < 100000; _i++) \
- { \
- _value = inw(GP_STAT); \
- if (_value == (CARD16)(-1)) \
- break; \
- if (!(_value & (GPBUSY | 1))) \
- break; \
- } \
- }
-
-/* Wait until GP has data available */
-#define WaitDataReady() \
- { \
- while (!(inw(GP_STAT) & DATARDY)); \
- }
-
-#endif /* AVOID_CPIO */
-
-#endif /* ___ATIIO_H___ */
diff --git a/src/atimach64io.h b/src/atimach64io.h
index 15a92ad6..d1b14d24 100644
--- a/src/atimach64io.h
+++ b/src/atimach64io.h
@@ -33,17 +33,17 @@
#define ___ATIMACH64IO_H___ 1
-#include "atiio.h"
+#include "atiregs.h"
#include "atistruct.h"
+#include "compiler.h"
+
/*
* A few important notes on some of the I/O statements provided:
*
* inl/outl 32-bit R/W through PIO space. The register is specified as the
* actual PIO address. These are actually defined in compiler.h.
*
- * inw/outw 16-bit counterparts to inl/outl. Not used for Mach64 support.
- *
* inb/outb 8-bit counterparts to inl/outl.
*
* inm/outm 32-bit R/W through MMIO space. The register is specified as
@@ -88,6 +88,13 @@
* accessed (nor by what).
*/
+/* I/O decoding definitions */
+typedef enum
+{
+ SPARSE_IO,
+ BLOCK_IO
+} ATIIODecodingType;
+
#define inm(_Register) \
MMIO_IN32(pATI->pBlock[GetBits(_Register, BLOCK_SELECT)], \
(_Register) & MM_IO_SELECT)
@@ -111,17 +118,13 @@
/* Cause a cpp syntax error if any of these are used */
#undef inb
-#undef inw
#undef inl
#undef outb
-#undef outw
#undef outl
#define inb() /* Nothing */
-#define inw() /* Nothing */
#define inl() /* Nothing */
#define outb() /* Nothing */
-#define outw() /* Nothing */
#define outl() /* Nothing */
#else /* AVOID_CPIO */
diff --git a/src/atimode.c b/src/atimode.c
index 17210de1..3ac46d9d 100644
--- a/src/atimode.c
+++ b/src/atimode.c
@@ -273,8 +273,6 @@ ATIModePreInit
ATIVGAWonderPreInit(pATI, pATIHW);
}
- if (pATI->Chip >= ATI_CHIP_88800GXC)
-
#endif /* AVOID_CPIO */
{
@@ -447,8 +445,6 @@ ATIModeSave
ATIVGAWonderSave(pATI, pATIHW);
}
- if (pATI->Chip >= ATI_CHIP_88800GXC)
-
#endif /* AVOID_CPIO */
{
@@ -507,27 +503,9 @@ ATIModeSave
ATIRGB514Save(pATI, pATIHW);
}
-#ifndef AVOID_CPIO
-
- /*
- * For some unknown reason, CLKDIV2 needs to be turned off to save the
- * DAC's LUT reliably on VGA Wonder VLB adapters.
- */
- if ((pATI->Adapter == ATI_ADAPTER_NONISA) && (pATIHW->seq[1] & 0x08U))
- PutReg(SEQX, 0x01U, pATIHW->seq[1] & ~0x08U);
-
-#endif /* AVOID_CPIO */
-
/* Save RAMDAC state */
ATIDACSave(pATI, pATIHW);
-#ifndef AVOID_CPIO
-
- if ((pATI->Adapter == ATI_ADAPTER_NONISA) && (pATIHW->seq[1] & 0x08U))
- PutReg(SEQX, 0x01U, pATIHW->seq[1]);
-
-#endif /* AVOID_CPIO */
-
/*
* The server has already saved video memory contents when switching out of
* its virtual console, so don't do it again.
@@ -588,29 +566,13 @@ ATIModeCalculate
* limitations.
*/
VScan = pATI->LCDVertical / pMode->VDisplay;
- switch (pATIHW->crtc)
{
-
-#ifndef AVOID_CPIO
-
- case ATI_CRTC_VGA:
- if (VScan > 64)
- VScan = 64;
- pMode->VScan = VScan;
- break;
-
-#endif /* AVOID_CPIO */
-
- case ATI_CRTC_MACH64:
pMode->VScan = 0;
- if (VScan <= 1)
- break;
+ if (VScan > 1)
+ {
VScan = 2;
pMode->Flags |= V_DBLSCAN;
- break;
-
- default:
- break;
+ }
}
pMode->HSyncStart = pMode->HDisplay + pATI->LCDHSyncStart;
@@ -625,132 +587,9 @@ ATIModeCalculate
ATIDivide(pATI->LCDVBlankWidth, VScan, 0, 0);
}
- switch (pATIHW->crtc)
{
-
-#ifndef AVOID_CPIO
-
- case ATI_CRTC_VGA:
- /* Fill in VGA data */
- ATIVGACalculate(pATI, pATIHW, pMode);
-
- /* Fill in VGA Wonder data */
- if (pATI->CPIO_VGAWonder)
- ATIVGAWonderCalculate(pATI, pATIHW, pMode);
-
- if (pATI->Chip >= ATI_CHIP_88800GXC)
- {
- if (pATI->Chip >= ATI_CHIP_264CT)
- {
- /*
- * Selected bits of accelerator & VGA CRTC registers are
- * actually copies of each other.
- */
- pATIHW->crtc_h_total_disp =
- SetBits(pMode->CrtcHTotal, CRTC_H_TOTAL) |
- SetBits(pMode->CrtcHDisplay, CRTC_H_DISP);
- pATIHW->crtc_h_sync_strt_wid =
- SetBits(pMode->CrtcHSyncStart, CRTC_H_SYNC_STRT) |
- SetBits(pMode->CrtcHSkew, CRTC_H_SYNC_DLY) | /* ? */
- SetBits(GetBits(pMode->CrtcHSyncStart, 0x0100U),
- CRTC_H_SYNC_STRT_HI) |
- SetBits(pMode->CrtcHSyncEnd, CRTC_H_SYNC_WID);
- if (pMode->Flags & V_NHSYNC)
- pATIHW->crtc_h_sync_strt_wid |= CRTC_H_SYNC_POL;
-
- pATIHW->crtc_v_total_disp =
- SetBits(pMode->CrtcVTotal, CRTC_V_TOTAL) |
- SetBits(pMode->CrtcVDisplay, CRTC_V_DISP);
- pATIHW->crtc_v_sync_strt_wid =
- SetBits(pMode->CrtcVSyncStart, CRTC_V_SYNC_STRT) |
- SetBits(pMode->CrtcVSyncEnd, CRTC_V_SYNC_END_VGA);
- if (pMode->Flags & V_NVSYNC)
- pATIHW->crtc_v_sync_strt_wid |= CRTC_V_SYNC_POL;
- }
-
- pATIHW->crtc_gen_cntl = inr(CRTC_GEN_CNTL) &
- ~(CRTC_DBL_SCAN_EN | CRTC_INTERLACE_EN |
- CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_CSYNC_EN |
- CRTC_PIX_BY_2_EN | CRTC_DISPLAY_DIS |
- CRTC_VGA_XOVERSCAN | CRTC_PIX_WIDTH |
- CRTC_BYTE_PIX_ORDER | CRTC_VGA_128KAP_PAGING |
- CRTC_VFC_SYNC_TRISTATE |
- CRTC_LOCK_REGS | /* Already off, but ... */
- CRTC_SYNC_TRISTATE | CRTC_EXT_DISP_EN |
- CRTC_DISP_REQ_EN | CRTC_VGA_LINEAR | CRTC_VGA_TEXT_132 |
- CRTC_CUR_B_TEST);
- /* Some of these are not relevent, but that doesn't matter */
- switch (pATI->depth)
- {
- case 1:
- pATIHW->crtc_gen_cntl |=
- SetBits(PIX_WIDTH_1BPP, CRTC_PIX_WIDTH);
- break;
-
- case 4:
- pATIHW->crtc_gen_cntl |=
- SetBits(PIX_WIDTH_4BPP, CRTC_PIX_WIDTH);
- break;
-
- case 8:
- pATIHW->crtc_gen_cntl |=
- SetBits(PIX_WIDTH_8BPP, CRTC_PIX_WIDTH);
- break;
-
- case 15:
- pATIHW->crtc_gen_cntl |=
- SetBits(PIX_WIDTH_15BPP, CRTC_PIX_WIDTH);
- break;
-
- case 16:
- pATIHW->crtc_gen_cntl |=
- SetBits(PIX_WIDTH_16BPP, CRTC_PIX_WIDTH);
- break;
-
- case 24:
- if (pATI->bitsPerPixel == 24)
- {
- pATIHW->crtc_gen_cntl |=
- SetBits(PIX_WIDTH_24BPP, CRTC_PIX_WIDTH);
- break;
- }
- if (pATI->bitsPerPixel != 32)
- break;
- /* Fall through */
-
- case 32:
- pATIHW->crtc_gen_cntl |=
- SetBits(PIX_WIDTH_32BPP, CRTC_PIX_WIDTH);
- break;
-
- default:
- break;
- }
-#if 0 /* This isn't needed, but is kept for reference */
- if (pMode->Flags & V_DBLSCAN)
- pATIHW->crtc_gen_cntl |= CRTC_DBL_SCAN_EN;
-#endif
- if (pMode->Flags & V_INTERLACE)
- pATIHW->crtc_gen_cntl |= CRTC_INTERLACE_EN;
- if ((pMode->Flags & (V_CSYNC | V_PCSYNC)) || pATI->OptionCSync)
- pATIHW->crtc_gen_cntl |= CRTC_CSYNC_EN;
- if (pATI->depth <= 4)
- pATIHW->crtc_gen_cntl |= CRTC_EN | CRTC_CNT_EN;
- else
- pATIHW->crtc_gen_cntl |=
- CRTC_EN | CRTC_VGA_LINEAR | CRTC_CNT_EN;
- }
- break;
-
-#endif /* AVOID_CPIO */
-
- case ATI_CRTC_MACH64:
/* Fill in Mach64 data */
ATIMach64Calculate(pATI, pATIHW, pMode);
- break;
-
- default:
- break;
}
/* Set up LCD register values */
@@ -1070,7 +909,6 @@ ATIModeSet
#endif /* AVOID_CPIO */
- if (pATI->Chip >= ATI_CHIP_88800GXC)
{
/* Stop CRTC */
outr(CRTC_GEN_CNTL,
@@ -1154,7 +992,6 @@ ATIModeSet
ATIVGASet(pATI, pATIHW);
/* Load Mach64 registers */
- if (pATI->Chip >= ATI_CHIP_88800GXC)
{
/* Load MMIO registers */
if (pATI->Block0Base)
diff --git a/src/atipreinit.c b/src/atipreinit.c
index ff5cc04c..bfdd56d3 100644
--- a/src/atipreinit.c
+++ b/src/atipreinit.c
@@ -54,250 +54,6 @@
#include "vbe.h"
#include "xf86RAC.h"
-#ifndef AVOID_CPIO
-
-typedef CARD16 Colour; /* The correct spelling should be OK :-) */
-
-/*
- * Bit patterns which are extremely unlikely to show up when reading from
- * nonexistant memory (which normally shows up as either all bits set or all
- * bits clear).
- */
-static const Colour Test_Pixel[] = {0x5AA5U, 0x55AAU, 0xA55AU, 0xCA53U};
-
-static const struct
-{
- int videoRamSize;
- int Miscellaneous_Options_Setting;
- struct
- {
- short int x, y;
- }
- Coordinates[NumberOf(Test_Pixel) + 1];
-}
-Test_Case[] =
-{
- /*
- * Given the engine settings used, only a 4M card will have enough memory
- * to back up the 1025th line of the display. Since the pixel coordinates
- * are zero-based, line 1024 will be the first one which is only backed on
- * 4M cards.
- *
- * <Mark_Weaver@brown.edu>:
- * In case memory is being wrapped, (0,0) and (0,1024) to make sure they
- * can each hold a unique value.
- */
- {4096, MEM_SIZE_4M, {{0,0}, {0,1024}, {-1,-1}}},
-
- /*
- * This card has 2M or less. On a 1M card, the first 2M of the card's
- * memory will have even doublewords backed by physical memory and odd
- * doublewords unbacked.
- *
- * Pixels 0 and 1 of a row will be in the zeroth doubleword, while pixels 2
- * and 3 will be in the first. Check both pixels 2 and 3 in case this is a
- * pseudo-1M card (one chip pulled to turn a 2M card into a 1M card).
- *
- * <Mark_Weaver@brown.edu>:
- * I don't have a 1M card, so I'm taking a stab in the dark. Maybe memory
- * wraps every 512 lines, or maybe odd doublewords are aliases of their
- * even doubleword counterparts. I try everything here.
- */
- {2048, MEM_SIZE_2M, {{0,0}, {0,512}, {2,0}, {3,0}, {-1,-1}}},
-
- /*
- * This is a either a 1M card or a 512k card. Test pixel 1, since it is an
- * odd word in an even doubleword.
- *
- * <Mark_Weaver@brown.edu>:
- * This is the same idea as the test above.
- */
- {1024, MEM_SIZE_1M, {{0,0}, {0,256}, {1,0}, {-1,-1}}},
-
- /*
- * Assume it is a 512k card by default, since that is the minimum
- * configuration.
- */
- {512, MEM_SIZE_512K, {{-1,-1}}}
-};
-
-/*
- * ATIMach32ReadPixel --
- *
- * Return the colour of the specified screen location. Called from
- * ATIMach32videoRam function below.
- */
-static Colour
-ATIMach32ReadPixel
-(
- const short int X,
- const short int Y
-)
-{
- Colour Pixel_Colour;
-
- /* Wait for idle engine */
- ProbeWaitIdleEmpty();
-
- /* Set up engine for pixel read */
- ATIWaitQueue(7);
- outw(RD_MASK, (CARD16)(~0));
- outw(DP_CONFIG, FG_COLOR_SRC_BLIT | DATA_WIDTH | DRAW | DATA_ORDER);
- outw(CUR_X, X);
- outw(CUR_Y, Y);
- outw(DEST_X_START, X);
- outw(DEST_X_END, X + 1);
- outw(DEST_Y_END, Y + 1);
-
- /* Wait for data to become ready */
- ATIWaitQueue(16);
- WaitDataReady();
-
- /* Read pixel colour */
- Pixel_Colour = inw(PIX_TRANS);
- ProbeWaitIdleEmpty();
- return Pixel_Colour;
-}
-
-/*
- * ATIMach32WritePixel --
- *
- * Set the colour of the specified screen location. Called from
- * ATIMach32videoRam function below.
- */
-static void
-ATIMach32WritePixel
-(
- const short int X,
- const short int Y,
- const Colour Pixel_Colour
-)
-{
- /* Set up engine for pixel write */
- ATIWaitQueue(9);
- outw(WRT_MASK, (CARD16)(~0));
- outw(DP_CONFIG, FG_COLOR_SRC_FG | DRAW | READ_WRITE);
- outw(ALU_FG_FN, MIX_FN_PAINT);
- outw(FRGD_COLOR, Pixel_Colour);
- outw(CUR_X, X);
- outw(CUR_Y, Y);
- outw(DEST_X_START, X);
- outw(DEST_X_END, X + 1);
- outw(DEST_Y_END, Y + 1);
-}
-
-/*
- * ATIMach32videoRam --
- *
- * Determine the amount of video memory installed on an 68800-6 based adapter.
- * This is done because these chips exhibit a bug that causes their
- * MISC_OPTIONS register to report 1M rather than the true amount of memory.
- *
- * This function is adapted from a similar function in mach32mem.c written by
- * Robert Wolff, David Dawes and Mark Weaver.
- */
-static int
-ATIMach32videoRam
-(
- void
-)
-{
- CARD16 clock_sel, mem_bndry, misc_options, ext_ge_config;
- Colour saved_Pixel[NumberOf(Test_Pixel)];
- unsigned int Case_Number, Pixel_Number;
- Bool AllPixelsOK;
-
- /* Save register values to be modified */
- clock_sel = inw(CLOCK_SEL);
- mem_bndry = inw(MEM_BNDRY);
- misc_options = inw(MISC_OPTIONS) & ~MEM_SIZE_ALIAS;
- ext_ge_config = inw(R_EXT_GE_CONFIG);
-
- /* Wait for enough FIFO entries */
- ATIWaitQueue(7);
-
- /* Enable accelerator */
- outw(CLOCK_SEL, clock_sel | DISABPASSTHRU);
-
- /* Make accelerator and VGA share video memory */
- outw(MEM_BNDRY, mem_bndry & ~(MEM_PAGE_BNDRY | MEM_BNDRY_ENA));
-
- /* Prevent video memory wrap */
- outw(MISC_OPTIONS, misc_options | MEM_SIZE_4M);
-
- /*
- * Set up the drawing engine for a pitch of 1024 at 16 bits per pixel. No
- * need to mess with the CRT because the results of this test are not
- * intended to be seen.
- */
- outw(EXT_GE_CONFIG, PIXEL_WIDTH_16 | ORDER_16BPP_565 | MONITOR_8514 |
- ALIAS_ENA);
- outw(GE_PITCH, 1024 >> 3);
- outw(GE_OFFSET_HI, 0);
- outw(GE_OFFSET_LO, 0);
-
- for (Case_Number = 0;
- Case_Number < (NumberOf(Test_Case) - 1);
- Case_Number++)
- {
- /* Reduce redundancy as per Mark_Weaver@brown.edu */
-# define TestPixel Test_Case[Case_Number].Coordinates[Pixel_Number]
-# define ForEachTestPixel \
- for (Pixel_Number = 0; TestPixel.x >= 0; Pixel_Number++)
-
- /* Save pixel colours that will be clobbered */
- ForEachTestPixel
- saved_Pixel[Pixel_Number] =
- ATIMach32ReadPixel(TestPixel.x, TestPixel.y);
-
- /* Write test patterns */
- ForEachTestPixel
- ATIMach32WritePixel(TestPixel.x, TestPixel.y,
- Test_Pixel[Pixel_Number]);
-
- /* Test for lost pixels */
- AllPixelsOK = TRUE;
- ForEachTestPixel
- {
- if (ATIMach32ReadPixel(TestPixel.x, TestPixel.y) !=
- Test_Pixel[Pixel_Number])
- {
- AllPixelsOK = FALSE;
- break;
- }
- }
-
- /* Restore clobbered pixels */
- ForEachTestPixel
- ATIMach32WritePixel(TestPixel.x, TestPixel.y,
- saved_Pixel[Pixel_Number]);
-
- /* End test on success */
- if (AllPixelsOK)
- break;
-
- /* Completeness */
-# undef ForEachTestPixel
-# undef TestPixel
- }
-
- /* Restore what was changed and correct MISC_OPTIONS register */
- ATIWaitQueue(4);
- outw(EXT_GE_CONFIG, ext_ge_config);
- misc_options |= Test_Case[Case_Number].Miscellaneous_Options_Setting;
- outw(MISC_OPTIONS, misc_options);
- outw(MEM_BNDRY, mem_bndry);
- outw(CLOCK_SEL, clock_sel);
-
- /* Wait for activity to die down */
- ProbeWaitIdleEmpty();
-
- /* Tell ATIPreInit the REAL story */
- return Test_Case[Case_Number].videoRamSize;
-}
-
-#endif /* AVOID_CPIO */
-
/*
* ATIReportMemory --
*
@@ -317,19 +73,6 @@ ATIReportMemory
snprintf(Buffer, SizeOf(Buffer), "%d kB of %s detected",
pATI->VideoRAM, MemoryTypeName);
-#ifndef AVOID_CPIO
-
- if (pATI->depth == 1)
- {
- /* 1bpp only uses one plane of four */
- pScreenInfo->videoRam /= 4;
- Message += snprintf(Message, Buffer + SizeOf(Buffer) - Message,
- " (using %d kB)", pScreenInfo->videoRam);
- }
- else
-
-#endif /* AVOID_CPIO */
-
if (pATI->VideoRAM > pScreenInfo->videoRam)
{
Message += snprintf(Message, Buffer + SizeOf(Buffer) - Message,
@@ -487,28 +230,6 @@ ATIPreInit
/* Promote chipset specification */
switch (pATI->Chipset)
{
-
-#ifndef AVOID_CPIO
-
- case ATI_CHIPSET_IBMVGA:
- if (pATI->Adapter == ATI_ADAPTER_VGA)
- break; /* XXX */
- /* Fall through */
-
- case ATI_CHIPSET_VGAWONDER:
- pATI->Chipset = ATI_CHIPSET_ATIVGA;
- break;
-
- case ATI_CHIPSET_IBM8514:
- if (pATI->Adapter == ATI_ADAPTER_8514A)
- break; /* XXX */
- /* Fall through */
-
- case ATI_CHIPSET_MACH8:
- case ATI_CHIPSET_MACH32:
-
-#endif /* AVOID_CPIO */
-
case ATI_CHIPSET_MACH64:
case ATI_CHIPSET_RAGE128:
case ATI_CHIPSET_RADEON:
@@ -523,8 +244,7 @@ ATIPreInit
pScreenInfo->monitor = pScreenInfo->confScreen->monitor;
/* Set depth, bpp, etc. */
- if ((pATI->Chipset != ATI_CHIPSET_ATI) ||
- (pATI->Chip < ATI_CHIP_264CT))
+ if ((pATI->Chip < ATI_CHIP_264CT))
{
i = NoDepth24Support; /* No support for >8bpp either */
DefaultDepth = 8;
@@ -542,15 +262,6 @@ ATIPreInit
{
static const CARD8 AllowedDepthBpp[][2] =
{
-
-#ifndef AVOID_CPIO
-
- { 1, 1},
- { 4, 4},
- { 4, 8},
-
-#endif /* AVOID_CPIO */
-
{ 8, 8},
{15, 16},
{16, 16},
@@ -781,70 +492,6 @@ ATIPreInit
/* Finish probing the adapter */
switch (pATI->Adapter)
{
-
-#ifndef AVOID_CPIO
-
- case ATI_ADAPTER_NONE:
- case ATI_ADAPTER_EGA:
- case ATI_ADAPTER_EGA_PLUS:
- case ATI_ADAPTER_VGA:
- case ATI_ADAPTER_BASIC:
- pATI->NewHW.SetBank = (ATIBankProcPtr)NoopDDA;
- pATI->BankInfo.SetSourceBank =
- pATI->BankInfo.SetDestinationBank =
- pATI->BankInfo.SetSourceAndDestinationBanks =
- (miBankProcPtr)NoopDDA;
- break;
-
- case ATI_ADAPTER_V3:
- pATI->NewHW.SetBank = ATIV3SetBank;
- pATI->BankInfo.SetSourceBank = ATIV3SetRead;
- pATI->BankInfo.SetDestinationBank = ATIV3SetWrite;
- pATI->BankInfo.SetSourceAndDestinationBanks = ATIV3SetReadWrite;
- break;
-
- case ATI_ADAPTER_V4:
- case ATI_ADAPTER_V5:
- pATI->NewHW.SetBank = ATIV4V5SetBank;
- pATI->BankInfo.SetSourceBank = ATIV4V5SetRead;
- pATI->BankInfo.SetDestinationBank = ATIV4V5SetWrite;
- pATI->BankInfo.SetSourceAndDestinationBanks = ATIV4V5SetReadWrite;
- break;
-
- case ATI_ADAPTER_XL:
- pATI->DAC = ATI_DAC_SC11483;
- break;
-
- case ATI_ADAPTER_8514A:
- pATI->VideoRAM =
- videoRamSizes[GetBits(inw(SUBSYS_STAT), _8PLANE) + 2];
- break;
-
- case ATI_ADAPTER_MACH8:
- pATI->VideoRAM =
- videoRamSizes[GetBits(inw(CONFIG_STATUS_1), MEM_INSTALLED) + 2];
- break;
-
- case ATI_ADAPTER_MACH32:
- IOValue = inw(CONFIG_STATUS_1);
- pATI->DAC = ATI_DAC(GetBits(IOValue, DACTYPE), 0);
- pATI->MemoryType = GetBits(IOValue, MEM_TYPE);
-
- IOValue = inw(MISC_OPTIONS);
- pATI->VideoRAM =
- videoRamSizes[GetBits(IOValue, MEM_SIZE_ALIAS) + 2];
-
- /*
- * The 68800-6 doesn't necessarily report the correct video memory
- * size.
- */
- if ((pATI->Chip == ATI_CHIP_68800_6) && (pATI->VideoRAM == 1024))
- pATI->VideoRAM = ATIMach32videoRam();
-
- break;
-
-#endif /* AVOID_CPIO */
-
case ATI_ADAPTER_MACH64:
do
{
@@ -1035,13 +682,6 @@ ATIPreInit
* For Mach64 adapters, pick up, from the BIOS, the type of programmable
* clock generator (if any), and various information about it.
*/
-
-#ifndef AVOID_CPIO
-
- if (pATI->Chip >= ATI_CHIP_88800GXC)
-
-#endif /* AVOID_CPIO */
-
{
CARD16 ClockDac;
@@ -1161,9 +801,7 @@ ATIPreInit
* accelerator modes.
*/
if ((pATI->ProgrammableClock == ATI_CLOCK_ICS2595) &&
- (pATI->DAC == ATI_DAC_IBMRGB514) &&
- (pScreenInfo->depth >= 8) &&
- (pATI->Chipset == ATI_CHIPSET_ATI))
+ (pATI->DAC == ATI_DAC_IBMRGB514))
pATI->ProgrammableClock = ATI_CLOCK_IBMRGB514;
pATI->ClockDescriptor =
@@ -1414,29 +1052,10 @@ ATIPreInit
ATIUnlock(pATI); /* Unlock registers */
-#ifndef AVOID_CPIO
-
- /* Sometimes, the BIOS lies about the chip */
- if ((pATI->Chip >= ATI_CHIP_28800_4) && (pATI->Chip <= ATI_CHIP_28800_6))
- {
- IOValue = GetBits(ATIGetExtReg(0xAAU), 0x0FU) +
- (ATI_CHIP_28800_4 - 4);
- if ((IOValue <= ATI_CHIP_28800_6) && (IOValue > pATI->Chip))
- pATI->Chip = IOValue;
- }
-
-#endif /* AVOID_CPIO */
-
/* Report what was found */
xf86DrvMsg(pScreenInfo->scrnIndex, X_PROBED,
"%s graphics controller detected.\n", ATIChipNames[pATI->Chip]);
-#ifndef AVOID_CPIO
-
- if ((pATI->Chip >= ATI_CHIP_68800) && (pATI->Chip != ATI_CHIP_68800_3))
-
-#endif /* AVOID_CPIO */
-
{
Message = Buffer + snprintf(Buffer, SizeOf(Buffer), "Chip type %04X",
pATI->ChipType);
@@ -1458,19 +1077,12 @@ ATIPreInit
Buffer, pATI->ChipClass, pATI->ChipRevision);
}
-#ifndef AVOID_CPIO
-
- if (pATI->Adapter >= ATI_ADAPTER_MACH8)
-
-#endif /* AVOID_CPIO */
-
{
Message = Buffer + snprintf(Buffer, SizeOf(Buffer),
"%s bus interface detected", ATIBusNames[pATI->BusType]);
#ifndef AVOID_CPIO
- if (pATI->Adapter >= ATI_ADAPTER_MACH64)
{
Message += snprintf(Message, Buffer + SizeOf(Buffer) - Message,
"; %s I/O base is 0x%04lX",
@@ -1605,14 +1217,6 @@ ATIPreInit
/*
* Set colour gamma.
*/
-
-#ifndef AVOID_CPIO
-
- if (pScreenInfo->depth > 1)
-
-#endif /* AVOID_CPIO */
-
- {
if (!xf86SetGamma(pScreenInfo, defaultGamma))
{
ATILock(pATI);
@@ -1620,7 +1224,6 @@ ATIPreInit
ATIUnmapApertures(pScreenInfo->scrnIndex, pATI);
return FALSE;
}
- }
pATI->depth = pScreenInfo->depth;
pATI->bitsPerPixel = pScreenInfo->bitsPerPixel;
@@ -1631,14 +1234,6 @@ ATIPreInit
* Determine which CRT controller to use for video modes.
*/
-#ifndef AVOID_CPIO
-
- if ((pATI->Chip >= ATI_CHIP_88800GXC) &&
- (pATI->depth >= 8) &&
- (pATI->Chipset == ATI_CHIPSET_ATI))
-
-#endif /* AVOID_CPIO */
-
{
pATI->NewHW.crtc = ATI_CRTC_MACH64;
@@ -1682,14 +1277,6 @@ ATIPreInit
#ifndef AVOID_CPIO
- else
- {
- pATI->NewHW.crtc = ATI_CRTC_VGA;
-
- xf86DrvMsg(pScreenInfo->scrnIndex, X_INFO,
- "Using VGA CRTC.\n");
- }
-
/* Complain if VGA is needed but not there */
if ((pATI->NewHW.crtc == ATI_CRTC_VGA) || !pATI->OptionLinear)
{
@@ -2317,31 +1904,12 @@ ATIPreInit
#ifndef AVOID_CPIO
AcceleratorVideoRAM = pScreenInfo->videoRam;
- if (pATI->Chip == ATI_CHIP_VGA)
- {
- if (pATI->depth <= 4)
- VGAVideoRAM = 256;
- else
- VGAVideoRAM = 64;
-
- /* For VGA, allow a lower override */
- if ((pGDev->videoRam > 0) && (pGDev->videoRam < VGAVideoRAM))
- VGAVideoRAM = pGDev->videoRam;
- }
- else if (pATI->CPIO_VGAWonder)
+ if (pATI->CPIO_VGAWonder)
{
/*
* XXX There's an assumption here that the values retrieved are those
* set by BIOS initialisation.
*/
- if (pATI->Chip <= ATI_CHIP_18800_1)
- {
- VGAVideoRAM =
- videoRamSizes[GetBits(ATIGetExtReg(0xBBU), 0x20U) + 1];
- if (AcceleratorVideoRAM > 512)
- AcceleratorVideoRAM = 512;
- }
- else
{
IOValue = ATIGetExtReg(0xB0U);
if (IOValue & 0x08U)
@@ -2359,30 +1927,6 @@ ATIPreInit
if (!AcceleratorVideoRAM)
{
pScreenInfo->videoRam = pATI->VideoRAM = VGAVideoRAM;
-
- /*
- * VGA Wonder V3's, V4's and V5's don't appear to support banking in
- * planar modes.
- */
- if ((pATI->depth <= 4) &&
- (pATI->Chip <= ATI_CHIP_18800_1) &&
- (VGAVideoRAM > 256))
- {
- if (pATI->OptionDevel)
- {
- xf86DrvMsg(pScreenInfo->scrnIndex, X_NOTICE,
- "Virtual resolutions requiring more than %s kB\n of video"
- " memory might not function properly.\n",
- (pATI->depth == 1) ? "64" : "256");
- }
- else
- {
- xf86DrvMsg(pScreenInfo->scrnIndex, X_NOTICE,
- "VideoRAM reduced to 256 kB due to hardware"
- " limitations.\n");
- pScreenInfo->videoRam = 256;
- }
- }
}
else if ((pATI->NewHW.crtc == ATI_CRTC_MACH64) ||
(pATI->Chip >= ATI_CHIP_264CT))
@@ -2390,13 +1934,6 @@ ATIPreInit
#endif /* AVOID_CPIO */
{
-
-#ifndef AVOID_CPIO
-
- if (pATI->depth >= 8)
-
-#endif /* AVOID_CPIO */
-
{
/* Get adapter's linear aperture configuration */
pATIHW->config_cntl = inr(CONFIG_CNTL);
@@ -2598,15 +2135,6 @@ ATIPreInit
pATI->UseSmallApertures = TRUE;
/* Set banking functions */
- if (pATI->depth <= 4)
- {
- pATI->NewHW.SetBank = ATIMach64SetBankPlanar;
- pATI->BankInfo.SetSourceBank = ATIMach64SetReadPlanar;
- pATI->BankInfo.SetDestinationBank = ATIMach64SetWritePlanar;
- pATI->BankInfo.SetSourceAndDestinationBanks =
- ATIMach64SetReadWritePlanar;
- }
- else
{
pATI->NewHW.SetBank = ATIMach64SetBankPacked;
pATI->BankInfo.SetSourceBank = ATIMach64SetReadPacked;
@@ -2688,8 +2216,7 @@ ATIPreInit
* However, it's possible that there is more video memory than VGA Wonder
* can architecturally handle.
*/
- if (((pATI->Chip < ATI_CHIP_68800) || (pATI->Chip > ATI_CHIP_68800AX)) &&
- (AcceleratorVideoRAM < pScreenInfo->videoRam))
+ if ((AcceleratorVideoRAM < pScreenInfo->videoRam))
{
if (pATI->OptionDevel)
{
@@ -2780,12 +2307,6 @@ ATIPreInit
}
}
-#ifndef AVOID_CPIO
-
- if (pATI->Adapter >= ATI_ADAPTER_MACH32)
-
-#endif /* AVOID_CPIO */
-
{
if (pATI->Chip >= ATI_CHIP_264CT)
ATIReportMemory(pScreenInfo, pATI,
@@ -2798,20 +2319,6 @@ ATIPreInit
ATIMemoryTypeNames_Mach[pATI->MemoryType]);
}
-#ifndef AVOID_CPIO
-
- else if (pATI->Adapter >= ATI_ADAPTER_V3)
- {
- ATIReportMemory(pScreenInfo, pATI,
- (ATIGetExtReg(0xB7U) & 0x04U) ? "DRAM" : "VRAM");
- }
- else
- {
- ATIReportMemory(pScreenInfo, pATI, "video memory");
- }
-
-#endif /* AVOID_CPIO */
-
/*
* Finish banking setup. This needs to be fixed to not assume the mode on
* entry is a VGA mode. XXX
@@ -2840,18 +2347,11 @@ ATIPreInit
else
{
pATIHW->crtc = ATI_CRTC_VGA;
- if ((pATI->Chip >= ATI_CHIP_88800GXC) &&
- (pATI->LockData.crtc_gen_cntl & CRTC_EXT_DISP_EN))
+ if ((pATI->LockData.crtc_gen_cntl & CRTC_EXT_DISP_EN))
{
pATIHW->crtc = ATI_CRTC_MACH64;
}
- if (pATI->depth <= 4)
- {
- pATI->BankInfo.nBankDepth = 1;
- pATI->NewHW.nPlane = 4;
- }
- else
{
pATI->BankInfo.nBankDepth = pATI->depth;
pATI->NewHW.nPlane = 1;
@@ -2867,13 +2367,7 @@ ATIPreInit
pATI->NewHW.nBank = ATIDivide(pATI->VideoRAM,
pATI->NewHW.nPlane * pATI->BankInfo.BankSize, 10, 1);
- if (pATI->VGAAdapter == ATI_ADAPTER_VGA)
- {
- pATIHW->SetBank = pATI->NewHW.SetBank =
- (ATIBankProcPtr)NoopDDA;
- pATIHW->nBank = pATI->NewHW.nBank = 1;
- }
- else if (!pATI->UseSmallApertures)
+ if (!pATI->UseSmallApertures)
{
pATIHW->SetBank = pATI->NewHW.SetBank;
}
@@ -2911,12 +2405,6 @@ ATIPreInit
"Cannot shadow a banked frame buffer.\n");
pATI->OptionShadowFB = FALSE;
}
- else if (pATI->depth < 8)
- {
- xf86DrvMsg(pScreenInfo->scrnIndex, X_WARNING,
- "Cannot shadow a planar frame buffer.\n");
- pATI->OptionShadowFB = FALSE;
- }
else
#endif /* AVOID_CPIO */
@@ -2982,12 +2470,6 @@ ATIPreInit
Denominator = pATI->ClockDescriptor.MinM *
pATI->XCLKReferenceDivider * pATI->ReferenceDenominator;
-#ifndef AVOID_CPIO
-
- if (pATI->depth >= 8)
-
-#endif /* AVOID_CPIO */
-
{
Denominator *= pATI->bitsPerPixel / 4;
}
@@ -3092,19 +2574,7 @@ ATIPreInit
#ifndef AVOID_CPIO
- /*
- * 80 MHz is too high in some cases. Limit 18800-x's to 40
- * MHz. Don't exceed the memory clock on VGA Wonder capables
- * with less than 1 MB, if using a packed mode.
- */
- if ((pATI->Chip == ATI_CHIP_18800) ||
- (pATI->Chip == ATI_CHIP_18800_1))
- {
- DefaultmaxClock = 40000;
- }
- else if (pATI->CPIO_VGAWonder &&
- (pATI->VideoRAM < 1024) &&
- (pATI->depth >= 8))
+ if (pATI->CPIO_VGAWonder && (pATI->VideoRAM < 1024))
{
DefaultmaxClock =
(GetBits(BIOSByte(0x44U), 0x04U) * 5000) + 40000;
@@ -3144,30 +2614,10 @@ ATIPreInit
* Mode validation.
*/
-#ifdef AVOID_CPIO
-
if (pATI->Chip >= ATI_CHIP_264CT)
{
minPitch = 8;
}
-
-#else /* AVOID_CPIO */
-
- if ((pATI->depth >= 8) && (pATI->Chip >= ATI_CHIP_264CT))
- {
- minPitch = 8;
- }
- else if (pATI->CPIO_VGAWonder &&
- (pATI->Chip <= ATI_CHIP_18800_1) &&
- (pATI->VideoRAM == 256) &&
- (pATI->depth >= 8))
- {
- minPitch = 32; /* Very strange, but true */
- maxPitch = 0x3FU;
- }
-
-#endif /* AVOID_CPIO */
-
else
{
minPitch = 16;
@@ -3175,12 +2625,6 @@ ATIPreInit
pATI->pitchInc = minPitch;
-#ifndef AVOID_CPIO
-
- if (pATI->depth >= 8)
-
-#endif /* AVOID_CPIO */
-
{
pATI->pitchInc *= pATI->bitsPerPixel;
}
@@ -3191,12 +2635,6 @@ ATIPreInit
#ifndef AVOID_CPIO
case ATI_CRTC_VGA:
- /*
- * IBM's VGA doesn't allow for interlaced modes.
- */
- if (pATI->Adapter <= ATI_ADAPTER_VGA)
- ATIClockRange.interlaceAllowed = FALSE;
-
pScreenInfo->maxHValue = (0xFFU + 1) << 3; /* max HTotal */
/*
@@ -3205,7 +2643,6 @@ ATIPreInit
* Finer-grained checks are done in ATIValidateMode().
*/
pScreenInfo->maxVValue = 0x03FFU + 1;
- if (pATI->Adapter > ATI_ADAPTER_VGA)
{
pScreenInfo->maxVValue <<= 1;
if (ATIClockRange.interlaceAllowed &&
@@ -3213,20 +2650,6 @@ ATIPreInit
pScreenInfo->maxVValue <<= 1;
}
- /*
- * 18800-x and 28800-x do not support interlaced modes when the
- * scanline pitch is 2048 pixels or more. For 18800-x's with 256
- * kB of video memory, the limit for 8bpp is 1024.
- */
- if (ATIClockRange.interlaceAllowed &&
- (pATI->Chip <= ATI_CHIP_28800_6))
- {
- if (minPitch == 32)
- pATI->MaximumInterlacedPitch = 0x1FU * 32;
- else
- pATI->MaximumInterlacedPitch = 0x7FU * minPitch;
- }
-
Strategy |= LOOKUP_CLKDIV2;
break;
diff --git a/src/atistruct.h b/src/atistruct.h
index fbb23910..698ec016 100644
--- a/src/atistruct.h
+++ b/src/atistruct.h
@@ -444,9 +444,6 @@ typedef struct _ATIRec
CARD32 config_cntl;
- /* Mach8/Mach32 registers */
- CARD16 clock_sel, misc_options, mem_bndry, mem_cfg;
-
/* VGA Wonder registers */
CARD8 a6, ab, b1, b4, b5, b6, b8, b9, be;
@@ -462,8 +459,6 @@ typedef struct _ATIRec
/* Mode data */
ATIHWRec OldHW, NewHW;
- int MaximumInterlacedPitch;
- Bool InterlacedSeen;
/*
* Resource Access Control entity index.
diff --git a/src/ativalid.c b/src/ativalid.c
index c2539a2d..25ad7182 100644
--- a/src/ativalid.c
+++ b/src/ativalid.c
@@ -48,7 +48,6 @@ ATIValidMode
{
ScrnInfoPtr pScreenInfo = xf86Screens[iScreen];
ATIPtr pATI = ATIPTR(pScreenInfo);
- Bool InterlacedSeen;
int HBlankWidth, HAdjust, VScan, VInterlace;
#ifndef AVOID_CPIO
@@ -59,31 +58,6 @@ ATIValidMode
if (flags & MODECHECK_FINAL)
{
- /*
- * This is the final check before the common layer accepts a mode.
- * pScreenInfo->displayWidth is set to the proposed virtual pitch
- * should the mode be accepted. The only check needed here is for
- * 18800's and 28800's, which don't support interlaced modes if the
- * pitch is over half the chipset's maximum pitch.
- */
- if (pATI->MaximumInterlacedPitch)
- {
- /*
- * Ensure no interlaced modes have a scanline pitch larger than the
- * limit.
- */
- if (pMode->Flags & V_INTERLACE)
- InterlacedSeen = TRUE;
- else
- InterlacedSeen = pATI->InterlacedSeen;
-
- if (InterlacedSeen &&
- (pScreenInfo->displayWidth > pATI->MaximumInterlacedPitch))
- return MODE_INTERLACE_WIDTH;
-
- pATI->InterlacedSeen = InterlacedSeen;
- }
-
return MODE_OK;
}
@@ -214,12 +188,6 @@ ATIValidMode
if ((VDisplay > 2048) || (VTotal > 2050))
return MODE_BAD_VVALUE;
- if (pATI->Adapter != ATI_ADAPTER_VGA)
- break;
-
- if ((VDisplay > 1024) || (VTotal > 1025))
- return MODE_BAD_VVALUE;
-
break;
#endif /* AVOID_CPIO */
diff --git a/src/ativga.c b/src/ativga.c
index 5678c6e3..7332431c 100644
--- a/src/ativga.c
+++ b/src/ativga.c
@@ -164,265 +164,6 @@ ATIVGASave
}
/*
- * ATIVGACalculate --
- *
- * This function fills in the VGA portion of an ATIHWRec.
- */
-void
-ATIVGACalculate
-(
- ATIPtr pATI,
- ATIHWPtr pATIHW,
- DisplayModePtr pMode
-)
-{
- int Index, VDisplay;
-
- /* If not already done, adjust horizontal timings */
- if (!pMode->CrtcHAdjusted)
- {
- pMode->CrtcHAdjusted = TRUE;
- pMode->CrtcHDisplay = (pMode->HDisplay >> 3) - 1;
- pMode->CrtcHBlankStart = (pMode->HDisplay >> 3);
- if ((pATI->Chip == ATI_CHIP_18800_1) ||
- (pATI->Chip >= ATI_CHIP_264CT))
- pMode->CrtcHBlankStart--;
- pMode->CrtcHSyncStart = pMode->HSyncStart >> 3;
- if (pATI->LCDPanelID >= 0)
- pMode->CrtcHSyncStart--;
- pMode->CrtcHSyncEnd = pMode->HSyncEnd >> 3;
- if (pATI->LCDPanelID >= 0)
- pMode->CrtcHSyncEnd--;
- pMode->CrtcHBlankEnd = (pMode->HTotal >> 3) - 1;
- pMode->CrtcHTotal = (pMode->HTotal >> 3) - 5;
- pMode->CrtcHSkew = pMode->HSkew;
-
- /* Check sync pulse width */
- Index = pMode->CrtcHSyncEnd - pMode->CrtcHSyncStart - 0x1F;
- if (Index > 0)
- {
- pMode->CrtcHSyncStart += Index / 2;
- pMode->CrtcHSyncEnd = pMode->CrtcHSyncStart + 0x1F;
- }
-
- /* Check blank pulse width */
- Index = pMode->CrtcHBlankEnd - pMode->CrtcHBlankStart - 0x3F;
- if (Index > 0)
- {
- if ((pMode->CrtcHBlankEnd - Index) > pMode->CrtcHSyncEnd)
- {
- pMode->CrtcHBlankStart += Index / 2;
- if (pMode->CrtcHBlankStart >= pMode->CrtcHSyncStart)
- pMode->CrtcHBlankStart = pMode->CrtcHSyncStart - 1;
- pMode->CrtcHBlankEnd = pMode->CrtcHBlankStart + 0x3F;
- }
- else
- {
- Index -= 0x40;
- if (Index > 0)
- {
- pMode->CrtcHBlankStart += Index / 2;
- if (pMode->CrtcHBlankStart >= pMode->CrtcHSyncStart)
- pMode->CrtcHBlankStart = pMode->CrtcHSyncStart - 1;
- pMode->CrtcHBlankEnd = pMode->CrtcHBlankStart + 0x7F;
- }
- }
- }
- }
-
- /*
- * Because of the use of CRTC[23] bit 0x04's for vertical doubling, it is
- * necessary to always re-adjust vertical timings here.
- */
- pMode->CrtcVDisplay = pMode->VDisplay;
- pMode->CrtcVBlankStart = pMode->VDisplay;
- pMode->CrtcVSyncStart = pMode->VSyncStart;
- pMode->CrtcVSyncEnd = pMode->VSyncEnd;
- pMode->CrtcVBlankEnd = pMode->VTotal;
- pMode->CrtcVTotal = pMode->VTotal;
-
- /* Adjust for doublescanned modes */
- if (pMode->Flags & V_DBLSCAN)
- {
- pMode->CrtcVDisplay <<= 1;
- pMode->CrtcVBlankStart <<= 1;
- pMode->CrtcVSyncStart <<= 1;
- pMode->CrtcVSyncEnd <<= 1;
- pMode->CrtcVBlankEnd <<= 1;
- pMode->CrtcVTotal <<= 1;
- }
-
- /* Adjust for multiscanned modes */
- if (pMode->VScan > 1)
- {
- pMode->CrtcVDisplay *= pMode->VScan;
- pMode->CrtcVBlankStart *= pMode->VScan;
- pMode->CrtcVSyncStart *= pMode->VScan;
- pMode->CrtcVSyncEnd *= pMode->VScan;
- pMode->CrtcVBlankEnd *= pMode->VScan;
- pMode->CrtcVTotal *= pMode->VScan;
- }
-
- /* Set up miscellaneous output register value */
- pATIHW->genmo = 0x23U;
- if ((pMode->Flags & (V_PHSYNC | V_NHSYNC)) &&
- (pMode->Flags & (V_PVSYNC | V_NVSYNC)))
- {
- if (pMode->Flags & V_NHSYNC)
- pATIHW->genmo |= 0x40U;
- if (pMode->Flags & V_NVSYNC)
- pATIHW->genmo |= 0x80U;
- }
- else
- {
- pMode->Flags &= ~(V_PHSYNC | V_NHSYNC | V_PVSYNC | V_NVSYNC);
-
- if (pATI->OptionPanelDisplay && (pATI->LCDPanelID >= 0))
- VDisplay = pATI->LCDVertical;
- else
- VDisplay = pMode->CrtcVDisplay;
-
- if (VDisplay < 400)
- {
- pMode->Flags |= V_PHSYNC | V_NVSYNC;
- pATIHW->genmo |= 0x80U;
- }
- else if (VDisplay < 480)
- {
- pMode->Flags |= V_NHSYNC | V_PVSYNC;
- pATIHW->genmo |= 0x40U;
- }
- else if (VDisplay < 768)
- {
- pMode->Flags |= V_NHSYNC | V_NVSYNC;
- pATIHW->genmo |= 0xC0U;
- }
- else
- {
- pMode->Flags |= V_PHSYNC | V_PVSYNC;
- }
- }
-
- /* Adjust for interlaced modes */
- if ((pMode->Flags & V_INTERLACE) && (pATI->Chip < ATI_CHIP_264CT))
- {
- pMode->CrtcVDisplay >>= 1;
- pMode->CrtcVBlankStart >>= 1;
- pMode->CrtcVSyncStart >>= 1;
- pMode->CrtcVSyncEnd >>= 1;
- pMode->CrtcVBlankEnd >>= 1;
- pMode->CrtcVTotal >>= 1;
- }
-
- if (pMode->CrtcVTotal > 1024)
- {
- pATIHW->crt[23] |= 0x04U;
- pMode->CrtcVDisplay >>= 1;
- pMode->CrtcVBlankStart >>= 1;
- pMode->CrtcVSyncStart >>= 1;
- pMode->CrtcVSyncEnd >>= 1;
- pMode->CrtcVBlankEnd >>= 1;
- pMode->CrtcVTotal >>= 1;
- }
- else
- {
- pATIHW->crt[23] &= ~0x04U;
- }
-
- pMode->CrtcVDisplay--;
- if (pATI->Chip == ATI_CHIP_18800)
- pMode->CrtcVBlankStart++;
- else
- pMode->CrtcVBlankStart--;
- if (pATI->LCDPanelID >= 0)
- {
- pMode->CrtcVSyncStart--;
- pMode->CrtcVSyncEnd--;
- }
- pMode->CrtcVBlankEnd--;
- if (pATI->Chip < ATI_CHIP_264CT)
- pMode->CrtcVBlankEnd--;
- pMode->CrtcVTotal -= 2;
- pMode->CrtcVAdjusted = TRUE; /* Redundant */
-
- /* Check sync pulse width */
- Index = pMode->CrtcVSyncEnd - pMode->CrtcVSyncStart - 0x0F;
- if (Index > 0)
- {
- pMode->CrtcVSyncStart += Index / 2;
- pMode->CrtcVSyncEnd = pMode->CrtcVSyncStart + 0x0F;
- }
-
- /* Check blank pulse width */
- Index = pMode->CrtcVBlankEnd - pMode->CrtcVBlankStart - 0x00FF;
- if (Index > 0)
- {
- if ((pMode->CrtcVBlankEnd - Index) > pMode->CrtcVSyncEnd)
- {
- pMode->CrtcVBlankStart += Index / 2;
- if (pMode->CrtcVBlankStart >= pMode->CrtcVSyncStart)
- pMode->CrtcVBlankStart = pMode->CrtcVSyncStart - 1;
- pMode->CrtcVBlankEnd = pMode->CrtcVBlankStart + 0x00FF;
- }
- else
- {
- Index -= 0x0100;
- if (Index > 0)
- {
- pMode->CrtcVBlankStart += Index / 2;
- if (pMode->CrtcVBlankStart >= pMode->CrtcVSyncStart)
- pMode->CrtcVBlankStart = pMode->CrtcVSyncStart - 1;
- pMode->CrtcVBlankEnd = pMode->CrtcVBlankStart + 0x01FF;
- }
- }
- }
-
- /* Set up sequencer register values */
- if (pMode->Flags & V_CLKDIV2)
- pATIHW->seq[1] = 0x09U;
- else
- pATIHW->seq[1] = 0x01U;
-
- /* Set up CRTC register values */
- pATIHW->crt[0] = pMode->CrtcHTotal;
- pATIHW->crt[1] = pMode->CrtcHDisplay;
- pATIHW->crt[2] = pMode->CrtcHBlankStart;
- pATIHW->crt[3] = (pMode->CrtcHBlankEnd & 0x1FU) | 0x80U;
- Index = ((pMode->CrtcHSkew << 2) + 0x10U) & ~0x1FU;
- if (Index < 0x0080)
- pATIHW->crt[3] |= Index;
- pATIHW->crt[4] = pMode->CrtcHSyncStart;
- pATIHW->crt[5] = ((pMode->CrtcHBlankEnd & 0x20U) << 2) |
- ((pMode->CrtcHSyncEnd & 0x1FU) );
- pATIHW->crt[6] = pMode->CrtcVTotal & 0xFFU;
- pATIHW->crt[7] = ((pMode->CrtcVTotal & 0x0100U) >> 8) |
- ((pMode->CrtcVDisplay & 0x0100U) >> 7) |
- ((pMode->CrtcVSyncStart & 0x0100U) >> 6) |
- ((pMode->CrtcVBlankStart & 0x0100U) >> 5) |
- 0x10U |
- ((pMode->CrtcVTotal & 0x0200U) >> 4) |
- ((pMode->CrtcVDisplay & 0x0200U) >> 3) |
- ((pMode->CrtcVSyncStart & 0x0200U) >> 2);
- pATIHW->crt[9] = ((pMode->CrtcVBlankStart & 0x0200U) >> 4) | 0x40U;
- /*
- * Doublescanned modes are missing the top scanline. Convert
- * doublescanning to multiscanning, using the doublescan bit only as a last
- * resort.
- */
- if ((Index = pMode->VScan) <= 0)
- Index = 1;
- if (pMode->Flags & V_DBLSCAN)
- Index <<= 1;
- Index--;
- pATIHW->crt[9] |= (Index & 0x1FU) | ((Index & 0x20U) << 2);
- pATIHW->crt[16] = pMode->CrtcVSyncStart & 0xFFU;
- pATIHW->crt[17] = (pMode->CrtcVSyncEnd & 0x0FU) | 0x20U;
- pATIHW->crt[18] = pMode->CrtcVDisplay & 0xFFU;
- pATIHW->crt[21] = pMode->CrtcVBlankStart & 0xFFU;
- pATIHW->crt[22] = pMode->CrtcVBlankEnd & 0xFFU;
-}
-
-/*
* ATIVGASet --
*
* This function is called to load the VGA portion of a video state.
diff --git a/src/ativga.h b/src/ativga.h
index 90c3ef41..a02a2d01 100644
--- a/src/ativga.h
+++ b/src/ativga.h
@@ -31,7 +31,6 @@
extern void ATIVGAPreInit(ATIPtr, ATIHWPtr);
extern void ATIVGASave(ATIPtr, ATIHWPtr);
-extern void ATIVGACalculate(ATIPtr, ATIHWPtr, DisplayModePtr);
extern void ATIVGASet(ATIPtr, ATIHWPtr);
extern void ATIVGASaveScreen(ATIPtr, int);
diff --git a/src/ativgaio.h b/src/ativgaio.h
index 0409a727..c73e8ae1 100644
--- a/src/ativgaio.h
+++ b/src/ativgaio.h
@@ -29,9 +29,11 @@
#define ___ATIVGAIO_H___ 1
-#include "atiio.h"
+#include "atiregs.h"
#include "atipriv.h"
+#include "compiler.h"
+
#ifndef AVOID_CPIO
extern void ATISetVGAIOBase(ATIPtr, const CARD8);
diff --git a/src/atiwonder.c b/src/atiwonder.c
index e6a4ec26..6822872f 100644
--- a/src/atiwonder.c
+++ b/src/atiwonder.c
@@ -132,138 +132,6 @@ ATIVGAWonderSave
}
/*
- * ATIVGAWonderCalculate --
- *
- * This function fills in the VGA Wonder portion of an ATIHWRec structure
- * occurrence.
- */
-void
-ATIVGAWonderCalculate
-(
- ATIPtr pATI,
- ATIHWPtr pATIHW,
- DisplayModePtr pMode
-)
-{
- /* Set up the default horizontal display enable skew */
- if ((pATI->Chip >= ATI_CHIP_28800_2) && (pATI->Chip <= ATI_CHIP_28800_6) &&
- !(pMode->Flags & V_HSKEW))
- {
- /*
- * Modes using the higher clock frequencies need a non-zero Display
- * Enable Skew. The following number has been empirically determined
- * to be somewhere between 4.2 and 4.7 MHz.
- */
-# define DisplayEnableSkewThreshold 4500
-
- /* Set a reasonable default Display Enable Skew */
- pMode->HSkew = pMode->CrtcHSkew =
- ATIDivide(pMode->SynthClock, DisplayEnableSkewThreshold, 0, 0);
- }
- pMode->Flags |= V_HSKEW;
-
- /*
- * Fill in mode-specific VGA Wonder data.
- */
- pATIHW->b0 = 0x00U;
- if (pATI->depth >= 8)
- pATIHW->b0 = 0x20U;
- if (pATI->Chip >= ATI_CHIP_28800_2)
- {
- if (pATI->VideoRAM > 512)
- pATIHW->b0 |= 0x08U;
- else if (pATI->VideoRAM > 256)
- pATIHW->b0 |= 0x10U;
- }
- else if (pATI->depth <= 4)
- {
- if (pATI->VideoRAM > 256)
- pATIHW->b0 |= 0x08U;
- }
- else
- {
- if (pATI->VideoRAM > 256)
- pATIHW->b0 |= 0x18U;
- else
- pATIHW->b0 |= 0x06U;
- }
- pATIHW->b1 = ATIGetExtReg(0xB1U) & 0x04U;
- /*
- * Setting the following bit causes hangs on return to text mode from
- * packed modes on 18800-1's. The hang occurs because the adapter's I/O
- * response is completely disabled when the register is rewritten. The
- * adapter can then only be re-enabled with a powerdown. The bit, when on,
- * blanks out the overscan.
- */
- if ((pATI->Chip == ATI_CHIP_18800_1) && (pATI->depth >= 8))
- pATIHW->b5 = 0x00U;
- else
- pATIHW->b5 = 0x01U;
- pATIHW->b8 = ATIGetExtReg(0xB8U) & 0xC0U;
- pATIHW->b9 = ATIGetExtReg(0xB9U) & 0x7FU;
- pATIHW->bd = ATIGetExtReg(0xBDU) & 0x02U;
- if (pATI->Chip <= ATI_CHIP_18800)
- pATIHW->b2 = ATIGetExtReg(0xB2U) & 0xC0U;
- else
- {
- pATIHW->b2 = 0x00U;
- pATIHW->be = (ATIGetExtReg(0xBEU) & 0x30U) | 0x09U;
- if (pATI->Chip >= ATI_CHIP_28800_2)
- {
- pATIHW->a6 = (ATIGetExtReg(0xA6U) & 0x38U) | 0x04U;
- pATIHW->a7 = (ATIGetExtReg(0xA7U) & 0xBEU) ;
- pATIHW->ac = (ATIGetExtReg(0xACU) & 0x8EU) ;
- }
- }
- if (pMode->Flags & V_INTERLACE)
- { /* Enable interlace */
- if (pATI->Chip <= ATI_CHIP_18800)
- pATIHW->b2 |= 0x01U;
- else
- pATIHW->be |= 0x02U;
- }
-#if 0 /* This is no longer needed but is left in for reference */
- if (pMode->Flags & V_DBLSCAN) /* Enable doublescan */
- pATIHW->b1 |= 0x08U;
-#endif
- if (pATI->OptionCSync || (pMode->Flags & (V_CSYNC | V_PCSYNC)))
- pATIHW->bd |= 0x08U; /* Enable composite sync */
- if (pMode->Flags & V_NCSYNC)
- pATIHW->bd |= 0x09U; /* Invert composite sync */
- if (pMode->HSkew > 0)
- {
- if (pMode->HSkew <= 3)
- pATIHW->b5 |= 0x04U;
- else if (pATI->Chip >= ATI_CHIP_28800_2)
- switch ((pMode->HSkew + 4) >> 3)
- {
- case 1: /* Use ATI override */
- pATIHW->crt[3] &= ~0x60U;
- pATIHW->b0 |= 0x01U;
- break;
- case 2: /* Use ATI override */
- pATIHW->crt[3] &= ~0x60U;
- pATIHW->a6 |= 0x01U;
- break;
- case 3:
- pATIHW->crt[3] |= 0x60U;
- break;
- case 4:
- pATIHW->a7 |= 0x40U;
- break;
- case 5:
- pATIHW->ac |= 0x10U;
- break;
- case 6:
- pATIHW->ac |= 0x20U;
- break;
- default:
- break;
- }
- }
-}
-
-/*
* ATIVGAWonderSet --
*
* This function loads the VGA Wonder portion of a video state.
diff --git a/src/atiwonder.h b/src/atiwonder.h
index 1412be22..2fe5e5ea 100644
--- a/src/atiwonder.h
+++ b/src/atiwonder.h
@@ -31,7 +31,6 @@
extern void ATIVGAWonderPreInit(ATIPtr, ATIHWPtr);
extern void ATIVGAWonderSave(ATIPtr, ATIHWPtr);
-extern void ATIVGAWonderCalculate(ATIPtr, ATIHWPtr, DisplayModePtr);
extern void ATIVGAWonderSet(ATIPtr, ATIHWPtr);
#endif /* AVOID_CPIO */