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path: root/src/intel_driver.h
AgeCommit message (Expand)AuthorFilesLines
2017-01-17Follow the HW spec to configure the buffer cache on Gen9+Zhao Yakui1-0/+1
2016-11-21Query the kernel API to check the EU counts of GPU deviceZhao Yakui1-0/+2
2016-11-18Add a new gpe function gen8_gpe_pipe_control() for GEN8Xiang, Haihao1-0/+6
2016-09-28Check whether there is a fully loaded HuC firmwareXiang, Haihao1-0/+1
2016-05-27Add some utility functions for i965_gpe_resourcesZhao Yakui1-0/+2
2016-05-09Add some utility functions for MI commands for GEN9Xiang, Haihao1-0/+19
2016-05-09Add a flag for skylake in struct intel_device_infoXiang, Haihao1-0/+5
2016-01-29KBL driver enablingPeng Chen1-0/+3
2015-12-07Initial support for Broxton in the intel-driverSirisha Muppavarapu1-0/+1
2015-03-05Do not print warnings on stdoutMichael Müller1-1/+1
2014-12-29Add new debug option for aub dumpZhenyu Wang1-0/+1
2014-12-14Add the override flag to assure that HEVC video command always uses BSD ring0...Zhao Yakui1-0/+1
2014-12-14HEVC: gen9_hcpd_ref_idx_state()Xiang, Haihao1-0/+1
2014-12-14Skl: Add the PCIIDs and initial driver-codec info for SklZhao Yakui1-0/+2
2014-09-30CHV: Add PCIID placeholders for CHVSean V Kelley1-0/+2
2014-06-06debug: add g_intel_debug_option_flags for simple driver debugZhao, Halley1-2/+7
2014-05-26Simplify some macrosXiang, Haihao1-266/+10
2014-05-26Add a new intel_device_info structureXiang, Haihao1-0/+16
2014-04-23clean up some assert in i965_drv_video.cZhao, Halley1-0/+7
2014-04-23va: User specified tiling and stride support.Zhao, Halley1-0/+1
2014-02-27New PCI IDs for BDWXiang, Haihao1-3/+10
2014-02-27Initialize the 8x8 sampler for AVS on BDWZhao Yakui1-0/+2
2014-02-27Add the PCI ids for BDWZhao Yakui1-0/+43
2013-11-13Workaround for SNBXiang, Haihao1-0/+2
2013-09-06Enable the Bay Trail platform.Zhao Halley1-1/+17
2013-07-01Check whether VEBOX is supported by the underlying OSXiang, Haihao1-0/+1
2013-06-25Revert "Make it built against the current upstream libdrm"Xiang, Haihao1-4/+0
2013-06-09More reserved PCI IDs for HaswellXiang, Haihao1-3/+53
2013-06-09Fix Haswell GT3Xiang, Haihao1-26/+28
2013-04-03Merge branch 'master' into stagingXiang, Haihao1-0/+1
2013-03-15Fix the initilization path and the termination path in reverseXiang, Haihao1-2/+3
2013-03-04Update PCI IDs for Haswell CRWXiang, Haihao1-9/+9
2013-03-04Update PCI IDs for Haswell CRWXiang, Haihao1-9/+9
2012-12-28Add IS_SNB_GT1/IS_SNB_GT2/IS_IVB_GT1/IS_IVB_GT2 and remove IS_HSW_ULT and IS_...Xiang, Haihao1-46/+52
2012-12-28Add IS_SNB_GT1/IS_SNB_GT2/IS_IVB_GT1/IS_IVB_GT2 and remove IS_HSW_ULT and IS_...Xiang, Haihao1-46/+52
2012-10-31VPP: Render target surface with background colorXiang, Haihao1-0/+2
2012-10-29Make it built against the current upstream libdrmXiang, Haihao1-0/+4
2012-10-24Make it built against the current upstream libdrmXiang, Haihao1-0/+4
2012-10-23Handle the MFX change between A stepping and B-stepping for haswellZhao Yakui1-0/+1
2012-10-23Add haswell PCI IDsGwenole Beauchesne1-1/+87
2012-10-23Handle the MFX change between A stepping and B-stepping for haswellZhao Yakui1-0/+1
2012-10-23Add PCI IDs for HaswellGwenole Beauchesne1-1/+87
2012-10-08Fix build with VA-API 0.32.0.Gwenole Beauchesne1-0/+1
2012-04-13Add support for new Ivybridge chipsetXiang, Haihao1-1/+3
2012-04-13Add support for new Ivybridge chipsetXiang, Haihao1-1/+3
2012-03-29Add WARN_ONCE() helper macro.Gwenole Beauchesne1-0/+8
2012-03-18Add WARN_ONCE() helper macro.Gwenole Beauchesne1-0/+8
2012-01-30Clear target surface with specified colorXiang, Haihao1-0/+2
2012-01-10Avoid depending on va_backend.h for some filesXiang, Haihao1-0/+5
2012-01-10Remove legacy DRI supportXiang, Haihao1-6/+0
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